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[/] [mem_ctrl/] [trunk/] [bench/] [richard/] [verilog/] [tst_asram.v] - Blame information for rev 28

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  OpenCores Memory Controller Testbench                      ////
////  Asynchronous memory devices tests                          ////
////  This file is being included by the main testbench          ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001, 2002 Richard Herveille                  ////
////                          richard@asics.ws                   ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: tst_asram.v,v 1.1 2002-03-06 15:10:34 rherveille Exp $
//
//  $Date: 2002-03-06 15:10:34 $
//  $Revision: 1.1 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
 
 
        ///////////////////////////////////////
        // Asynchronous memory sequential test
        //
 
        // 1) Fill entire SRAM memory using sequential accesses
        // 2) Test 8/16/32 bit wide asynchronous accesses
        // 2) Verify memory contents
        //
        // THIS IS A FULL MEMORY TEST, TAKES A WHILE
        task tst_amem_seq;
                parameter MAX_CYC_DELAY = 5;
                parameter MAX_STB_DELAY = 5;
 
                parameter [31:0] SRAM_STARTA = `SRAM_LOC;
                parameter [ 7:0] SRAM_SEL = SRAM_STARTA[28:21];
                parameter SRAM_TST_RUN = 1<<11; // entire sram memory
 
                integer n, cnt;
                reg [1:0] tmp;
                reg [31:0] my_adr;
                reg [31:0] my_dat;
 
                reg[1:0] bw;
                reg [31:0] csr_data, tms_data;
 
                integer cyc_delay, stb_delay;
 
                begin
 
                        $display("\n\n --- ASYNCHRONOUS MEMORY SEQUENTIAL/FILL TEST ---\n\n");
 
                        bw = 2;
                        for (bw = 0; bw < 3; bw = bw +1)
                        begin
                                csr_data = {
                                        8'h00,    //     reserved
                                        SRAM_SEL, // SEL base address (a[28:21] == 8'b0100_0000)
                                        4'h0,     //     reserved
                                        1'b0,     // PEN no parity
                                        1'b0,     // KRO ---
                                        1'b0,     // BAS ---
                                        1'b0,     // WP  no write protection
                                        2'b00,    // MS  ---
                                        bw,       // BW  Bus width
                                        3'h2,     // MEM memory type == asynchronous
                                        1'b1      // EN  enable chip select
                                };
 
                                tms_data = {
                                        6'h0,  // reserved
                                        6'h0,  // Twwd =  5ns =>  0ns
                                        4'h0,  // Twd  =  0ns =>  0ns
                                        4'h1,  // Twpw = 15ns => 20ns
                                        4'h0,  // Trdz =  8ns => 10ns
                                        8'h02  // Trdv = 20ns => 20ns
                                };
 
                                // program chip select registers
                                wbm.wb_write(0, 0, 32'h6000_0018, csr_data);      // program cs1 config register
                                wbm.wb_write(0, 0, 32'h6000_001c, tms_data);      // program cs1 timing register
 
                                // check written data
                                wbm.wb_cmp(0, 0, 32'h6000_0018, csr_data);
                                wbm.wb_cmp(0, 0, 32'h6000_001c, tms_data);
 
                                cyc_delay = 1;
                                stb_delay = 1;
                                for (cyc_delay = 0; cyc_delay < MAX_CYC_DELAY; cyc_delay = cyc_delay +1)
                                for (stb_delay = 0; stb_delay < MAX_STB_DELAY; stb_delay = stb_delay +1)
                                        begin
                                                $display("Asynchronous memory sequential test. CYC-delay = %d, STB-delay = %d, BW = %d", cyc_delay, stb_delay, bw);
 
                                                // fill srams
                                                tmp = ~(bw +1);
 
                                                my_dat = 0;
                                                for (n=0; n < (SRAM_TST_RUN<<tmp); n=n+1)
                                                        begin
                                                                my_adr = SRAM_STARTA + (n << bw);
 
                                                                cnt = (n >> tmp) + cyc_delay + stb_delay;
 
                                                                case (bw)
                                                                        2'b00: //  8bit asynchronous memory connected
                                                                                case (n[1:0])
                                                                                        2'b00: my_dat[7:0] = ~cnt[ 7:0];
                                                                                        2'b01: my_dat[7:0] = ~cnt[15:8];
                                                                                        2'b10: my_dat[7:0] =  cnt[ 7:0];
                                                                                        2'b11: my_dat[7:0] =  cnt[15:8];
                                                                                endcase
                                                                        2'b01: // 16bit asynchronous memory connected
                                                                                if (n[0])
                                                                                        my_dat[15:0] = cnt;
                                                                                else
                                                                                        my_dat[15:0] = ~cnt;
                                                                        2'b10: // 32bit asynchronous memory connected
                                                                                begin
                                                                                        my_dat[31:16] = cnt;
                                                                                        my_dat[15: 0] = ~cnt;
                                                                                end
                                                                        2'b11: // reserved
                                                                                begin
                                                                                end
                                                                endcase
 
                                                                wbm.wb_write(cyc_delay, stb_delay, my_adr, my_dat);
                                                        end
 
                                                // read srams
                                                my_dat = 0;
                                                for (n=0; n < SRAM_TST_RUN; n=n+1)
                                                        begin
                                                                my_adr = SRAM_STARTA + (n<<2); // always read 32bits
                                                                my_dat[31:16] =  (n + cyc_delay + stb_delay);
                                                                my_dat[15: 0] = ~(n + cyc_delay + stb_delay);
 
                                                                wbm.wb_cmp(cyc_delay, stb_delay, my_adr, my_dat);
                                                        end
                                        end
                        end
 
                        $display("\nAsynchronous memory sequential test ended");
 
                end
        endtask // tst_amem_seq
 
 
        ///////////////////////////////////////
        // Asynchronous memory back2back test
        //
 
        // 1) Test back-2-back read/write accesses to asynchronous memory
        task tst_amem_b2b;
                parameter MAX_CYC_DELAY = 5;
                parameter MAX_STB_DELAY = 5;
 
                parameter [31:0] SRAM_STARTA = `SRAM_LOC;
                parameter [ 7:0] SRAM_SEL = SRAM_STARTA[28:21];
                parameter SRAM_TST_RUN = 64; // only do a few accesses
 
                integer n, cnt;
                reg [1:0] tmp;
                reg [31:0] my_adr;
                reg [31:0] my_dat;
 
                reg [31:0] csr_data, tms_data;
 
                integer cyc_delay, stb_delay;
 
                begin
                        csr_data = {
                                8'h00,    //     reserved
                                SRAM_SEL, // SEL base address (a[28:21] == 8'b0100_0000)
                                4'h0,     //     reserved
                                1'b0,     // PEN no parity
                                1'b0,     // KRO ---
                                1'b0,     // BAS ---
                                1'b0,     // WP  no write protection
                                2'b00,    // MS  ---
                                2'h2,     // BW  32bit Bus width
                                3'h2,     // MEM memory type == asynchronous
                                1'b1      // EN  enable chip select
                        };
 
                        tms_data = {
                                6'h0,  // reserved
                                6'h0,  // Twwd =  5ns =>  0ns
                                4'h0,  // Twd  =  0ns =>  0ns
                                4'h1,  // Twpw = 15ns => 20ns
                                4'h0,  // Trdz =  8ns => 10ns
                                8'h02  // Trdv = 20ns => 20ns
                        };
 
                        // program chip select registers
                        wbm.wb_write(0, 0, 32'h6000_0018, csr_data);      // program cs1 config register
                        wbm.wb_write(0, 0, 32'h6000_001c, tms_data);      // program cs1 timing register
 
                        // check written data
                        wbm.wb_cmp(0, 0, 32'h6000_0018, csr_data);
                        wbm.wb_cmp(0, 0, 32'h6000_001c, tms_data);
 
                        cyc_delay = 1;
                        stb_delay = 1;
                        for (cyc_delay = 0; cyc_delay <= MAX_CYC_DELAY; cyc_delay = cyc_delay +1)
                        for (stb_delay = 0; stb_delay <= MAX_STB_DELAY; stb_delay = stb_delay +1)
                                begin
                                        $display("Asynchronous memory back-2-back test. CYC-delay = %d, STB-delay = %d", cyc_delay, stb_delay);
 
                                        // fill srams
 
                                        my_dat = 0;
                                        for (n=0; n < SRAM_TST_RUN; n=n+1)
                                                begin
                                                        my_adr = SRAM_STARTA + (n << 2);
 
                                                        cnt = n + cyc_delay + stb_delay;
 
                                                        my_dat[31:16] = cnt;
                                                        my_dat[15: 0] = ~cnt;
 
                                                        wbm.wb_write(cyc_delay, stb_delay, my_adr, my_dat);
 
                                                        // read srams
                                                        my_adr = SRAM_STARTA + (n<<2); // always read 32bits
                                                        wbm.wb_cmp(cyc_delay, stb_delay, my_adr, my_dat);
                                                end
                                end
 
                        $display("\nAsynchronous memory back-2-back test ended");
                end
        endtask // tst_amem_b2b
 

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Subversion Repositories mem_ctrl

[/] [mem_ctrl/] [trunk/] [bench/] [richard/] [verilog/] [tst_asram.v] - Blame information for rev 28

Line No.	Rev	Author	Line
1	25	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OpenCores Memory Controller Testbench ////`
4			`//// Asynchronous memory devices tests ////`
5			`//// This file is being included by the main testbench ////`
6			`//// ////`
7			`//// Author: Richard Herveille ////`
8			`//// richard@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2001, 2002 Richard Herveille ////`
16			`//// richard@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41			`// $Id: tst_asram.v,v 1.1 2002-03-06 15:10:34 rherveille Exp $`
42			`//`
43			`// $Date: 2002-03-06 15:10:34 $`
44			`// $Revision: 1.1 $`
45			`// $Author: rherveille $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51			`//`
52
53
54			`///////////////////////////////////////`
55			`// Asynchronous memory sequential test`
56			`//`
57
58			`// 1) Fill entire SRAM memory using sequential accesses`
59			`// 2) Test 8/16/32 bit wide asynchronous accesses`
60			`// 2) Verify memory contents`
61			`//`
62			`// THIS IS A FULL MEMORY TEST, TAKES A WHILE`
63			`task tst_amem_seq;`
64			`parameter MAX_CYC_DELAY = 5;`
65			`parameter MAX_STB_DELAY = 5;`
66
67			parameter [31:0] SRAM_STARTA = `SRAM_LOC;
68			`parameter [ 7:0] SRAM_SEL = SRAM_STARTA[28:21];`
69			`parameter SRAM_TST_RUN = 1<<11; // entire sram memory`
70
71			`integer n, cnt;`
72			`reg [1:0] tmp;`
73			`reg [31:0] my_adr;`
74			`reg [31:0] my_dat;`
75
76			`reg[1:0] bw;`
77			`reg [31:0] csr_data, tms_data;`
78
79			`integer cyc_delay, stb_delay;`
80
81			`begin`
82
83			`$display("\n\n --- ASYNCHRONOUS MEMORY SEQUENTIAL/FILL TEST ---\n\n");`
84
85			`bw = 2;`
86			`for (bw = 0; bw < 3; bw = bw +1)`
87			`begin`
88			`csr_data = {`
89			`8'h00, // reserved`
90			`SRAM_SEL, // SEL base address (a[28:21] == 8'b0100_0000)`
91			`4'h0, // reserved`
92			`1'b0, // PEN no parity`
93			`1'b0, // KRO ---`
94			`1'b0, // BAS ---`
95			`1'b0, // WP no write protection`
96			`2'b00, // MS ---`
97			`bw, // BW Bus width`
98			`3'h2, // MEM memory type == asynchronous`
99			`1'b1 // EN enable chip select`
100			`};`
101
102			`tms_data = {`
103			`6'h0, // reserved`
104			`6'h0, // Twwd = 5ns => 0ns`
105			`4'h0, // Twd = 0ns => 0ns`
106			`4'h1, // Twpw = 15ns => 20ns`
107			`4'h0, // Trdz = 8ns => 10ns`
108			`8'h02 // Trdv = 20ns => 20ns`
109			`};`
110
111			`// program chip select registers`
112			`wbm.wb_write(0, 0, 32'h6000_0018, csr_data); // program cs1 config register`
113			`wbm.wb_write(0, 0, 32'h6000_001c, tms_data); // program cs1 timing register`
114
115			`// check written data`
116			`wbm.wb_cmp(0, 0, 32'h6000_0018, csr_data);`
117			`wbm.wb_cmp(0, 0, 32'h6000_001c, tms_data);`
118
119			`cyc_delay = 1;`
120			`stb_delay = 1;`
121			`for (cyc_delay = 0; cyc_delay < MAX_CYC_DELAY; cyc_delay = cyc_delay +1)`
122			`for (stb_delay = 0; stb_delay < MAX_STB_DELAY; stb_delay = stb_delay +1)`
123			`begin`
124			`$display("Asynchronous memory sequential test. CYC-delay = %d, STB-delay = %d, BW = %d", cyc_delay, stb_delay, bw);`
125
126			`// fill srams`
127			`tmp = ~(bw +1);`
128
129			`my_dat = 0;`
130			`for (n=0; n < (SRAM_TST_RUN<<tmp); n=n+1)`
131			`begin`
132			`my_adr = SRAM_STARTA + (n << bw);`
133
134			`cnt = (n >> tmp) + cyc_delay + stb_delay;`
135
136			`case (bw)`
137			`2'b00: // 8bit asynchronous memory connected`
138			`case (n[1:0])`
139			`2'b00: my_dat[7:0] = ~cnt[ 7:0];`
140			`2'b01: my_dat[7:0] = ~cnt[15:8];`
141			`2'b10: my_dat[7:0] = cnt[ 7:0];`
142			`2'b11: my_dat[7:0] = cnt[15:8];`
143			`endcase`
144			`2'b01: // 16bit asynchronous memory connected`
145			`if (n[0])`
146			`my_dat[15:0] = cnt;`
147			`else`
148			`my_dat[15:0] = ~cnt;`
149			`2'b10: // 32bit asynchronous memory connected`
150			`begin`
151			`my_dat[31:16] = cnt;`
152			`my_dat[15: 0] = ~cnt;`
153			`end`
154			`2'b11: // reserved`
155			`begin`
156			`end`
157			`endcase`
158
159			`wbm.wb_write(cyc_delay, stb_delay, my_adr, my_dat);`
160			`end`
161
162			`// read srams`
163			`my_dat = 0;`
164			`for (n=0; n < SRAM_TST_RUN; n=n+1)`
165			`begin`
166			`my_adr = SRAM_STARTA + (n<<2); // always read 32bits`
167			`my_dat[31:16] = (n + cyc_delay + stb_delay);`
168			`my_dat[15: 0] = ~(n + cyc_delay + stb_delay);`
169
170			`wbm.wb_cmp(cyc_delay, stb_delay, my_adr, my_dat);`
171			`end`
172			`end`
173			`end`
174
175			`$display("\nAsynchronous memory sequential test ended");`
176
177			`end`
178			`endtask // tst_amem_seq`
179
180
181			`///////////////////////////////////////`
182			`// Asynchronous memory back2back test`
183			`//`
184
185			`// 1) Test back-2-back read/write accesses to asynchronous memory`
186			`task tst_amem_b2b;`
187			`parameter MAX_CYC_DELAY = 5;`
188			`parameter MAX_STB_DELAY = 5;`
189
190			parameter [31:0] SRAM_STARTA = `SRAM_LOC;
191			`parameter [ 7:0] SRAM_SEL = SRAM_STARTA[28:21];`
192			`parameter SRAM_TST_RUN = 64; // only do a few accesses`
193
194			`integer n, cnt;`
195			`reg [1:0] tmp;`
196			`reg [31:0] my_adr;`
197			`reg [31:0] my_dat;`
198
199			`reg [31:0] csr_data, tms_data;`
200
201			`integer cyc_delay, stb_delay;`
202
203			`begin`
204			`csr_data = {`
205			`8'h00, // reserved`
206			`SRAM_SEL, // SEL base address (a[28:21] == 8'b0100_0000)`
207			`4'h0, // reserved`
208			`1'b0, // PEN no parity`
209			`1'b0, // KRO ---`
210			`1'b0, // BAS ---`
211			`1'b0, // WP no write protection`
212			`2'b00, // MS ---`
213			`2'h2, // BW 32bit Bus width`
214			`3'h2, // MEM memory type == asynchronous`
215			`1'b1 // EN enable chip select`
216			`};`
217
218			`tms_data = {`
219			`6'h0, // reserved`
220			`6'h0, // Twwd = 5ns => 0ns`
221			`4'h0, // Twd = 0ns => 0ns`
222			`4'h1, // Twpw = 15ns => 20ns`
223			`4'h0, // Trdz = 8ns => 10ns`
224			`8'h02 // Trdv = 20ns => 20ns`
225			`};`
226
227			`// program chip select registers`
228			`wbm.wb_write(0, 0, 32'h6000_0018, csr_data); // program cs1 config register`
229			`wbm.wb_write(0, 0, 32'h6000_001c, tms_data); // program cs1 timing register`
230
231			`// check written data`
232			`wbm.wb_cmp(0, 0, 32'h6000_0018, csr_data);`
233			`wbm.wb_cmp(0, 0, 32'h6000_001c, tms_data);`
234
235			`cyc_delay = 1;`
236			`stb_delay = 1;`
237			`for (cyc_delay = 0; cyc_delay <= MAX_CYC_DELAY; cyc_delay = cyc_delay +1)`
238			`for (stb_delay = 0; stb_delay <= MAX_STB_DELAY; stb_delay = stb_delay +1)`
239			`begin`
240			`$display("Asynchronous memory back-2-back test. CYC-delay = %d, STB-delay = %d", cyc_delay, stb_delay);`
241
242			`// fill srams`
243
244			`my_dat = 0;`
245			`for (n=0; n < SRAM_TST_RUN; n=n+1)`
246			`begin`
247			`my_adr = SRAM_STARTA + (n << 2);`
248
249			`cnt = n + cyc_delay + stb_delay;`
250
251			`my_dat[31:16] = cnt;`
252			`my_dat[15: 0] = ~cnt;`
253
254			`wbm.wb_write(cyc_delay, stb_delay, my_adr, my_dat);`
255
256			`// read srams`
257			`my_adr = SRAM_STARTA + (n<<2); // always read 32bits`
258			`wbm.wb_cmp(cyc_delay, stb_delay, my_adr, my_dat);`
259			`end`
260			`end`
261
262			`$display("\nAsynchronous memory back-2-back test ended");`
263			`end`
264			`endtask // tst_amem_b2b`
265