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[/] [mem_ctrl/] [trunk/] [bench/] [richard/] [verilog/] [tst_multi_mem.v] - Blame information for rev 28

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  OpenCores Memory Controller Testbench                      ////
////  Multiple memory devices tests                              ////
////  This file is being included by the main testbench          ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001, 2002 Richard Herveille                  ////
////                          richard@asics.ws                   ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: tst_multi_mem.v,v 1.1 2002-03-06 15:10:34 rherveille Exp $
//
//  $Date: 2002-03-06 15:10:34 $
//  $Revision: 1.1 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
 
        ///////////////////////////////
        // SDRAM/SRAM Block copy test1
        //
 
        // Test multi-memory accesses (SDRAM & SRAM)
        // 1) Copy memory-block from SDRAM to SRAM
        // 2) Copy block from SRAM to SDRAM
        // 3) Run test for all CS settings for SDRAMS
        task tst_blk_cpy1;
 
                parameter MAX_CYC_DELAY = 5;
                parameter MAX_STB_DELAY = 5;
                parameter MAX_BSIZE = 8;
 
                parameter [31:0] SDRAM_STARTA = `SDRAM1_LOC;
                parameter [ 7:0] SDRAM_SEL = SDRAM_STARTA[28:21];
                parameter [31:0] SRAM_STARTA = `SRAM_LOC;
                parameter [ 7:0] SRAM_SEL = SRAM_STARTA[28:21];
                parameter TST_RUN = 64; // only perform a few accesses
 
                parameter SDRAM_SRC = SDRAM_STARTA;
                parameter SRAM_SRC  = SRAM_STARTA;
 
                integer n, wcnt, bsize;
                reg [31:0] my_adr, src_adr, dest_adr;
                reg [31:0] my_dat;
                reg [31:0] tmp [MAX_BSIZE -1 :0];
                reg [31:0] sdram_dest;
 
                // config register mode bits
                reg [1:0] kro, bas; // a single register doesn't work with the for-loops
 
                // SDRAM Mode Register bits
                reg [1:0] wbl; // a single register doesn't work with the for-loops
                reg [2:0] cl, bl;
 
                reg [31:0] csc_data, tms_data;
 
                integer cyc_delay, stb_delay;
 
                begin
 
                        $display("\n\n --- Multiple memory block copy TEST-1- ---\n\n");
 
                        // clear Wishbone-Master-model current-error-counter 
                        wbm.set_cur_err_cnt(0);
 
                        // program asynchronous SRAMs
                        csc_data = {
                                8'h00,    //     reserved
                                SRAM_SEL, // SEL base address (a[28:21] == 8'b0100_0000)
                                4'h0,     //     reserved
                                1'b0,     // PEN no parity
                                1'b0,     // KRO ---
                                1'b0,     // BAS ---
                                1'b0,     // WP  no write protection
                                2'b00,    // MS  ---
                                2'h2,     // BW  Bus width
                                3'h2,     // MEM memory type == asynchronous
                                1'b1      // EN  enable chip select
                        };
 
                        tms_data = {
                                6'h0,  // reserved
                                6'h0,  // Twwd =  5ns =>  0ns
                                4'h0,  // Twd  =  0ns =>  0ns
                                4'h1,  // Twpw = 15ns => 20ns
                                4'h0,  // Trdz =  8ns => 10ns
                                8'h02  // Trdv = 20ns => 20ns
                        };
 
                        // program chip select registers
                        wbm.wb_write(0, 0, 32'h6000_0018, csc_data);      // program cs1 config register
                        wbm.wb_write(0, 0, 32'h6000_001c, tms_data);      // program cs1 timing register
 
                        // check written data
                        wbm.wb_cmp(0, 0, 32'h6000_0018, csc_data);
                        wbm.wb_cmp(0, 0, 32'h6000_001c, tms_data);
 
 
                        // SDRAMS
                        kro = 1;
                        bas = 1;
 
                        wbl = 0; // programmed burst length
                        cl  = 2; // cas latency
                        bl  = 0; // burst length
 
                        // variables for TMS register
                        for (cl  = 2; cl  <= 3; cl  = cl  +1)
                        for (wbl = 0; wbl <= 1; wbl = wbl +1)
                        for (bl  = 0; bl  <= 3; bl  = bl  +1)
 
                        // variables for CSC register
                        for (kro = 0; kro <= 1; kro = kro +1)
                        for (bas = 0; bas <= 1; bas = bas +1)
                                begin
                                        csc_data = {
                                                8'h00,      // reserved
                                                SDRAM_SEL,  // SEL
                                                4'h0,       // reserved
                                                1'b0,       // parity disabled
                                                kro[0],     // KRO
                                                bas[0],     // BAS
                                                1'b0,       // WP
                                                2'b10,      // MS == 256MB
                                                2'b01 ,     // BW == 16bit bus per device
                                                3'b000,     // MEM_TYPE == SDRAM
                                                1'b1        // EN == chip select enabled
                                        };
 
                                        tms_data = {
                                                4'h0,   // reserved
                                                4'h8,   // Trfc == 7 (+1)
                                                4'h4,   // Trp == 2 (+1) ?????
                                                3'h3,   // Trcd == 2 (+1)
                                                2'b11,  // Twr == 2 (+1)
                                                5'h0,   // reserved
                                                wbl[0], // write burst length
                                                2'b00,  // OM  == normal operation
                                                cl,     // cas latency
                                                1'b0,   // BT == sequential burst type
                                                bl
                                        };
 
                                        // program chip select registers
                                        $display("\nProgramming SDRAM chip select register. KRO = %d, BAS = %d", kro, bas);
                                        wbm.wb_write(0, 0, 32'h6000_0028, csc_data); // program cs3 config register (CSC3)
 
                                        $display("Programming SDRAM timing register. WBL = %d, CL = %d, BL = %d\n", wbl, cl, bl);
                                        wbm.wb_write(0, 0, 32'h6000_002c, tms_data); // program cs3 timing register (TMS3)
 
                                        // check written data
                                        wbm.wb_cmp(0, 0, 32'h6000_0028, csc_data);
                                        wbm.wb_cmp(0, 0, 32'h6000_002c, tms_data);
 
                                        // calculate sdram destination address
                                        if (bas)
                                                sdram_dest = SDRAM_SRC + 32'h0001_0000; // add row address
                                        else
                                                sdram_dest = SDRAM_SRC + 32'h0000_0800; // add column address
 
                                        cyc_delay = 1;
                                        stb_delay = 2;
                                        bsize     = 0;
                                        wcnt      = 0;
                                        for (cyc_delay = 0; cyc_delay <= MAX_CYC_DELAY; cyc_delay = cyc_delay +1)
                                        for (stb_delay = 0; stb_delay <= MAX_STB_DELAY; stb_delay = stb_delay +1)
                                        for (bsize     = 0; bsize     <  MAX_BSIZE;     bsize     = bsize     +1)
                                                begin
 
                                                        if (cyc_delay == 0)
                                                                while ( ((bsize +1) % (1 << bl) != 0) && (bsize < (MAX_BSIZE -1)) )
                                                                        bsize = bsize +1;
 
                                                        $display("SDRAM/SRAM block copy test-1-. CYC-delay = %d, STB-delay = %d, burst-size = %d", cyc_delay, stb_delay, bsize);
 
                                                        // fill sdrams
                                                        my_dat = 0;
                                                        for (n = 0; n < TST_RUN; n=n+1)
                                                                begin
                                                                        my_adr   = (n << 2);
                                                                        dest_adr = SDRAM_SRC + my_adr;
                                                                        my_dat   = my_adr + my_dat + kro + bas + wbl + cl + bl + cyc_delay + stb_delay;
 
                                                                        wbm.wb_write(cyc_delay, stb_delay, dest_adr, my_dat);
                                                                end
 
                                                        // perform Read-Modify-Write cycle
                                                        n = 0;
                                                        while (n < TST_RUN)
                                                                begin
                                                                        // copy from sdrams into srams
                                                                        for (wcnt = 0; wcnt <= bsize; wcnt = wcnt +1)
                                                                        begin
                                                                                my_adr   = (n + wcnt) << 2;
                                                                                src_adr  = SDRAM_SRC + my_adr;
 
                                                                                // read memory contents
                                                                                wbm.wb_read(cyc_delay, stb_delay, src_adr, my_dat);
 
                                                                                // modify memory contents
                                                                                tmp[wcnt] = my_dat +1;
                                                                        end
 
                                                                        for (wcnt = 0; wcnt <= bsize; wcnt = wcnt +1)
                                                                        begin
                                                                                my_adr   = (n + wcnt) << 2;
                                                                                dest_adr = SRAM_SRC + my_adr;
 
                                                                                // write contents back into memory
                                                                                wbm.wb_write(cyc_delay, stb_delay, dest_adr, tmp[wcnt]);
                                                                        end
 
                                                                        // copy from srams into sdrams
                                                                        for (wcnt = 0; wcnt <= bsize; wcnt = wcnt +1)
                                                                        begin
                                                                                my_adr   = (n + wcnt) << 2;
                                                                                src_adr  = SRAM_SRC + my_adr;
 
                                                                                // read memory contents
                                                                                wbm.wb_read(cyc_delay, stb_delay, src_adr, my_dat);
 
                                                                                // modify memory contents
                                                                                tmp[wcnt] = my_dat -1;
                                                                        end
 
                                                                        for (wcnt = 0; wcnt <= bsize; wcnt = wcnt +1)
                                                                        begin
                                                                                my_adr   = (n + wcnt) << 2;
                                                                                dest_adr = sdram_dest + my_adr;
 
                                                                                // write contents back into memory
                                                                                wbm.wb_write(cyc_delay, stb_delay, dest_adr, tmp[wcnt]);
                                                                        end
 
                                                                        n = n + bsize +1;
                                                                end
 
                                                        // read sdrams
                                                        my_dat = 0;
                                                        for (n=0; n < TST_RUN; n=n+1)
                                                                begin
                                                                        my_adr   = (n << 2);
                                                                        dest_adr = sdram_dest + my_adr;
                                                                        my_dat   = my_adr + my_dat + kro + bas + wbl + cl + bl + cyc_delay + stb_delay;
 
                                                                        wbm.wb_cmp(cyc_delay, stb_delay, dest_adr, my_dat);
                                                                end
                                                end
                                end
 
                        // show Wishbone-Master-model current-error-counter 
                        wbm.show_cur_err_cnt;
 
                        $display("\nSDRAM/SRAM block copy test-1- ended");
 
                end
        endtask // tst_blk_cpy1
 
 
        ///////////////////////////////
        // SDRAM/SDRAM Block copy test2
        //
 
        // Test multimemory accesses (SDRAM & SDRAM)
        // 1) Copy memory block from SDRAM1 to SDRAM2
        // 2) Copy block from SDRAM2 to SDRAM1
        // 3) Use different pages/banks for copy (4 runs)
        // 4) Run test for all CS settings for SDRAM1 & SDRAM2
        //
        // THIS IS A VERY LONG TEST !!!!
        // MAY RUN FOR A COUPLE OF WEEKS
        task tst_blk_cpy2;
 
                // if the MAX_ numbers are larger than 15, adjust the appropriate _reg registers (see below)
                parameter MAX_CYC_DELAY = 5;
                parameter MAX_STB_DELAY = 5;
                parameter MAX_BSIZE = 8;
 
                parameter [31:0] SDRAM1_STARTA = `SDRAM1_LOC;
                parameter [ 7:0] SDRAM1_SEL = SDRAM1_STARTA[28:21];
                parameter [31:0] SDRAM2_STARTA = `SDRAM2_LOC;
                parameter [ 7:0] SDRAM2_SEL = SDRAM2_STARTA[28:21];
                parameter TST_RUN = 32; // only perform a few accesses
 
                parameter SDRAM0 = SDRAM1_STARTA;
                parameter SDRAM1 = SDRAM2_STARTA;
 
                integer n, wcnt, bsize, opt;
                reg [31:0] my_adr, src_adr, dest_adr, dest_adr0, dest_adr1;
                reg [31:0] my_dat;
                reg [31:0] tmp [MAX_BSIZE -1 :0];
 
                // display registers (convert integers into regs)
                reg [1:0] opt_reg;
                reg [3:0] cyc_reg, stb_reg, bsz_reg;
 
                // config register mode bits
                reg [1:0] kro0, bas0, kro1, bas1; // a single register doesn't work with the for-loops
 
                // SDRAM Mode Register bits
                reg [1:0] wbl0, wbl1; // a single register doesn't work with the for-loops
                reg [2:0] cl0, bl0, cl1, bl1;
 
                reg [31:0] csc_data, tms_data;
 
                integer cyc_delay, stb_delay;
 
        begin
 
                $display("\n\n --- Multiple memory block copy TEST-2- ---\n\n");
 
                // clear Wishbone-Master-model current-error-counter 
                wbm.set_cur_err_cnt(0);
 
                for(opt = 0; opt <= 4; opt = opt +1)
                begin
                        // SDRAM1
                        kro0 = 0;
                        bas0 = 0;
 
                        wbl0 = 0;
                        cl0  = 2; // cas latency = 2
                        bl0  = 1;
 
                        // variables for TMS register
                        for (cl0  = 2; cl0  <= 3; cl0  = cl0  +1)
                        for (wbl0 = 0; wbl0 <= 1; wbl0 = wbl0 +1)
                        for (bl0  = 0; bl0  <= 3; bl0  = bl0  +1)
 
                        // variables for CSC register
                        for (kro0 = 0; kro0 <= 1; kro0 = kro0 +1)
//                      for (bas0 = 0; bas0 <= 1; bas0 = bas0 +1) // ignore bas, speed up test
                        begin
                                csc_data = {
                                        8'h00,       // reserved
                                        SDRAM1_SEL,  // SEL
                                        4'h0,        // reserved
                                        1'b0,        // parity disabled
                                        kro0[0],     // KRO
                                        bas0[0],     // BAS
                                        1'b0,        // WP
                                        2'b10,       // MS == 256MB
                                        2'b01,       // BW == 16bit bus per device
                                        3'b000,      // MEM_TYPE == SDRAM
                                        1'b1         // EN == chip select enabled
                                };
 
                                tms_data = {
                                        4'h0,   // reserved
                                        4'h8,   // Trfc == 7 (+1)
                                        4'h4,   // Trp == 2 (+1) ?????
                                        3'h3,   // Trcd == 2 (+1)
                                        2'b11,  // Twr == 2 (+1)
                                        5'h0,   // reserved
                                        wbl0[0],// write burst length
                                        2'b00,  // OM  == normal operation
                                        cl0,    // cas latency
                                        1'b0,   // BT == sequential burst type
                                        bl0     // BL == burst length
                                };
 
                                // program chip select registers
                                $display("\nProgramming SDRAM1 chip select register. KRO = %d, BAS = %d", kro0, bas0);
                                wbm.wb_write(0, 0, 32'h6000_0028, csc_data); // program cs3 config register (CSC3)
 
                                $display("Programming SDRAM1 timing register. WBL = %d, CL = %d, BL = %d\n", wbl0, cl0, bl0);
                                wbm.wb_write(0, 0, 32'h6000_002c, tms_data); // program cs3 timing register (TMS3)
 
                                // check written data
                                wbm.wb_cmp(0, 0, 32'h6000_0028, csc_data);
                                wbm.wb_cmp(0, 0, 32'h6000_002c, tms_data);
 
                                // calculate sdram destination address
                                if (!opt[0])
                                                dest_adr0 = SDRAM0;
                                else
                                        if (bas0)
                                                dest_adr0 = SDRAM0 + 32'h0001_0000; // add row address
                                        else
                                                dest_adr0 = SDRAM0 + 32'h0000_0800; // add column address
 
                                //SDRAM1
                                kro1 = 0;
                                bas1 = 0;
 
                                wbl1 = 1;
                                cl1  = 2; // cas latency = 2
                                bl1  = 2;
 
                                // variables for TMS register
                                for (cl1  = 2; cl1  <= 3; cl1  = cl1  +1)
                                for (wbl1 = 0; wbl1 <= 1; wbl1 = wbl1 +1)
                                for (bl1  = 0; bl1  <= 3; bl1  = bl1  +1)
 
                                // variables for CSC register
                                for (kro1 = 0; kro1 <= 1; kro1 = kro1 +1)
//                              for (bas1 = 0; bas1 <= 1; bas1 = bas1 +1) // ignore bas, speed up test
                                begin
                                        csc_data = {
                                                8'h00,       // reserved
                                                SDRAM2_SEL,  // SEL
                                                4'h0,        // reserved
                                                1'b0,        // parity disabled
                                                kro1[0],     // KRO
                                                bas1[0],     // BAS
                                                1'b0,        // WP
                                                2'b10,       // MS == 256MB
                                                2'b01,       // BW == 16bit bus per device
                                                3'b000,      // MEM_TYPE == SDRAM
                                                1'b1         // EN == chip select enabled
                                        };
 
                                        tms_data = {
                                                4'h0,   // reserved
                                                4'h8,   // Trfc == 7 (+1)
                                                4'h4,   // Trp == 2 (+1) ?????
                                                3'h3,   // Trcd == 2 (+1)
                                                2'b11,  // Twr == 2 (+1)
                                                5'h0,   // reserved
                                                wbl1[0],// write burst length
                                                2'b00,  // OM  == normal operation
                                                cl1,    // cas latency
                                                1'b0,   // BT == sequential burst type
                                                bl1     // BL == burst length
                                        };
 
                                        // program chip select registers
                                        $display("\nProgramming SDRAM2 chip select register. KRO = %d, BAS = %d", kro1, bas1);
                                        wbm.wb_write(0, 0, 32'h6000_0020, csc_data); // program cs3 config register (CSC2)
 
                                        $display("Programming SDRAM2 timing register. WBL = %d, CL = %d, BL = %d\n", wbl1, cl1, bl1);
                                        wbm.wb_write(0, 0, 32'h6000_0024, tms_data); // program cs3 timing register (TMS2)
 
                                        // check written data
                                        wbm.wb_cmp(0, 0, 32'h6000_0020, csc_data);
                                        wbm.wb_cmp(0, 0, 32'h6000_0024, tms_data);
 
                                        // calculate sdram destination address
                                        if (!opt[1])
                                                dest_adr1 = SDRAM1;
                                        else
                                                if (bas1)
                                                        dest_adr1 = SDRAM1 + 32'h0001_0000; // add row address
                                                else
                                                        dest_adr1 = SDRAM1 + 32'h0000_0800; // add column address
 
                                        cyc_delay = 0;
                                        stb_delay = 0;
                                        bsize     = 2;
                                        wcnt      = 0;
                                        for (cyc_delay = 0; cyc_delay <= MAX_CYC_DELAY; cyc_delay = cyc_delay +1)
                                        for (stb_delay = 0; stb_delay <= MAX_STB_DELAY; stb_delay = stb_delay +1)
                                        for (bsize     = 0; bsize     <  MAX_BSIZE;     bsize     = bsize     +1)
                                        begin
                                                if (cyc_delay == 0)
                                                        while ( ( ((bsize +1) % (1 << bl0) !=0) && ((1 << bl0) % (bsize +1) !=0) ) ||
                                                                ( ((bsize +1) % (1 << bl1) !=0) && ((1 << bl1) % (bsize +1) !=0) )
                                                              )
                                                                bsize = bsize +1;
 
 
                                                // convert integers into regs (for display)
                                                opt_reg = opt;
                                                cyc_reg = cyc_delay;
                                                stb_reg = stb_delay;
                                                bsz_reg = bsize;
 
 
                                                $display("SDRAM multi-memory block copy test-2-. Opt = %d, CYC-delay = %d, STB-delay = %d, burst-size = %d", opt_reg, cyc_reg, stb_reg, bsz_reg);
 
                                                // fill sdram0
                                                my_dat = 0;
                                                for (n = 0; n < TST_RUN; n=n+1)
                                                begin
                                                        my_adr   = (n << 2);
                                                        dest_adr = SDRAM0 + my_adr;
                                                        my_dat   = my_adr + my_dat + kro0 + kro1 + bas0 + bas1 + wbl0 + wbl1 + cl0 + cl1 + bl0 + bl1 + cyc_delay + stb_delay;
 
                                                        wbm.wb_write(cyc_delay, stb_delay, dest_adr, my_dat);
                                                end
 
                                                // perform Read-Modify-Write cycle
                                                n = 0;
                                                while (n < TST_RUN)
                                                begin
                                                        // copy from sdram0 into sdram1
                                                        for (wcnt = 0; wcnt <= bsize; wcnt = wcnt +1)
                                                        begin
                                                                my_adr   = (n + wcnt) << 2;
                                                                src_adr  = SDRAM0 + my_adr;
 
                                                                // read memory contents
                                                                wbm.wb_read(cyc_delay, stb_delay, src_adr, my_dat);
 
                                                                // modify memory contents
                                                                tmp[wcnt] = my_dat +1;
                                                        end
 
                                                        for (wcnt = 0; wcnt <= bsize; wcnt = wcnt +1)
                                                        begin
                                                                my_adr   = (n + wcnt) << 2;
                                                                dest_adr = dest_adr1 + my_adr;
 
                                                                // write contents back into memory
                                                                wbm.wb_write(cyc_delay, stb_delay, dest_adr, tmp[wcnt]);
                                                        end
 
                                                        // copy from sdram1 into sdram0
                                                        for (wcnt = 0; wcnt <= bsize; wcnt = wcnt +1)
                                                        begin
                                                                my_adr   = (n + wcnt) << 2;
                                                                src_adr  = dest_adr1 + my_adr;
 
                                                                // read memory contents
                                                                wbm.wb_read(cyc_delay, stb_delay, src_adr, my_dat);
 
                                                                // modify memory contents
                                                                tmp[wcnt] = my_dat +1;
                                                        end
 
                                                        for (wcnt = 0; wcnt <= bsize; wcnt = wcnt +1)
                                                        begin
                                                                my_adr   = (n + wcnt) << 2;
                                                                dest_adr = dest_adr0 + my_adr;
 
                                                                // write contents back into memory
                                                                wbm.wb_write(cyc_delay, stb_delay, dest_adr, tmp[wcnt]);
                                                        end
 
                                                        n = n + bsize +1;
                                                end
 
                                                // read sdrams
                                                my_dat = 0;
                                                for (n=0; n < TST_RUN; n=n+1)
                                                begin
                                                        my_adr   = (n << 2);
                                                        dest_adr = dest_adr0 + my_adr;
                                                        my_dat   = my_adr + my_dat + kro0 + kro1 + bas0 + bas1 + wbl0 + wbl1 + cl0 + cl1 + bl0 + bl1 + cyc_delay + stb_delay;
 
                                                        wbm.wb_cmp(cyc_delay, stb_delay, dest_adr, my_dat +2);
                                                end
                                        end
                                end
                        end
                end
 
                // show Wishbone-Master-model current-error-counter 
                wbm.show_cur_err_cnt;
                $display("\nSDRAM/SRAM block copy test-2- ended");
 
        end
        endtask // tst_blk_cpy2
 

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[/] [mem_ctrl/] [trunk/] [bench/] [richard/] [verilog/] [tst_multi_mem.v] - Blame information for rev 28

Line No.	Rev	Author	Line
1	25	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OpenCores Memory Controller Testbench ////`
4			`//// Multiple memory devices tests ////`
5			`//// This file is being included by the main testbench ////`
6			`//// ////`
7			`//// Author: Richard Herveille ////`
8			`//// richard@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2001, 2002 Richard Herveille ////`
16			`//// richard@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41			`// $Id: tst_multi_mem.v,v 1.1 2002-03-06 15:10:34 rherveille Exp $`
42			`//`
43			`// $Date: 2002-03-06 15:10:34 $`
44			`// $Revision: 1.1 $`
45			`// $Author: rherveille $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51			`//`
52
53			`///////////////////////////////`
54			`// SDRAM/SRAM Block copy test1`
55			`//`
56
57			`// Test multi-memory accesses (SDRAM & SRAM)`
58			`// 1) Copy memory-block from SDRAM to SRAM`
59			`// 2) Copy block from SRAM to SDRAM`
60			`// 3) Run test for all CS settings for SDRAMS`
61			`task tst_blk_cpy1;`
62
63			`parameter MAX_CYC_DELAY = 5;`
64			`parameter MAX_STB_DELAY = 5;`
65			`parameter MAX_BSIZE = 8;`
66
67			parameter [31:0] SDRAM_STARTA = `SDRAM1_LOC;
68			`parameter [ 7:0] SDRAM_SEL = SDRAM_STARTA[28:21];`
69			parameter [31:0] SRAM_STARTA = `SRAM_LOC;
70			`parameter [ 7:0] SRAM_SEL = SRAM_STARTA[28:21];`
71			`parameter TST_RUN = 64; // only perform a few accesses`
72
73			`parameter SDRAM_SRC = SDRAM_STARTA;`
74			`parameter SRAM_SRC = SRAM_STARTA;`
75
76			`integer n, wcnt, bsize;`
77			`reg [31:0] my_adr, src_adr, dest_adr;`
78			`reg [31:0] my_dat;`
79			`reg [31:0] tmp [MAX_BSIZE -1 :0];`
80			`reg [31:0] sdram_dest;`
81
82			`// config register mode bits`
83			`reg [1:0] kro, bas; // a single register doesn't work with the for-loops`
84
85			`// SDRAM Mode Register bits`
86			`reg [1:0] wbl; // a single register doesn't work with the for-loops`
87			`reg [2:0] cl, bl;`
88
89			`reg [31:0] csc_data, tms_data;`
90
91			`integer cyc_delay, stb_delay;`
92
93			`begin`
94
95			`$display("\n\n --- Multiple memory block copy TEST-1- ---\n\n");`
96
97			`// clear Wishbone-Master-model current-error-counter`
98			`wbm.set_cur_err_cnt(0);`
99
100			`// program asynchronous SRAMs`
101			`csc_data = {`
102			`8'h00, // reserved`
103			`SRAM_SEL, // SEL base address (a[28:21] == 8'b0100_0000)`
104			`4'h0, // reserved`
105			`1'b0, // PEN no parity`
106			`1'b0, // KRO ---`
107			`1'b0, // BAS ---`
108			`1'b0, // WP no write protection`
109			`2'b00, // MS ---`
110			`2'h2, // BW Bus width`
111			`3'h2, // MEM memory type == asynchronous`
112			`1'b1 // EN enable chip select`
113			`};`
114
115			`tms_data = {`
116			`6'h0, // reserved`
117			`6'h0, // Twwd = 5ns => 0ns`
118			`4'h0, // Twd = 0ns => 0ns`
119			`4'h1, // Twpw = 15ns => 20ns`
120			`4'h0, // Trdz = 8ns => 10ns`
121			`8'h02 // Trdv = 20ns => 20ns`
122			`};`
123
124			`// program chip select registers`
125			`wbm.wb_write(0, 0, 32'h6000_0018, csc_data); // program cs1 config register`
126			`wbm.wb_write(0, 0, 32'h6000_001c, tms_data); // program cs1 timing register`
127
128			`// check written data`
129			`wbm.wb_cmp(0, 0, 32'h6000_0018, csc_data);`
130			`wbm.wb_cmp(0, 0, 32'h6000_001c, tms_data);`
131
132
133			`// SDRAMS`
134			`kro = 1;`
135			`bas = 1;`
136
137			`wbl = 0; // programmed burst length`
138			`cl = 2; // cas latency`
139			`bl = 0; // burst length`
140
141			`// variables for TMS register`
142			`for (cl = 2; cl <= 3; cl = cl +1)`
143			`for (wbl = 0; wbl <= 1; wbl = wbl +1)`
144			`for (bl = 0; bl <= 3; bl = bl +1)`
145
146			`// variables for CSC register`
147			`for (kro = 0; kro <= 1; kro = kro +1)`
148			`for (bas = 0; bas <= 1; bas = bas +1)`
149			`begin`
150			`csc_data = {`
151			`8'h00, // reserved`
152			`SDRAM_SEL, // SEL`
153			`4'h0, // reserved`
154			`1'b0, // parity disabled`
155			`kro[0], // KRO`
156			`bas[0], // BAS`
157			`1'b0, // WP`
158			`2'b10, // MS == 256MB`
159			`2'b01 , // BW == 16bit bus per device`
160			`3'b000, // MEM_TYPE == SDRAM`
161			`1'b1 // EN == chip select enabled`
162			`};`
163
164			`tms_data = {`
165			`4'h0, // reserved`
166			`4'h8, // Trfc == 7 (+1)`
167			`4'h4, // Trp == 2 (+1) ?????`
168			`3'h3, // Trcd == 2 (+1)`
169			`2'b11, // Twr == 2 (+1)`
170			`5'h0, // reserved`
171			`wbl[0], // write burst length`
172			`2'b00, // OM == normal operation`
173			`cl, // cas latency`
174			`1'b0, // BT == sequential burst type`
175			`bl`
176			`};`
177
178			`// program chip select registers`
179			`$display("\nProgramming SDRAM chip select register. KRO = %d, BAS = %d", kro, bas);`
180			`wbm.wb_write(0, 0, 32'h6000_0028, csc_data); // program cs3 config register (CSC3)`
181
182			`$display("Programming SDRAM timing register. WBL = %d, CL = %d, BL = %d\n", wbl, cl, bl);`
183			`wbm.wb_write(0, 0, 32'h6000_002c, tms_data); // program cs3 timing register (TMS3)`
184
185			`// check written data`
186			`wbm.wb_cmp(0, 0, 32'h6000_0028, csc_data);`
187			`wbm.wb_cmp(0, 0, 32'h6000_002c, tms_data);`
188
189			`// calculate sdram destination address`
190			`if (bas)`
191			`sdram_dest = SDRAM_SRC + 32'h0001_0000; // add row address`
192			`else`
193			`sdram_dest = SDRAM_SRC + 32'h0000_0800; // add column address`
194
195			`cyc_delay = 1;`
196			`stb_delay = 2;`
197			`bsize = 0;`
198			`wcnt = 0;`
199			`for (cyc_delay = 0; cyc_delay <= MAX_CYC_DELAY; cyc_delay = cyc_delay +1)`
200			`for (stb_delay = 0; stb_delay <= MAX_STB_DELAY; stb_delay = stb_delay +1)`
201			`for (bsize = 0; bsize < MAX_BSIZE; bsize = bsize +1)`
202			`begin`
203
204			`if (cyc_delay == 0)`
205			`while ( ((bsize +1) % (1 << bl) != 0) && (bsize < (MAX_BSIZE -1)) )`
206			`bsize = bsize +1;`
207
208			`$display("SDRAM/SRAM block copy test-1-. CYC-delay = %d, STB-delay = %d, burst-size = %d", cyc_delay, stb_delay, bsize);`
209
210			`// fill sdrams`
211			`my_dat = 0;`
212			`for (n = 0; n < TST_RUN; n=n+1)`
213			`begin`
214			`my_adr = (n << 2);`
215			`dest_adr = SDRAM_SRC + my_adr;`
216			`my_dat = my_adr + my_dat + kro + bas + wbl + cl + bl + cyc_delay + stb_delay;`
217
218			`wbm.wb_write(cyc_delay, stb_delay, dest_adr, my_dat);`
219			`end`
220
221			`// perform Read-Modify-Write cycle`
222			`n = 0;`
223			`while (n < TST_RUN)`
224			`begin`
225			`// copy from sdrams into srams`
226			`for (wcnt = 0; wcnt <= bsize; wcnt = wcnt +1)`
227			`begin`
228			`my_adr = (n + wcnt) << 2;`
229			`src_adr = SDRAM_SRC + my_adr;`
230
231			`// read memory contents`
232			`wbm.wb_read(cyc_delay, stb_delay, src_adr, my_dat);`
233
234			`// modify memory contents`
235			`tmp[wcnt] = my_dat +1;`
236			`end`
237
238			`for (wcnt = 0; wcnt <= bsize; wcnt = wcnt +1)`
239			`begin`
240			`my_adr = (n + wcnt) << 2;`
241			`dest_adr = SRAM_SRC + my_adr;`
242
243			`// write contents back into memory`
244			`wbm.wb_write(cyc_delay, stb_delay, dest_adr, tmp[wcnt]);`
245			`end`
246
247			`// copy from srams into sdrams`
248			`for (wcnt = 0; wcnt <= bsize; wcnt = wcnt +1)`
249			`begin`
250			`my_adr = (n + wcnt) << 2;`
251			`src_adr = SRAM_SRC + my_adr;`
252
253			`// read memory contents`
254			`wbm.wb_read(cyc_delay, stb_delay, src_adr, my_dat);`
255
256			`// modify memory contents`
257			`tmp[wcnt] = my_dat -1;`
258			`end`
259
260			`for (wcnt = 0; wcnt <= bsize; wcnt = wcnt +1)`
261			`begin`
262			`my_adr = (n + wcnt) << 2;`
263			`dest_adr = sdram_dest + my_adr;`
264
265			`// write contents back into memory`
266			`wbm.wb_write(cyc_delay, stb_delay, dest_adr, tmp[wcnt]);`
267			`end`
268
269			`n = n + bsize +1;`
270			`end`
271
272			`// read sdrams`
273			`my_dat = 0;`
274			`for (n=0; n < TST_RUN; n=n+1)`
275			`begin`
276			`my_adr = (n << 2);`
277			`dest_adr = sdram_dest + my_adr;`
278			`my_dat = my_adr + my_dat + kro + bas + wbl + cl + bl + cyc_delay + stb_delay;`
279
280			`wbm.wb_cmp(cyc_delay, stb_delay, dest_adr, my_dat);`
281			`end`
282			`end`
283			`end`
284
285			`// show Wishbone-Master-model current-error-counter`
286			`wbm.show_cur_err_cnt;`
287
288			`$display("\nSDRAM/SRAM block copy test-1- ended");`
289
290			`end`
291			`endtask // tst_blk_cpy1`
292
293
294			`///////////////////////////////`
295			`// SDRAM/SDRAM Block copy test2`
296			`//`
297
298			`// Test multimemory accesses (SDRAM & SDRAM)`
299			`// 1) Copy memory block from SDRAM1 to SDRAM2`
300			`// 2) Copy block from SDRAM2 to SDRAM1`
301			`// 3) Use different pages/banks for copy (4 runs)`
302			`// 4) Run test for all CS settings for SDRAM1 & SDRAM2`
303			`//`
304			`// THIS IS A VERY LONG TEST !!!!`
305			`// MAY RUN FOR A COUPLE OF WEEKS`
306			`task tst_blk_cpy2;`
307
308			`// if the MAX_ numbers are larger than 15, adjust the appropriate _reg registers (see below)`
309			`parameter MAX_CYC_DELAY = 5;`
310			`parameter MAX_STB_DELAY = 5;`
311			`parameter MAX_BSIZE = 8;`
312
313			parameter [31:0] SDRAM1_STARTA = `SDRAM1_LOC;
314			`parameter [ 7:0] SDRAM1_SEL = SDRAM1_STARTA[28:21];`
315			parameter [31:0] SDRAM2_STARTA = `SDRAM2_LOC;
316			`parameter [ 7:0] SDRAM2_SEL = SDRAM2_STARTA[28:21];`
317			`parameter TST_RUN = 32; // only perform a few accesses`
318
319			`parameter SDRAM0 = SDRAM1_STARTA;`
320			`parameter SDRAM1 = SDRAM2_STARTA;`
321
322			`integer n, wcnt, bsize, opt;`
323			`reg [31:0] my_adr, src_adr, dest_adr, dest_adr0, dest_adr1;`
324			`reg [31:0] my_dat;`
325			`reg [31:0] tmp [MAX_BSIZE -1 :0];`
326
327			`// display registers (convert integers into regs)`
328			`reg [1:0] opt_reg;`
329			`reg [3:0] cyc_reg, stb_reg, bsz_reg;`
330
331			`// config register mode bits`
332			`reg [1:0] kro0, bas0, kro1, bas1; // a single register doesn't work with the for-loops`
333
334			`// SDRAM Mode Register bits`
335			`reg [1:0] wbl0, wbl1; // a single register doesn't work with the for-loops`
336			`reg [2:0] cl0, bl0, cl1, bl1;`
337
338			`reg [31:0] csc_data, tms_data;`
339
340			`integer cyc_delay, stb_delay;`
341
342			`begin`
343
344			`$display("\n\n --- Multiple memory block copy TEST-2- ---\n\n");`
345
346			`// clear Wishbone-Master-model current-error-counter`
347			`wbm.set_cur_err_cnt(0);`
348
349			`for(opt = 0; opt <= 4; opt = opt +1)`
350			`begin`
351			`// SDRAM1`
352			`kro0 = 0;`
353			`bas0 = 0;`
354
355			`wbl0 = 0;`
356			`cl0 = 2; // cas latency = 2`
357			`bl0 = 1;`
358
359			`// variables for TMS register`
360			`for (cl0 = 2; cl0 <= 3; cl0 = cl0 +1)`
361			`for (wbl0 = 0; wbl0 <= 1; wbl0 = wbl0 +1)`
362			`for (bl0 = 0; bl0 <= 3; bl0 = bl0 +1)`
363
364			`// variables for CSC register`
365			`for (kro0 = 0; kro0 <= 1; kro0 = kro0 +1)`
366			`// for (bas0 = 0; bas0 <= 1; bas0 = bas0 +1) // ignore bas, speed up test`
367			`begin`
368			`csc_data = {`
369			`8'h00, // reserved`
370			`SDRAM1_SEL, // SEL`
371			`4'h0, // reserved`
372			`1'b0, // parity disabled`
373			`kro0[0], // KRO`
374			`bas0[0], // BAS`
375			`1'b0, // WP`
376			`2'b10, // MS == 256MB`
377			`2'b01, // BW == 16bit bus per device`
378			`3'b000, // MEM_TYPE == SDRAM`
379			`1'b1 // EN == chip select enabled`
380			`};`
381
382			`tms_data = {`
383			`4'h0, // reserved`
384			`4'h8, // Trfc == 7 (+1)`
385			`4'h4, // Trp == 2 (+1) ?????`
386			`3'h3, // Trcd == 2 (+1)`
387			`2'b11, // Twr == 2 (+1)`
388			`5'h0, // reserved`
389			`wbl0[0],// write burst length`
390			`2'b00, // OM == normal operation`
391			`cl0, // cas latency`
392			`1'b0, // BT == sequential burst type`
393			`bl0 // BL == burst length`
394			`};`
395
396			`// program chip select registers`
397			`$display("\nProgramming SDRAM1 chip select register. KRO = %d, BAS = %d", kro0, bas0);`
398			`wbm.wb_write(0, 0, 32'h6000_0028, csc_data); // program cs3 config register (CSC3)`
399
400			`$display("Programming SDRAM1 timing register. WBL = %d, CL = %d, BL = %d\n", wbl0, cl0, bl0);`
401			`wbm.wb_write(0, 0, 32'h6000_002c, tms_data); // program cs3 timing register (TMS3)`
402
403			`// check written data`
404			`wbm.wb_cmp(0, 0, 32'h6000_0028, csc_data);`
405			`wbm.wb_cmp(0, 0, 32'h6000_002c, tms_data);`
406
407			`// calculate sdram destination address`
408			`if (!opt[0])`
409			`dest_adr0 = SDRAM0;`
410			`else`
411			`if (bas0)`
412			`dest_adr0 = SDRAM0 + 32'h0001_0000; // add row address`
413			`else`
414			`dest_adr0 = SDRAM0 + 32'h0000_0800; // add column address`
415
416			`//SDRAM1`
417			`kro1 = 0;`
418			`bas1 = 0;`
419
420			`wbl1 = 1;`
421			`cl1 = 2; // cas latency = 2`
422			`bl1 = 2;`
423
424			`// variables for TMS register`
425			`for (cl1 = 2; cl1 <= 3; cl1 = cl1 +1)`
426			`for (wbl1 = 0; wbl1 <= 1; wbl1 = wbl1 +1)`
427			`for (bl1 = 0; bl1 <= 3; bl1 = bl1 +1)`
428
429			`// variables for CSC register`
430			`for (kro1 = 0; kro1 <= 1; kro1 = kro1 +1)`
431			`// for (bas1 = 0; bas1 <= 1; bas1 = bas1 +1) // ignore bas, speed up test`
432			`begin`
433			`csc_data = {`
434			`8'h00, // reserved`
435			`SDRAM2_SEL, // SEL`
436			`4'h0, // reserved`
437			`1'b0, // parity disabled`
438			`kro1[0], // KRO`
439			`bas1[0], // BAS`
440			`1'b0, // WP`
441			`2'b10, // MS == 256MB`
442			`2'b01, // BW == 16bit bus per device`
443			`3'b000, // MEM_TYPE == SDRAM`
444			`1'b1 // EN == chip select enabled`
445			`};`
446
447			`tms_data = {`
448			`4'h0, // reserved`
449			`4'h8, // Trfc == 7 (+1)`
450			`4'h4, // Trp == 2 (+1) ?????`
451			`3'h3, // Trcd == 2 (+1)`
452			`2'b11, // Twr == 2 (+1)`
453			`5'h0, // reserved`
454			`wbl1[0],// write burst length`
455			`2'b00, // OM == normal operation`
456			`cl1, // cas latency`
457			`1'b0, // BT == sequential burst type`
458			`bl1 // BL == burst length`
459			`};`
460
461			`// program chip select registers`
462			`$display("\nProgramming SDRAM2 chip select register. KRO = %d, BAS = %d", kro1, bas1);`
463			`wbm.wb_write(0, 0, 32'h6000_0020, csc_data); // program cs3 config register (CSC2)`
464
465			`$display("Programming SDRAM2 timing register. WBL = %d, CL = %d, BL = %d\n", wbl1, cl1, bl1);`
466			`wbm.wb_write(0, 0, 32'h6000_0024, tms_data); // program cs3 timing register (TMS2)`
467
468			`// check written data`
469			`wbm.wb_cmp(0, 0, 32'h6000_0020, csc_data);`
470			`wbm.wb_cmp(0, 0, 32'h6000_0024, tms_data);`
471
472			`// calculate sdram destination address`
473			`if (!opt[1])`
474			`dest_adr1 = SDRAM1;`
475			`else`
476			`if (bas1)`
477			`dest_adr1 = SDRAM1 + 32'h0001_0000; // add row address`
478			`else`
479			`dest_adr1 = SDRAM1 + 32'h0000_0800; // add column address`
480
481			`cyc_delay = 0;`
482			`stb_delay = 0;`
483			`bsize = 2;`
484			`wcnt = 0;`
485			`for (cyc_delay = 0; cyc_delay <= MAX_CYC_DELAY; cyc_delay = cyc_delay +1)`
486			`for (stb_delay = 0; stb_delay <= MAX_STB_DELAY; stb_delay = stb_delay +1)`
487			`for (bsize = 0; bsize < MAX_BSIZE; bsize = bsize +1)`
488			`begin`
489			`if (cyc_delay == 0)`
490			`while ( ( ((bsize +1) % (1 << bl0) !=0) && ((1 << bl0) % (bsize +1) !=0) ) \|\|`
491			`( ((bsize +1) % (1 << bl1) !=0) && ((1 << bl1) % (bsize +1) !=0) )`
492			`)`
493			`bsize = bsize +1;`
494
495
496			`// convert integers into regs (for display)`
497			`opt_reg = opt;`
498			`cyc_reg = cyc_delay;`
499			`stb_reg = stb_delay;`
500			`bsz_reg = bsize;`
501
502
503			`$display("SDRAM multi-memory block copy test-2-. Opt = %d, CYC-delay = %d, STB-delay = %d, burst-size = %d", opt_reg, cyc_reg, stb_reg, bsz_reg);`
504
505			`// fill sdram0`
506			`my_dat = 0;`
507			`for (n = 0; n < TST_RUN; n=n+1)`
508			`begin`
509			`my_adr = (n << 2);`
510			`dest_adr = SDRAM0 + my_adr;`
511			`my_dat = my_adr + my_dat + kro0 + kro1 + bas0 + bas1 + wbl0 + wbl1 + cl0 + cl1 + bl0 + bl1 + cyc_delay + stb_delay;`
512
513			`wbm.wb_write(cyc_delay, stb_delay, dest_adr, my_dat);`
514			`end`
515
516			`// perform Read-Modify-Write cycle`
517			`n = 0;`
518			`while (n < TST_RUN)`
519			`begin`
520			`// copy from sdram0 into sdram1`
521			`for (wcnt = 0; wcnt <= bsize; wcnt = wcnt +1)`
522			`begin`
523			`my_adr = (n + wcnt) << 2;`
524			`src_adr = SDRAM0 + my_adr;`
525
526			`// read memory contents`
527			`wbm.wb_read(cyc_delay, stb_delay, src_adr, my_dat);`
528
529			`// modify memory contents`
530			`tmp[wcnt] = my_dat +1;`
531			`end`
532
533			`for (wcnt = 0; wcnt <= bsize; wcnt = wcnt +1)`
534			`begin`
535			`my_adr = (n + wcnt) << 2;`
536			`dest_adr = dest_adr1 + my_adr;`
537
538			`// write contents back into memory`
539			`wbm.wb_write(cyc_delay, stb_delay, dest_adr, tmp[wcnt]);`
540			`end`
541
542			`// copy from sdram1 into sdram0`
543			`for (wcnt = 0; wcnt <= bsize; wcnt = wcnt +1)`
544			`begin`
545			`my_adr = (n + wcnt) << 2;`
546			`src_adr = dest_adr1 + my_adr;`
547
548			`// read memory contents`
549			`wbm.wb_read(cyc_delay, stb_delay, src_adr, my_dat);`
550
551			`// modify memory contents`
552			`tmp[wcnt] = my_dat +1;`
553			`end`
554
555			`for (wcnt = 0; wcnt <= bsize; wcnt = wcnt +1)`
556			`begin`
557			`my_adr = (n + wcnt) << 2;`
558			`dest_adr = dest_adr0 + my_adr;`
559
560			`// write contents back into memory`
561			`wbm.wb_write(cyc_delay, stb_delay, dest_adr, tmp[wcnt]);`
562			`end`
563
564			`n = n + bsize +1;`
565			`end`
566
567			`// read sdrams`
568			`my_dat = 0;`
569			`for (n=0; n < TST_RUN; n=n+1)`
570			`begin`
571			`my_adr = (n << 2);`
572			`dest_adr = dest_adr0 + my_adr;`
573			`my_dat = my_adr + my_dat + kro0 + kro1 + bas0 + bas1 + wbl0 + wbl1 + cl0 + cl1 + bl0 + bl1 + cyc_delay + stb_delay;`
574
575			`wbm.wb_cmp(cyc_delay, stb_delay, dest_adr, my_dat +2);`
576			`end`
577			`end`
578			`end`
579			`end`
580			`end`
581
582			`// show Wishbone-Master-model current-error-counter`
583			`wbm.show_cur_err_cnt;`
584			`$display("\nSDRAM/SRAM block copy test-2- ended");`
585
586			`end`
587			`endtask // tst_blk_cpy2`
588