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[/] [mem_ctrl/] [trunk/] [bench/] [richard/] [verilog/] [tst_ssram.v] - Blame information for rev 29

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  OpenCores Memory Controller Testbench                      ////
////  SSRAM memory devices tests                                 ////
////  This file is being included by the main testbench          ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001, 2002 Richard Herveille                  ////
////                          richard@asics.ws                   ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: tst_ssram.v,v 1.1 2002-03-06 15:10:34 rherveille Exp $
//
//  $Date: 2002-03-06 15:10:34 $
//  $Revision: 1.1 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
 
 
        ////////////////////////////////
        // SSRAM Sequential access test
        //
 
        // 1) Tests ssram sequential address access
        // 2) Tests page switch
        // 3) Test burst-action by filling memory backwards (high addresses first)
        task tst_ssram_seq;
 
                parameter MAX_CYC_DELAY = 5;
                parameter MAX_STB_DELAY = 5;
                parameter SSRAM_TST_RUN = 128;
                parameter [31:0] SSRAM_TST_STARTA = `SSRAM_LOC + (SSRAM_TST_RUN<<2);
                parameter [ 7:0] SSRAM_SEL = SSRAM_TST_STARTA[28:21];
 
                integer n, k;
                reg [31:0] my_adr, dest_adr;
                reg [31:0] my_dat;
                reg [15:0] tmp0, tmp1;
 
                // SSRAM Mode Register bits
                reg [31:0] csc_data, tms_data;
 
                integer cyc_delay, stb_delay, bl;
 
                begin
 
                        $display("\n\n --- SSRAM SEQUENTIAL ACCESS TEST ---\n\n");
 
                        // clear Wishbone-Master-model current-error-counter 
                        wbm.set_cur_err_cnt(0);
 
                        csc_data = {
                                8'h00,       // reserved
                                SSRAM_SEL,   // SEL
                                4'h0,        // reserved
                                1'b1,        // parity enabled
                                1'b0,        // KRO, no meaning for ssram
                                1'b0,        // BAS, no meaning for ssram
                                1'b0,        // WP
                                2'b00,       // MS, no meaning for ssram
                                2'b10,       // BW == 32bit bus. Always for ssram (maybe hardwire ???)
                                3'b001,      // MEM_TYPE == SDRAM
                                1'b1         // EN == chip select enabled
                        };
 
                        // tms_data is unused for ssrams
                        tms_data = {
                                32'hx
                        };
 
                        // program chip select registers
                        $display("\nProgramming SSRAM chip select register.");
                        wbm.wb_write(0, 0, 32'h6000_0030, csc_data); // program cs4 config register (CSC4)
 
                        $display("Programming SSRAM timing register.");
                        wbm.wb_write(0, 0, 32'h6000_0034, tms_data); // program cs4 timing register (TMS4)
 
                        // check written data
                        wbm.wb_cmp(0, 0, 32'h6000_0030, csc_data);
                        wbm.wb_cmp(0, 0, 32'h6000_0034, tms_data);
 
                        cyc_delay = 0;
                        stb_delay = 0;
                        for (cyc_delay = 0; cyc_delay <= MAX_CYC_DELAY; cyc_delay = cyc_delay +1)
                        for (stb_delay = 0; stb_delay <= MAX_STB_DELAY; stb_delay = stb_delay +1)
                        for (bl        = 1; bl        <= 8            ; bl        = bl        +1)
                                begin
 
                                        $display("\nSSRAM sequential test. BL = %d, CYC-delay = %d, STB-delay = ", bl, cyc_delay, stb_delay);
 
                                        // fill sdrams
                                        $display("Filling SSRAM memory...");
                                        my_dat = 0;
                                        for (n=0; n < SSRAM_TST_RUN; n=n+1)
                                        begin
                                                my_adr = SSRAM_TST_STARTA + ( (SSRAM_TST_RUN -n -bl) <<2);
                                                for (k=0; k < bl; k=k+1)
                                                        begin
                                                                // fill destination backwards, but with linear bursts
                                                                dest_adr   = my_adr + (k<<2);
 
                                                                tmp0     = ~dest_adr[15:0] + bl + cyc_delay + stb_delay;
                                                                tmp1     =  dest_adr[15:0] + bl + cyc_delay + stb_delay;
                                                                my_dat   = {tmp0, tmp1};
 
                                                                wbm.wb_write(cyc_delay, stb_delay, dest_adr, my_dat);
                                                        end
                                                end
 
 
                                        // read sdrams
                                        $display("Verifying SSRAM memory contents...");
                                        my_dat = 0;
                                        for (n=0; n < SSRAM_TST_RUN; n=n+1)
                                                begin
                                                        my_adr   = n<<2;
                                                        dest_adr = SSRAM_TST_STARTA + my_adr;
 
                                                        tmp0     = ~dest_adr[15:0] + bl + cyc_delay + stb_delay;
                                                        tmp1     =  dest_adr[15:0] + bl + cyc_delay + stb_delay;
                                                        my_dat   = {tmp0, tmp1};
 
                                                        wbm.wb_cmp(cyc_delay, stb_delay, dest_adr, my_dat);
                                                end
                                end
 
                        repeat(10) @(posedge wb_clk); //wait a while
 
                        // show Wishbone-Master-model current-error-counter 
                        wbm.show_cur_err_cnt;
 
                end
        endtask // test_ssram_seq

Line No.	Rev	Author	Line
1	25	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OpenCores Memory Controller Testbench ////`
4			`//// SSRAM memory devices tests ////`
5			`//// This file is being included by the main testbench ////`
6			`//// ////`
7			`//// Author: Richard Herveille ////`
8			`//// richard@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2001, 2002 Richard Herveille ////`
16			`//// richard@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41			`// $Id: tst_ssram.v,v 1.1 2002-03-06 15:10:34 rherveille Exp $`
42			`//`
43			`// $Date: 2002-03-06 15:10:34 $`
44			`// $Revision: 1.1 $`
45			`// $Author: rherveille $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51			`//`
52
53
54			`////////////////////////////////`
55			`// SSRAM Sequential access test`
56			`//`
57
58			`// 1) Tests ssram sequential address access`
59			`// 2) Tests page switch`
60			`// 3) Test burst-action by filling memory backwards (high addresses first)`
61			`task tst_ssram_seq;`
62
63			`parameter MAX_CYC_DELAY = 5;`
64			`parameter MAX_STB_DELAY = 5;`
65			`parameter SSRAM_TST_RUN = 128;`
66			parameter [31:0] SSRAM_TST_STARTA = `SSRAM_LOC + (SSRAM_TST_RUN<<2);
67			`parameter [ 7:0] SSRAM_SEL = SSRAM_TST_STARTA[28:21];`
68
69			`integer n, k;`
70			`reg [31:0] my_adr, dest_adr;`
71			`reg [31:0] my_dat;`
72			`reg [15:0] tmp0, tmp1;`
73
74			`// SSRAM Mode Register bits`
75			`reg [31:0] csc_data, tms_data;`
76
77			`integer cyc_delay, stb_delay, bl;`
78
79			`begin`
80
81			`$display("\n\n --- SSRAM SEQUENTIAL ACCESS TEST ---\n\n");`
82
83			`// clear Wishbone-Master-model current-error-counter`
84			`wbm.set_cur_err_cnt(0);`
85
86			`csc_data = {`
87			`8'h00, // reserved`
88			`SSRAM_SEL, // SEL`
89			`4'h0, // reserved`
90			`1'b1, // parity enabled`
91			`1'b0, // KRO, no meaning for ssram`
92			`1'b0, // BAS, no meaning for ssram`
93			`1'b0, // WP`
94			`2'b00, // MS, no meaning for ssram`
95			`2'b10, // BW == 32bit bus. Always for ssram (maybe hardwire ???)`
96			`3'b001, // MEM_TYPE == SDRAM`
97			`1'b1 // EN == chip select enabled`
98			`};`
99
100			`// tms_data is unused for ssrams`
101			`tms_data = {`
102			`32'hx`
103			`};`
104
105			`// program chip select registers`
106			`$display("\nProgramming SSRAM chip select register.");`
107			`wbm.wb_write(0, 0, 32'h6000_0030, csc_data); // program cs4 config register (CSC4)`
108
109			`$display("Programming SSRAM timing register.");`
110			`wbm.wb_write(0, 0, 32'h6000_0034, tms_data); // program cs4 timing register (TMS4)`
111
112			`// check written data`
113			`wbm.wb_cmp(0, 0, 32'h6000_0030, csc_data);`
114			`wbm.wb_cmp(0, 0, 32'h6000_0034, tms_data);`
115
116			`cyc_delay = 0;`
117			`stb_delay = 0;`
118			`for (cyc_delay = 0; cyc_delay <= MAX_CYC_DELAY; cyc_delay = cyc_delay +1)`
119			`for (stb_delay = 0; stb_delay <= MAX_STB_DELAY; stb_delay = stb_delay +1)`
120			`for (bl = 1; bl <= 8 ; bl = bl +1)`
121			`begin`
122
123			`$display("\nSSRAM sequential test. BL = %d, CYC-delay = %d, STB-delay = ", bl, cyc_delay, stb_delay);`
124
125			`// fill sdrams`
126			`$display("Filling SSRAM memory...");`
127			`my_dat = 0;`
128			`for (n=0; n < SSRAM_TST_RUN; n=n+1)`
129			`begin`
130			`my_adr = SSRAM_TST_STARTA + ( (SSRAM_TST_RUN -n -bl) <<2);`
131			`for (k=0; k < bl; k=k+1)`
132			`begin`
133			`// fill destination backwards, but with linear bursts`
134			`dest_adr = my_adr + (k<<2);`
135
136			`tmp0 = ~dest_adr[15:0] + bl + cyc_delay + stb_delay;`
137			`tmp1 = dest_adr[15:0] + bl + cyc_delay + stb_delay;`
138			`my_dat = {tmp0, tmp1};`
139
140			`wbm.wb_write(cyc_delay, stb_delay, dest_adr, my_dat);`
141			`end`
142			`end`
143
144
145			`// read sdrams`
146			`$display("Verifying SSRAM memory contents...");`
147			`my_dat = 0;`
148			`for (n=0; n < SSRAM_TST_RUN; n=n+1)`
149			`begin`
150			`my_adr = n<<2;`
151			`dest_adr = SSRAM_TST_STARTA + my_adr;`
152
153			`tmp0 = ~dest_adr[15:0] + bl + cyc_delay + stb_delay;`
154			`tmp1 = dest_adr[15:0] + bl + cyc_delay + stb_delay;`
155			`my_dat = {tmp0, tmp1};`
156
157			`wbm.wb_cmp(cyc_delay, stb_delay, dest_adr, my_dat);`
158			`end`
159			`end`
160
161			`repeat(10) @(posedge wb_clk); //wait a while`
162
163			`// show Wishbone-Master-model current-error-counter`
164			`wbm.show_cur_err_cnt;`
165
166			`end`
167			`endtask // test_ssram_seq`

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[/] [mem_ctrl/] [trunk/] [bench/] [richard/] [verilog/] [tst_ssram.v] - Blame information for rev 29