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[/] [mem_ctrl/] [trunk/] [bench/] [richard/] [verilog/] [wb_master_model.v] - Blame information for rev 29

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///////////////////////////////////////////////////////////////////////
////                                                               ////
////  WISHBONE rev.B2 Wishbone Master model                        ////
////                                                               ////
////                                                               ////
////  Author: Richard Herveille                                    ////
////          richard@asics.ws                                     ////
////          www.asics.ws                                         ////
////                                                               ////
////  Downloaded from: http://www.opencores.org/projects/mem_ctrl  ////
////                                                               ////
///////////////////////////////////////////////////////////////////////
////                                                               ////
//// Copyright (C) 2001 Richard Herveille                          ////
////                    richard@asics.ws                           ////
////                                                               ////
//// This source file may be used and distributed without          ////
//// restriction provided that this copyright statement is not     ////
//// removed from the file and that any derivative work contains   ////
//// the original copyright notice and the associated disclaimer.  ////
////                                                               ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY       ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED     ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS     ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR        ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,           ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES      ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE     ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR          ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT    ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT    ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE           ////
//// POSSIBILITY OF SUCH DAMAGE.                                   ////
////                                                               ////
///////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_master_model.v,v 1.1 2002-03-06 15:10:34 rherveille Exp $
//
//  $Date: 2002-03-06 15:10:34 $
//  $Revision: 1.1 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//
`include "timescale.v"
 
module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
 
        //
        // parameters
        //
        parameter dwidth = 32;
        parameter awidth = 32;
 
        //
        // inputs & outputs
        //
        input                  clk, rst;
        output [awidth   -1:0]   adr;
        input  [dwidth   -1:0]   din;
        output [dwidth   -1:0]   dout;
        output                 cyc, stb;
        output                          we;
        output [dwidth/8 -1:0] sel;
        input                           ack, err, rty;
 
        //
        // variables
        //
        reg     [awidth   -1:0]  adr;
        reg     [dwidth   -1:0]  dout;
        reg                            cyc, stb;
        reg                            we;
        reg [dwidth/8 -1:0] sel;
 
        reg [dwidth   -1:0] q;
 
        integer err_cur_cnt, err_tot_cnt, err_wb_cnt, err_watchdog;
 
 
        //
        // module body
        //
 
        // check ack, err and rty assertion
        always@(ack or err or rty)
        begin
                case ({ack, err, rty})
                        // ok-states
//                      3'b000: // none asserted
//                      3'b001: // only rty asserted
//                      3'b010: // only err asserted
//                      3'b100: // only ack asserted
 
                        // fault-states
                        3'b011: // oops, err and rty
                                begin
                                        err_wb_cnt = err_wb_cnt +1;
                                        $display("Wishbone error: ERR_I and RTY_I are both asserted at time %t.", $time);
                                end
                        3'b101: // oops, ack and rty
                                begin
                                        err_wb_cnt = err_wb_cnt +1;
                                        $display("Wishbone error: ACK_I and RTY_I are both asserted at time %t.", $time);
                                end
                        3'b110: // oops, ack and err
                                begin
                                        err_wb_cnt = err_wb_cnt +1;
                                        $display("Wishbone error: ACK_I and ERR_I are both asserted at time %t.", $time);
                                end
                        3'b111: // oops, ack, err and rty
                                begin
                                        err_wb_cnt = err_wb_cnt +1;
                                        $display("Wishbone error: ACK_I, ERR_I and RTY_I are all asserted at time %t.", $time);
                                end
                endcase
 
                if (err_wb_cnt > err_watchdog)
                        begin
                                $display("\nTestbench stopped. More than %d wishbone errors detected.\n", err_watchdog);
                                $stop;
                        end
        end
 
        // initial settings
        initial
        begin
                //adr = 32'hxxxx_xxxx;
                //adr = 0;
                adr  = {awidth{1'bx}};
                dout = {dwidth{1'bx}};
                cyc  = 1'b0;
                stb  = 1'bx;
                we   = 1'hx;
                sel  = {dwidth/8{1'bx}};
 
                err_tot_cnt = 0;
                err_cur_cnt = 0;
                err_wb_cnt  = 0;
                err_watchdog = 10;
 
                #1;
                $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
        end
 
 
        ////////////////////////////
        //
        // Wishbone write cycle
        //
 
        task wb_write;
                input   delay;
                integer delay;
                input   stb_delay;
                integer stb_delay;
 
                input   [awidth -1:0]    a;
                input   [dwidth -1:0]    d;
 
        begin
 
                // wait initial delay
                repeat(delay) @(posedge clk);
 
                #1;
                // assert cyc_signal
                cyc  = 1'b1;
                stb  = 1'b0;
 
                // wait for stb_assertion
                repeat(stb_delay) @(posedge clk);
 
                // assert wishbone signals
                adr  = a;
                dout = d;
                stb  = 1'b1;
                we   = 1'b1;
                sel  = {dwidth/8{1'b1}};
                @(posedge clk);
 
                // wait for acknowledge from slave
                // err is treated as normal ack
                // rty is ignored (thus retrying cycle)
                while(~ (ack || err))   @(posedge clk);
 
                // negate wishbone signals
                #1;
                cyc  = 1'b0;
                stb  = 1'bx;
                adr  = {awidth{1'bx}};
                dout = {dwidth{1'bx}};
                we   = 1'hx;
                sel  = {dwidth/8{1'bx}};
 
        end
        endtask
 
        task wb_write_sel;
                input   delay;
                integer delay;
                input   stb_delay;
                integer stb_delay;
 
                input [dwidth/8 -1:0] s;
                input   [awidth   -1:0]  a;
                input   [dwidth   -1:0]  d;
 
        begin
 
                // wait initial delay
                repeat(delay) @(posedge clk);
 
                #1;
                // assert cyc_signal
                cyc  = 1'b1;
                stb  = 1'b0;
 
                // wait for stb_assertion
                repeat(stb_delay) @(posedge clk);
 
                // assert wishbone signals
                adr  = a;
                dout = d;
                stb  = 1'b1;
                we   = 1'b1;
                sel  = s;
                @(posedge clk);
 
                // wait for acknowledge from slave
                // err is treated as normal ack
                // rty is ignored (thus retrying cycle)
                while(~ (ack || err))   @(posedge clk);
 
                // negate wishbone signals
                #1;
                cyc  = 1'b0;
                stb  = 1'bx;
                adr  = {awidth{1'bx}};
                dout = {dwidth{1'bx}};
                we   = 1'hx;
                sel  = {dwidth/8{1'bx}};
 
        end
        endtask
 
        ////////////////////////////
        //
        // Wishbone read cycle
        //
 
        task wb_read;
                input   delay;
                integer delay;
                input   stb_delay;
                integer stb_delay;
 
                input    [awidth -1:0]   a;
                output  [dwidth -1:0]    d;
 
        begin
 
                // wait initial delay
                repeat(delay) @(posedge clk);
 
                #1;
                // assert cyc_signal
                cyc  = 1'b1;
                stb  = 1'b0;
 
                // wait for stb_assertion
                repeat(stb_delay) @(posedge clk);
 
                // assert wishbone signals
                adr  = a;
                dout = {dwidth{1'bx}};
                stb  = 1'b1;
                we   = 1'b0;
                sel  = {dwidth/8{1'b1}};
                @(posedge clk);
 
                // wait for acknowledge from slave
                // err is treated as normal ack
                // rty is ignored (thus retrying cycle)
                while(~ (ack || err))   @(posedge clk);
 
                // negate wishbone signals
                #1;
                cyc  = 1'b0;
                stb  = 1'bx;
                adr  = {awidth{1'bx}};
                dout = {dwidth{1'bx}};
                we   = 1'hx;
                sel  = {dwidth/8{1'bx}};
                d    = din;
 
        end
        endtask
 
        task wb_read_sel;
                input   delay;
                integer delay;
                input   stb_delay;
                integer stb_delay;
 
                input  [dwidth/8 -1:0] s;
                input    [awidth   -1:0] a;
                output  [dwidth   -1:0]  d;
 
        begin
 
                // wait initial delay
                repeat(delay) @(posedge clk);
 
                #1;
                // assert cyc_signal
                cyc  = 1'b1;
                stb  = 1'b0;
 
                // wait for stb_assertion
                repeat(stb_delay) @(posedge clk);
 
                // assert wishbone signals
                adr  = a;
                dout = {dwidth{1'bx}};
                stb  = 1'b1;
                we   = 1'b0;
                sel  = s;
                @(posedge clk);
 
                // wait for acknowledge from slave
                // err is treated as normal ack
                // rty is ignored (thus retrying cycle)
                while(~ (ack || err))   @(posedge clk);
 
                // negate wishbone signals
                #1;
                cyc  = 1'b0;
                stb  = 1'bx;
                adr  = {awidth{1'bx}};
                dout = {dwidth{1'bx}};
                we   = 1'hx;
                sel  = {dwidth/8{1'bx}};
                d    = din;
 
        end
        endtask
 
        ////////////////////////////
        //
        // Wishbone compare cycle
        // read data from location and compare with expected data
        //
 
        task wb_cmp;
                input   delay;
                integer delay;
                input   stb_delay;
                integer stb_delay;
 
                input [awidth -1:0]      a;
                input   [dwidth -1:0]    d_exp;
 
        begin
                wb_read (delay, stb_delay, a, q);
 
                if (d_exp !== q)
                        begin
                                err_tot_cnt = err_tot_cnt +1;
                                err_cur_cnt = err_cur_cnt +1;
                                $display("Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q, d_exp, a);
                        end
 
                if (err_tot_cnt > err_watchdog)
                        begin
                                $display("\nTestbench stopped. More than %d errors detected.\n", err_watchdog);
                                $stop;
                        end
        end
        endtask
 
 
        ////////////////////////////
        //
        // Error counter handlers
        //
        task set_cur_err_cnt;
                input value;
        begin
                err_cur_cnt = value;
        end
        endtask
 
        task show_cur_err_cnt;
                $display("\nCurrent errors detected: %d\n", err_cur_cnt);
        endtask
 
        task show_tot_err_cnt;
                $display("\nTotal errors detected: %d\n", err_tot_cnt);
        endtask
 
endmodule
 

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[/] [mem_ctrl/] [trunk/] [bench/] [richard/] [verilog/] [wb_master_model.v] - Blame information for rev 29

Line No.	Rev	Author	Line
1	25	rherveille	`///////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE rev.B2 Wishbone Master model ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/mem_ctrl ////`
11			`//// ////`
12			`///////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer. ////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`///////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40			`// $Id: wb_master_model.v,v 1.1 2002-03-06 15:10:34 rherveille Exp $`
41			`//`
42			`// $Date: 2002-03-06 15:10:34 $`
43			`// $Revision: 1.1 $`
44			`// $Author: rherveille $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`//`
50			`include "timescale.v"
51
52			`module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);`
53
54			`//`
55			`// parameters`
56			`//`
57			`parameter dwidth = 32;`
58			`parameter awidth = 32;`
59
60			`//`
61			`// inputs & outputs`
62			`//`
63			`input clk, rst;`
64			`output [awidth -1:0] adr;`
65			`input [dwidth -1:0] din;`
66			`output [dwidth -1:0] dout;`
67			`output cyc, stb;`
68			`output we;`
69			`output [dwidth/8 -1:0] sel;`
70			`input ack, err, rty;`
71
72			`//`
73			`// variables`
74			`//`
75			`reg [awidth -1:0] adr;`
76			`reg [dwidth -1:0] dout;`
77			`reg cyc, stb;`
78			`reg we;`
79			`reg [dwidth/8 -1:0] sel;`
80
81			`reg [dwidth -1:0] q;`
82
83			`integer err_cur_cnt, err_tot_cnt, err_wb_cnt, err_watchdog;`
84
85
86			`//`
87			`// module body`
88			`//`
89
90			`// check ack, err and rty assertion`
91			`always@(ack or err or rty)`
92			`begin`
93			`case ({ack, err, rty})`
94			`// ok-states`
95			`// 3'b000: // none asserted`
96			`// 3'b001: // only rty asserted`
97			`// 3'b010: // only err asserted`
98			`// 3'b100: // only ack asserted`
99
100			`// fault-states`
101			`3'b011: // oops, err and rty`
102			`begin`
103			`err_wb_cnt = err_wb_cnt +1;`
104			`$display("Wishbone error: ERR_I and RTY_I are both asserted at time %t.", $time);`
105			`end`
106			`3'b101: // oops, ack and rty`
107			`begin`
108			`err_wb_cnt = err_wb_cnt +1;`
109			`$display("Wishbone error: ACK_I and RTY_I are both asserted at time %t.", $time);`
110			`end`
111			`3'b110: // oops, ack and err`
112			`begin`
113			`err_wb_cnt = err_wb_cnt +1;`
114			`$display("Wishbone error: ACK_I and ERR_I are both asserted at time %t.", $time);`
115			`end`
116			`3'b111: // oops, ack, err and rty`
117			`begin`
118			`err_wb_cnt = err_wb_cnt +1;`
119			`$display("Wishbone error: ACK_I, ERR_I and RTY_I are all asserted at time %t.", $time);`
120			`end`
121			`endcase`
122
123			`if (err_wb_cnt > err_watchdog)`
124			`begin`
125			`$display("\nTestbench stopped. More than %d wishbone errors detected.\n", err_watchdog);`
126			`$stop;`
127			`end`
128			`end`
129
130			`// initial settings`
131			`initial`
132			`begin`
133			`//adr = 32'hxxxx_xxxx;`
134			`//adr = 0;`
135			`adr = {awidth{1'bx}};`
136			`dout = {dwidth{1'bx}};`
137			`cyc = 1'b0;`
138			`stb = 1'bx;`
139			`we = 1'hx;`
140			`sel = {dwidth/8{1'bx}};`
141
142			`err_tot_cnt = 0;`
143			`err_cur_cnt = 0;`
144			`err_wb_cnt = 0;`
145			`err_watchdog = 10;`
146
147			`#1;`
148			`$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");`
149			`end`
150
151
152			`////////////////////////////`
153			`//`
154			`// Wishbone write cycle`
155			`//`
156
157			`task wb_write;`
158			`input delay;`
159			`integer delay;`
160			`input stb_delay;`
161			`integer stb_delay;`
162
163			`input [awidth -1:0] a;`
164			`input [dwidth -1:0] d;`
165
166			`begin`
167
168			`// wait initial delay`
169			`repeat(delay) @(posedge clk);`
170
171			`#1;`
172			`// assert cyc_signal`
173			`cyc = 1'b1;`
174			`stb = 1'b0;`
175
176			`// wait for stb_assertion`
177			`repeat(stb_delay) @(posedge clk);`
178
179			`// assert wishbone signals`
180			`adr = a;`
181			`dout = d;`
182			`stb = 1'b1;`
183			`we = 1'b1;`
184			`sel = {dwidth/8{1'b1}};`
185			`@(posedge clk);`
186
187			`// wait for acknowledge from slave`
188			`// err is treated as normal ack`
189			`// rty is ignored (thus retrying cycle)`
190			`while(~ (ack \|\| err)) @(posedge clk);`
191
192			`// negate wishbone signals`
193			`#1;`
194			`cyc = 1'b0;`
195			`stb = 1'bx;`
196			`adr = {awidth{1'bx}};`
197			`dout = {dwidth{1'bx}};`
198			`we = 1'hx;`
199			`sel = {dwidth/8{1'bx}};`
200
201			`end`
202			`endtask`
203
204			`task wb_write_sel;`
205			`input delay;`
206			`integer delay;`
207			`input stb_delay;`
208			`integer stb_delay;`
209
210			`input [dwidth/8 -1:0] s;`
211			`input [awidth -1:0] a;`
212			`input [dwidth -1:0] d;`
213
214			`begin`
215
216			`// wait initial delay`
217			`repeat(delay) @(posedge clk);`
218
219			`#1;`
220			`// assert cyc_signal`
221			`cyc = 1'b1;`
222			`stb = 1'b0;`
223
224			`// wait for stb_assertion`
225			`repeat(stb_delay) @(posedge clk);`
226
227			`// assert wishbone signals`
228			`adr = a;`
229			`dout = d;`
230			`stb = 1'b1;`
231			`we = 1'b1;`
232			`sel = s;`
233			`@(posedge clk);`
234
235			`// wait for acknowledge from slave`
236			`// err is treated as normal ack`
237			`// rty is ignored (thus retrying cycle)`
238			`while(~ (ack \|\| err)) @(posedge clk);`
239
240			`// negate wishbone signals`
241			`#1;`
242			`cyc = 1'b0;`
243			`stb = 1'bx;`
244			`adr = {awidth{1'bx}};`
245			`dout = {dwidth{1'bx}};`
246			`we = 1'hx;`
247			`sel = {dwidth/8{1'bx}};`
248
249			`end`
250			`endtask`
251
252			`////////////////////////////`
253			`//`
254			`// Wishbone read cycle`
255			`//`
256
257			`task wb_read;`
258			`input delay;`
259			`integer delay;`
260			`input stb_delay;`
261			`integer stb_delay;`
262
263			`input [awidth -1:0] a;`
264			`output [dwidth -1:0] d;`
265
266			`begin`
267
268			`// wait initial delay`
269			`repeat(delay) @(posedge clk);`
270
271			`#1;`
272			`// assert cyc_signal`
273			`cyc = 1'b1;`
274			`stb = 1'b0;`
275
276			`// wait for stb_assertion`
277			`repeat(stb_delay) @(posedge clk);`
278
279			`// assert wishbone signals`
280			`adr = a;`
281			`dout = {dwidth{1'bx}};`
282			`stb = 1'b1;`
283			`we = 1'b0;`
284			`sel = {dwidth/8{1'b1}};`
285			`@(posedge clk);`
286
287			`// wait for acknowledge from slave`
288			`// err is treated as normal ack`
289			`// rty is ignored (thus retrying cycle)`
290			`while(~ (ack \|\| err)) @(posedge clk);`
291
292			`// negate wishbone signals`
293			`#1;`
294			`cyc = 1'b0;`
295			`stb = 1'bx;`
296			`adr = {awidth{1'bx}};`
297			`dout = {dwidth{1'bx}};`
298			`we = 1'hx;`
299			`sel = {dwidth/8{1'bx}};`
300			`d = din;`
301
302			`end`
303			`endtask`
304
305			`task wb_read_sel;`
306			`input delay;`
307			`integer delay;`
308			`input stb_delay;`
309			`integer stb_delay;`
310
311			`input [dwidth/8 -1:0] s;`
312			`input [awidth -1:0] a;`
313			`output [dwidth -1:0] d;`
314
315			`begin`
316
317			`// wait initial delay`
318			`repeat(delay) @(posedge clk);`
319
320			`#1;`
321			`// assert cyc_signal`
322			`cyc = 1'b1;`
323			`stb = 1'b0;`
324
325			`// wait for stb_assertion`
326			`repeat(stb_delay) @(posedge clk);`
327
328			`// assert wishbone signals`
329			`adr = a;`
330			`dout = {dwidth{1'bx}};`
331			`stb = 1'b1;`
332			`we = 1'b0;`
333			`sel = s;`
334			`@(posedge clk);`
335
336			`// wait for acknowledge from slave`
337			`// err is treated as normal ack`
338			`// rty is ignored (thus retrying cycle)`
339			`while(~ (ack \|\| err)) @(posedge clk);`
340
341			`// negate wishbone signals`
342			`#1;`
343			`cyc = 1'b0;`
344			`stb = 1'bx;`
345			`adr = {awidth{1'bx}};`
346			`dout = {dwidth{1'bx}};`
347			`we = 1'hx;`
348			`sel = {dwidth/8{1'bx}};`
349			`d = din;`
350
351			`end`
352			`endtask`
353
354			`////////////////////////////`
355			`//`
356			`// Wishbone compare cycle`
357			`// read data from location and compare with expected data`
358			`//`
359
360			`task wb_cmp;`
361			`input delay;`
362			`integer delay;`
363			`input stb_delay;`
364			`integer stb_delay;`
365
366			`input [awidth -1:0] a;`
367			`input [dwidth -1:0] d_exp;`
368
369			`begin`
370			`wb_read (delay, stb_delay, a, q);`
371
372			`if (d_exp !== q)`
373			`begin`
374			`err_tot_cnt = err_tot_cnt +1;`
375			`err_cur_cnt = err_cur_cnt +1;`
376			`$display("Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q, d_exp, a);`
377			`end`
378
379			`if (err_tot_cnt > err_watchdog)`
380			`begin`
381			`$display("\nTestbench stopped. More than %d errors detected.\n", err_watchdog);`
382			`$stop;`
383			`end`
384			`end`
385			`endtask`
386
387
388			`////////////////////////////`
389			`//`
390			`// Error counter handlers`
391			`//`
392			`task set_cur_err_cnt;`
393			`input value;`
394			`begin`
395			`err_cur_cnt = value;`
396			`end`
397			`endtask`
398
399			`task show_cur_err_cnt;`
400			`$display("\nCurrent errors detected: %d\n", err_cur_cnt);`
401			`endtask`
402
403			`task show_tot_err_cnt;`
404			`$display("\nTotal errors detected: %d\n", err_tot_cnt);`
405			`endtask`
406
407			`endmodule`
408