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[/] [mem_ctrl/] [trunk/] [bench/] [verilog/] [160b3ver/] [dp160b3b.v] - Blame information for rev 29

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/*
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 INTEL DEVELOPER'S SOFTWARE LICENSE AGREEMENT
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BY USING THIS SOFTWARE, YOU ARE AGREEING TO BE BOUND BY THE TERMS OF
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THIS AGREEMENT.  DO NOT USE THE SOFTWARE UNTIL YOU HAVE CAREFULLY READ
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AND AGREED TO THE FOLLOWING TERMS AND CONDITIONS.  IF YOU DO NOT AGREE
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TO THE TERMS OF THIS AGREEMENT, PROMPTLY RETURN THE SOFTWARE PACKAGE AND
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ANY ACCOMPANYING ITEMS.
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IF YOU USE THIS SOFTWARE, YOU WILL BE BOUND BY THE TERMS OF THIS
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AGREEMENT
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LICENSE: Intel Corporation ("Intel") grants you the non-exclusive right
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to use the enclosed software program ("Software").  You will not use,
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copy, modify, rent, sell or transfer the Software or any portion
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thereof, except as provided in this Agreement.
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System OEM Developers may:
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1.      Copy the Software for support, backup or archival purposes;
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2.      Install, use, or distribute Intel owned Software in object code
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4.      Install, use, modify, distribute, and/or make or have made
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        terms and conditions in this Agreement, ONLY if you are a System
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        OEM Developer and NOT an end-user.
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RESTRICTIONS:
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*/
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//****************************************************************************
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// This file contains the paramenters which define the part for the
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// Smart 3 Advanced Boot Block memory model (adv_bb.v).  The '2.7V Vcc Timing'
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// parameters are representative of the 28F160B3-120 operating at 2.7-3.6V Vcc.
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// These parameters need to be changed if the 28F160B3-150 operating at
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// 2.7-3.6V Vcc is to be modeled.  The parameters were taken from the Smart 3 
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// Advanced Boot Block Flash Memory Family datasheet (Order Number 290580).
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// This file must be loaded before the main model, as it contains
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// definitions required by the model.
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//28F160B3-B
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`define BlockFileBegin  "f160b3b.bkb"   //starting addresses of each block
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`define BlockFileEnd    "f160b3b.bke"   //ending addresses of each block
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`define BlockFileType   "f160b3b.bkt"   //block types
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//Available Vcc supported by the device.
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`define VccLevels       4       //Bit 0 - 5V, Bit 1 = 3.3V, Bit 2 = 2.7V
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`define AddrSize        20          //number of address pins
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`define MaxAddr         `AddrSize'hFFFFF    // device ending address
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`define MainArraySize   0:`MaxAddr  //array definition in bytes
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                                    //include A-1 for 8 bit mode
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`define MaxOutputs      16          //number of output pins
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`define NumberOfBlocks  39          //number of blocks in the array
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`define ID_DeviceCodeB      'h8891  //160B3 Bottom
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`define ID_ManufacturerB    'h0089
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// Timing parameters.  See the data sheet for definition of the parameter.
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// Only the WE# controlled write timing parameters are used since their
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// respective CE# controlled write timing parameters have the same value.
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// The model does not differentiate between the two types of writes.
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//2.7V Vcc Timing
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`define TAVAV_27            120
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`define TAVQV_27            120
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`define TELQV_27            120
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`define TPHQV_27            600
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`define TGLQV_27             65
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`define TELQX_27              0
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`define TEHQZ_27             55
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`define TGLQX_27              0
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`define TGHQZ_27             45
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`define TOH_27                0
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`define TPHWL_27            600
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`define TWLWH_27             90
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`define TDVWH_27             70
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`define TAVWH_27             90
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`define TWHDX_27              0
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`define TWHAX_27              0
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`define TWHWL_27             30
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`define TVPWH_27            200
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// The following constants control how long it take an algorithm to run
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// to scale all times together (for making simulation run faster
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// change the constant later listed as TimerPeriod.  The actual delays
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// are TimerPeriod*xxx_Time, except for the suspend latency times.
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`define TimerPeriod_        1000    //1 usec = 1000ns  requires for
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                                    //following times to be accurate
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// The typical values given in the datasheet are used.
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// reducing the following will reduce simulation time
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//2.7V Vcc, 12V Vpp
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`define AC_ProgramTime_Word_27_12      8       //usecs
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`define AC_EraseTime_Param_27_12       800000  //0.8secs
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`define AC_EraseTime_Main_27_12        1100000 //1.1secs
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 //Latency times are NOT multiplied by TimerPeriod_
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`define AC_Program_Suspend_27_12       5000    //5 usecs
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`define AC_Erase_Suspend_27_12         10000   //10 usecs
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//2.7V Vcc 2.7V Vpp
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`define AC_ProgramTime_Word_27_27      22       //usecs
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`define AC_EraseTime_Param_27_27       1000000  //1sec
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`define AC_EraseTime_Main_27_27        1800000  //1.8secs
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 //Latency times are NOT multiplied by TimerPeriod_
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`define AC_Program_Suspend_27_27       6000     //6 usecs
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`define AC_Erase_Suspend_27_27         13000    //13 usecs

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