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[/] [mem_ctrl/] [trunk/] [bench/] [verilog/] [160b3ver/] [read.me] - Blame information for rev 28

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 INTEL DEVELOPER'S SOFTWARE LICENSE AGREEMENT
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BY USING THIS SOFTWARE, YOU ARE AGREEING TO BE BOUND BY THE TERMS OF
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THIS AGREEMENT.  DO NOT USE THE SOFTWARE UNTIL YOU HAVE CAREFULLY READ
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AND AGREED TO THE FOLLOWING TERMS AND CONDITIONS.  IF YOU DO NOT AGREE
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TO THE TERMS OF THIS AGREEMENT, PROMPTLY RETURN THE SOFTWARE PACKAGE AND
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ANY ACCOMPANYING ITEMS.
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IF YOU USE THIS SOFTWARE, YOU WILL BE BOUND BY THE TERMS OF THIS
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AGREEMENT
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LICENSE: Intel Corporation ("Intel") grants you the non-exclusive right
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to use the enclosed software program ("Software").  You will not use,
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copy, modify, rent, sell or transfer the Software or any portion
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thereof, except as provided in this Agreement.
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System OEM Developers may:
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1.      Copy the Software for support, backup or archival purposes;
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2.      Install, use, or distribute Intel owned Software in object code
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        only;
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3.      Modify and/or use Software source code that Intel directly makes
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        available to you as an OEM Developer;
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4.      Install, use, modify, distribute, and/or make or have made
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        derivatives ("Derivatives") of Intel owned Software under the
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        terms and conditions in this Agreement, ONLY if you are a System
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        OEM Developer and NOT an end-user.
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RESTRICTIONS:
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YOU WILL NOT:
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1.      Copy the Software, in whole or in part, except as provided for
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        in this Agreement;
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        code format;
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        unless approved by Intel in a prior writing.
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DERIVATIVE WORK: OEM Developers that make or have made Derivatives will
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not be required to provide Intel with a copy of the source or object
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code.  OEM Developers shall be authorized to use, market, sell, and/or
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U.S. GOVERNMENT RESTRICTED RIGHTS: The Software and documentation were
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EXPORT LAWS: You agree that the distribution and export/re-export of the
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APPLICABLE LAW: This Agreement is governed by the laws of the State of
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Any claim arising out of this Agreement will be brought in Santa Clara
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County, California.
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Intel's Smart 3 Advanced Boot Block verilog model consists of 5 files.  One
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file, "adv_bb.v" contains the basic model for the Smart 3 Advanced Boot Block
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Flash Memory Family.  The other files depend upon the device being modeled.
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One file is used to parametize the model (dp*.v) for the specific device.
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This file will call out other files to be loaded which contain:
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        *.bkb   block begin addressed.
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        *.bke   block end addresses.
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        *.bkt   block type information.
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The parameterization file will call out the names of the other files.  This
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file must be loaded into the simulator before the main model file "adv_bb.v"
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as it contains definitions required for the model.  Since the flash device
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can have the boot block at the top or bottom, files containg the block
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information (start address, end address and type) for both top and bottom
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boot block components are included (f160b3b.* for bottom; f160b3t.* for top).
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Test files, t160b3?.v, illustrating the interaction between the microprocessor
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and the flash memory are also included.  These test files can be changed to
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test different scenarios representative of specific applications.

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