OpenCores
URL https://opencores.org/ocsvn/mem_ctrl/mem_ctrl/trunk

Subversion Repositories mem_ctrl

[/] [mem_ctrl/] [trunk/] [bench/] [verilog/] [sdram_models/] [2Mx32/] [bank1.txt] - Blame information for rev 28

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 rudi
32
2
33
3
34
4
35
5
36
6
37
7
38
8
39
9
3a
10
3b
11
3c
12
3d
13
3e
14
3f
15
40
16
41
17
42
18
43
19
44
20
45
21
46
22
47
23
48
24
49
25
4a
26
4b
27
4c
28
4d
29
4e
30
4f
31
50
32
51
33
52
34
53
35
54
36
55
37
56
38
57
39
58
40
59
41
5a
42
5b
43
5c
44
5d
45
5e
46
5f
47
60
48
61
49
62
50
63

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.