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[/] [mem_ctrl/] [trunk/] [bench/] [verilog/] [sdram_models/] [2Mx32/] [mt48lc2m32b2.v] - Blame information for rev 28

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1 4 rudi 
/****************************************************************************************
2 
*
3 
*    File Name:  MT48LC2M32B2.V
4 
*      Version:  0.0g
5 
*         Date:  January 12th, 2000
6 
*        Model:  BUS Functional
7 
*    Simulator:  Model Technology (PC version 5.3 PE)
8 
*
9 
* Dependencies:  None
10 
*
11 
*       Author:  Son P. Huynh
12 
*        Email:  sphuynh@micron.com
13 
*        Phone:  (208) 368-3825
14 
*      Company:  Micron Technology, Inc.
15 
*        Model:  MT48LC2M32B2 (2Meg x 32 x 4 Banks)
16 
*
17 
*  Description:  Micron 64Mb SDRAM Verilog model
18 
*
19 
*   Limitation:  - Doesn't check for 4096 cycle refresh
20 
*
21 
*         Note:  - Set simulator resolution to "ps" accuracy
22 
*                - Set Debug = 0 to disable $display messages
23 
*
24 
*   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
25 
*                WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
26 
*                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
27 
*                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
28 
*
29 
*                Copyright © 1998 Micron Semiconductor Products, Inc.
30 
*                All rights researved
31 
*
32 
* Rev   Author          Phone         Date        Changes
33 
* ----  ----------------------------  ----------  ---------------------------------------
34 
* 0.0g  Son Huynh       208-368-3825  01/12/2000  - Change tRAS + tWR timing check
35 
*       Micron Technology Inc.                    - Change some error messages
36 
*
37 
* 0.0f  Son Huynh       208-368-3825  07/08/1999  - Fix tWR = 1 Clk + 7.5 ns (Auto)
38 
*       Micron Technology Inc.                    - Fix tWR = 15 ns (Manual)
39 
*                                                 - Fix tRP (Autoprecharge to AutoRefresh)
40 
*
41 
* 0.0e  Son Huynh       208-368-3825  12/22/1998  - Fix tWR check for WRITE
42 
*       Micron Technology Inc.                    - Fix Precharge pipeline for R/W
43 
*                                                 - Fix R/W with Concurrent Auto Precharge
44 
*
45 
* 0.0a  Son Huynh       208-368-3825  09/16/1998  - First Release
46 
*       Micron Technology Inc.                    - Simple testbench included
47 
****************************************************************************************/
48 
 
49 
`timescale 1ns / 100ps
50 
 
51 
module mt48lc2m32b2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
52 
 
53 
    parameter addr_bits =      11;
54 
    parameter data_bits =      32;
55 
    parameter col_bits  =       8;
56 
    parameter mem_sizes =  524287;
57 
 
58 
    inout     [data_bits - 1 : 0] Dq;
59 
    input     [addr_bits - 1 : 0] Addr;
60 
    input                 [1 : 0] Ba;
61 
    input                         Clk;
62 
    input                         Cke;
63 
    input                         Cs_n;
64 
    input                         Ras_n;
65 
    input                         Cas_n;
66 
    input                         We_n;
67 
    input                 [3 : 0] Dqm;
68 
 
69 
    reg       [data_bits - 1 : 0] Bank0 [0 : mem_sizes];
70 
    reg       [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
71 
    reg       [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
72 
    reg       [data_bits - 1 : 0] Bank3 [0 : mem_sizes];
73 
 
74 
    reg                   [1 : 0] Bank_addr [0 : 3];                // Bank Address Pipeline
75 
    reg        [col_bits - 1 : 0] Col_addr [0 : 3];                 // Column Address Pipeline
76 
    reg                   [3 : 0] Command [0 : 3];                  // Command Operation Pipeline
77 
    reg                   [3 : 0] Dqm_reg0, Dqm_reg1;               // DQM Operation Pipeline
78 
    reg       [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
79 
 
80 
    reg       [addr_bits - 1 : 0] Mode_reg;
81 
    reg       [data_bits - 1 : 0] Dq_reg, Dq_dqm;
82 
    reg        [col_bits - 1 : 0] Col_temp, Burst_counter;
83 
 
84 
    reg                           Act_b0, Act_b1, Act_b2, Act_b3;   // Bank Activate
85 
    reg                           Pc_b0, Pc_b1, Pc_b2, Pc_b3;       // Bank Precharge
86 
 
87 
    reg                   [1 : 0] Bank_precharge     [0 : 3];       // Precharge Command
88 
    reg                           A10_precharge      [0 : 3];       // Addr[10] = 1 (All banks)
89 
    reg                           Auto_precharge     [0 : 3];       // RW AutoPrecharge (Bank)
90 
    reg                           Read_precharge     [0 : 3];       // R  AutoPrecharge
91 
    reg                           Write_precharge    [0 : 3];       //  W AutoPrecharge
92 
    reg                           RW_interrupt_read  [0 : 3];       // RW Interrupt Read with Auto Precharge
93 
    reg                           RW_interrupt_write [0 : 3];       // RW Interrupt Write with Auto Precharge
94 
    reg                   [1 : 0] RW_interrupt_bank;                // RW interrupt Bank
95 
    time                          Count_time         [0 : 3];       // RW AutoPrecharge (time after tWR = 1)
96 
    integer                       Count_precharge    [0 : 3];       // RW AutoPrecharge (Counter)
97 
 
98 
    reg                           Data_in_enable;
99 
    reg                           Data_out_enable;
100 
 
101 
    reg                   [1 : 0] Bank, Previous_bank;
102 
    reg       [addr_bits - 1 : 0] Row;
103 
    reg        [col_bits - 1 : 0] Col, Col_brst;
104 
 
105 
    // Internal system clock
106 
    reg                           CkeZ, Sys_clk, RAS_clk;
107 
 
108 
    // Commands Decode
109 
    wire      Active_enable    = ~Cs_n & ~Ras_n &  Cas_n &  We_n;
110 
    wire      Aref_enable      = ~Cs_n & ~Ras_n & ~Cas_n &  We_n;
111 
    wire      Burst_term       = ~Cs_n &  Ras_n &  Cas_n & ~We_n;
112 
    wire      Mode_reg_enable  = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n;
113 
    wire      Prech_enable     = ~Cs_n & ~Ras_n &  Cas_n & ~We_n;
114 
    wire      Read_enable      = ~Cs_n &  Ras_n & ~Cas_n &  We_n;
115 
    wire      Write_enable     = ~Cs_n &  Ras_n & ~Cas_n & ~We_n;
116 
 
117 
    // Burst Length Decode
118 
    wire      Burst_length_1   = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0];
119 
    wire      Burst_length_2   = ~Mode_reg[2] & ~Mode_reg[1] &  Mode_reg[0];
120 
    wire      Burst_length_4   = ~Mode_reg[2] &  Mode_reg[1] & ~Mode_reg[0];
121 
    wire      Burst_length_8   = ~Mode_reg[2] &  Mode_reg[1] &  Mode_reg[0];
122 
 
123 
    // CAS Latency Decode
124 
    wire      Cas_latency_1    = ~Mode_reg[6] & ~Mode_reg[5] &  Mode_reg[4];
125 
    wire      Cas_latency_2    = ~Mode_reg[6] &  Mode_reg[5] & ~Mode_reg[4];
126 
    wire      Cas_latency_3    = ~Mode_reg[6] &  Mode_reg[5] &  Mode_reg[4];
127 
 
128 
    // Write Burst Mode
129 
    wire      Write_burst_mode = Mode_reg[9];
130 
 
131 
    wire      Debug            = 1'b0;                          // Debug messages : 1 = On
132 
    wire      Dq_chk           = Sys_clk & Data_in_enable;      // Check setup/hold time for DQ
133 
 
134 
    assign    Dq               = Dq_reg;                        // DQ buffer
135 
 
136 
    //Commands Operation
137 
    `define   ACT       0
138 
    `define   NOP       1
139 
    `define   READ      2
140 
    `define   READ_A    3
141 
    `define   WRITE     4
142 
    `define   WRITE_A   5
143 
    `define   PRECH     6
144 
    `define   A_REF     7
145 
    `define   BST       8
146 
    `define   LMR       9
147 
 
148 
    // Timing Parameters for -7 and CAS Latency = 3
149 
    parameter tAC  =   5.5;
150 
    parameter tHZ  =   5.5;
151 
    parameter tOH  =   2.5;
152 
    parameter tMRD =   2.0;     // 2 Clk Cycles
153 
    parameter tRAS =  42.0;
154 
    parameter tRC  =  70.0;
155 
    parameter tRCD =  20.0;
156 
    parameter tRP  =  20.0;
157 
    parameter tRRD =  14.0;
158 
    parameter tWRa =   7.0;     // A2 Version - Auto precharge mode only (1 Clk + 7.0 ns)
159 
    parameter tWRp =  14.0;     // A2 Version - Precharge mode only (14 ns)
160 
 
161 
    // Timing Check variable
162 
    integer   MRD_chk;
163 
    integer   WR_counter [0 : 3];
164 
    time      WR_time [0 : 3];
165 
    time      WR_chkp [0 : 3];
166 
    time      RC_chk, RRD_chk;
167 
    time      RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
168 
    time      RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
169 
    time      RP_chk0, RP_chk1, RP_chk2, RP_chk3;
170 
 
171 
    initial begin
172 
        Dq_reg = {data_bits{1'bz}};
173 
        {Data_in_enable, Data_out_enable} = 0;
174 
        {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000;
175 
        {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000;
176 
        {WR_chkp[0], WR_chkp[1], WR_chkp[2], WR_chkp[3]} = 0;
177 
        {WR_counter[0], WR_counter[1], WR_counter[2], WR_counter[3]} = 0;
178 
        {WR_time[0], WR_time[1], WR_time[2], WR_time[3]} = 0;
179 
        {RW_interrupt_read[0], RW_interrupt_read[1], RW_interrupt_read[2], RW_interrupt_read[3]} = 0;
180 
        {RW_interrupt_write[0], RW_interrupt_write[1], RW_interrupt_write[2], RW_interrupt_write[3]} = 0;
181 
        {MRD_chk, RC_chk, RRD_chk} = 0;
182 
        {RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3} = 0;
183 
        {RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3} = 0;
184 
        {RP_chk0, RP_chk1, RP_chk2, RP_chk3} = 0;
185 
        $timeformat (-9, 0, " ns", 12);
186 
//        $readmemh("bank0.txt", Bank0);
187 
//        $readmemh("bank1.txt", Bank1);
188 
//        $readmemh("bank2.txt", Bank2);
189 
//        $readmemh("bank3.txt", Bank3);
190 
        RAS_clk = 1'b0;
191 
    end
192 
 
193 
integer n;
194 
 
195 
task mem_fill;
196 
input   size;
197 
 
198 
integer         size;
199 
 
200 
begin
201 
        for(n=0;n<size;n=n+1)
202 
           begin
203 
                Bank0[n] = $random;
204 
                Bank1[n] = $random;
205 
                Bank2[n] = $random;
206 
                Bank3[n] = $random;
207 
           end
208 
 
209 
end
210 
endtask
211 
 
212 
 
213 
    // RAS Clk for checking tWR
214 
    always RAS_clk = #0.5 ~RAS_clk;
215 
 
216 
    // System clock generator
217 
    always begin
218 
        @ (posedge Clk) begin
219 
            Sys_clk = CkeZ;
220 
            CkeZ = Cke;
221 
        end
222 
        @ (negedge Clk) begin
223 
            Sys_clk = 1'b0;
224 
        end
225 
    end
226 
 
227 
    always @ (posedge Sys_clk) begin
228 
        // Internal Commamd Pipelined
229 
        Command[0] = Command[1];
230 
        Command[1] = Command[2];
231 
        Command[2] = Command[3];
232 
        Command[3] = `NOP;
233 
 
234 
        Col_addr[0] = Col_addr[1];
235 
        Col_addr[1] = Col_addr[2];
236 
        Col_addr[2] = Col_addr[3];
237 
        Col_addr[3] = {col_bits{1'b0}};
238 
 
239 
        Bank_addr[0] = Bank_addr[1];
240 
        Bank_addr[1] = Bank_addr[2];
241 
        Bank_addr[2] = Bank_addr[3];
242 
        Bank_addr[3] = 2'b0;
243 
 
244 
        Bank_precharge[0] = Bank_precharge[1];
245 
        Bank_precharge[1] = Bank_precharge[2];
246 
        Bank_precharge[2] = Bank_precharge[3];
247 
        Bank_precharge[3] = 2'b0;
248 
 
249 
        A10_precharge[0] = A10_precharge[1];
250 
        A10_precharge[1] = A10_precharge[2];
251 
        A10_precharge[2] = A10_precharge[3];
252 
        A10_precharge[3] = 1'b0;
253 
 
254 
        // Dqm pipeline for Read
255 
        Dqm_reg0 = Dqm_reg1;
256 
        Dqm_reg1 = Dqm;
257 
 
258 
        // Read or Write with Auto Precharge Counter
259 
        if (Auto_precharge[0] == 1'b1) begin
260 
            Count_precharge[0] = Count_precharge[0] + 1;
261 
        end
262 
        if (Auto_precharge[1] == 1'b1) begin
263 
            Count_precharge[1] = Count_precharge[1] + 1;
264 
        end
265 
        if (Auto_precharge[2] == 1'b1) begin
266 
            Count_precharge[2] = Count_precharge[2] + 1;
267 
        end
268 
        if (Auto_precharge[3] == 1'b1) begin
269 
            Count_precharge[3] = Count_precharge[3] + 1;
270 
        end
271 
 
272 
        // Auto Precharge Timer for tWR
273 
        if (Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) begin
274 
            if (Count_precharge[0] == 1) begin
275 
                Count_time[0] = $time;
276 
            end
277 
            if (Count_precharge[1] == 1) begin
278 
                Count_time[1] = $time;
279 
            end
280 
            if (Count_precharge[2] == 1) begin
281 
                Count_time[2] = $time;
282 
            end
283 
            if (Count_precharge[3] == 1) begin
284 
                Count_time[3] = $time;
285 
            end
286 
        end else if (Burst_length_2 == 1'b1) begin
287 
            if (Count_precharge[0] == 2) begin
288 
                Count_time[0] = $time;
289 
            end
290 
            if (Count_precharge[1] == 2) begin
291 
                Count_time[1] = $time;
292 
            end
293 
            if (Count_precharge[2] == 2) begin
294 
                Count_time[2] = $time;
295 
            end
296 
            if (Count_precharge[3] == 2) begin
297 
                Count_time[3] = $time;
298 
            end
299 
        end else if (Burst_length_4 == 1'b1) begin
300 
            if (Count_precharge[0] == 4) begin
301 
                Count_time[0] = $time;
302 
            end
303 
            if (Count_precharge[1] == 4) begin
304 
                Count_time[1] = $time;
305 
            end
306 
            if (Count_precharge[2] == 4) begin
307 
                Count_time[2] = $time;
308 
            end
309 
            if (Count_precharge[3] == 4) begin
310 
                Count_time[3] = $time;
311 
            end
312 
        end else if (Burst_length_8 == 1'b1) begin
313 
            if (Count_precharge[0] == 8) begin
314 
                Count_time[0] = $time;
315 
            end
316 
            if (Count_precharge[1] == 8) begin
317 
                Count_time[1] = $time;
318 
            end
319 
            if (Count_precharge[2] == 8) begin
320 
                Count_time[2] = $time;
321 
            end
322 
            if (Count_precharge[3] == 8) begin
323 
                Count_time[3] = $time;
324 
            end
325 
        end
326 
 
327 
        // tMRD Counter
328 
        MRD_chk = MRD_chk + 1;
329 
 
330 
        // tWR Counter for Write
331 
        WR_counter[0] = WR_counter[0] + 1;
332 
        WR_counter[1] = WR_counter[1] + 1;
333 
        WR_counter[2] = WR_counter[2] + 1;
334 
        WR_counter[3] = WR_counter[3] + 1;
335 
 
336 
        // Auto Refresh
337 
        if (Aref_enable == 1'b1) begin
338 
            if (Debug) $display ("%m at time %t AREF : Auto Refresh", $time);
339 
            // Auto Refresh to Auto Refresh
340 
            if ($time - RC_chk < tRC) begin
341 
                $display ("%m at time %t ERROR: tRC violation during Auto Refresh", $time);
342 
            end
343 
            // Precharge to Auto Refresh
344 
            if ($time - RP_chk0 < tRP || $time - RP_chk1 < tRP || $time - RP_chk2 < tRP || $time - RP_chk3 < tRP) begin
345 
                $display ("%m at time %t ERROR: tRP violation during Auto Refresh", $time);
346 
            end
347 
            // Precharge to Refresh
348 
            if (Pc_b0 == 1'b0 || Pc_b1 == 1'b0 || Pc_b2 == 1'b0 || Pc_b3 == 1'b0) begin
349 
                $display ("%m at time %t ERROR: All banks must be Precharge before Auto Refresh", $time);
350 
            end
351 
            // Record Current tRC time
352 
            RC_chk = $time;
353 
        end
354 
 
355 
        // Load Mode Register
356 
        if (Mode_reg_enable == 1'b1) begin
357 
            // Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode
358 
            if (Pc_b0 == 1'b1 && Pc_b1 == 1'b1 && Pc_b2 == 1'b1 && Pc_b3 == 1'b1) begin
359 
                Mode_reg = Addr;
360 
                if (Debug) begin
361 
                    $display ("%m at time %t LMR  : Load Mode Register", $time);
362 
                    // CAS Latency
363 
                    if (Addr[6 : 4] == 3'b001)
364 
                        $display ("                            CAS Latency      = 1");
365 
                    else if (Addr[6 : 4] == 3'b010)
366 
                        $display ("                            CAS Latency      = 2");
367 
                    else if (Addr[6 : 4] == 3'b011)
368 
                        $display ("                            CAS Latency      = 3");
369 
                    else
370 
                        $display ("                            CAS Latency      = Reserved");
371 
                    // Burst Length
372 
                    if (Addr[2 : 0] == 3'b000)
373 
                        $display ("                            Burst Length     = 1");
374 
                    else if (Addr[2 : 0] == 3'b001)
375 
                        $display ("                            Burst Length     = 2");
376 
                    else if (Addr[2 : 0] == 3'b010)
377 
                        $display ("                            Burst Length     = 4");
378 
                    else if (Addr[2 : 0] == 3'b011)
379 
                        $display ("                            Burst Length     = 8");
380 
                    else if (Addr[3 : 0] == 4'b0111)
381 
                        $display ("                            Burst Length     = Full");
382 
                    else
383 
                        $display ("                            Burst Length     = Reserved");
384 
                    // Burst Type
385 
                    if (Addr[3] == 1'b0)
386 
                        $display ("                            Burst Type       = Sequential");
387 
                    else if (Addr[3] == 1'b1)
388 
                        $display ("                            Burst Type       = Interleaved");
389 
                    else
390 
                        $display ("                            Burst Type       = Reserved");
391 
                    // Write Burst Mode
392 
                    if (Addr[9] == 1'b0)
393 
                        $display ("                            Write Burst Mode = Programmed Burst Length");
394 
                    else if (Addr[9] == 1'b1)
395 
                        $display ("                            Write Burst Mode = Single Location Access");
396 
                    else
397 
                        $display ("                            Write Burst Mode = Reserved");
398 
                end
399 
            end else begin
400 
                $display ("%m at time %t ERROR: all banks must be Precharge before Load Mode Register", $time);
401 
            end
402 
            // REF to LMR
403 
            if ($time - RC_chk < tRC) begin
404 
                $display ("%m at time %t ERROR: tRC violation during Load Mode Register", $time);
405 
            end
406 
            // LMR to LMR
407 
            if (MRD_chk < tMRD) begin
408 
                $display ("%m at time %t ERROR: tMRD violation during Load Mode Register", $time);
409 
            end
410 
            MRD_chk = 0;
411 
        end
412 
 
413 
        // Active Block (Latch Bank Address and Row Address)
414 
        if (Active_enable == 1'b1) begin
415 
            if (Ba == 2'b00 && Pc_b0 == 1'b1) begin
416 
                {Act_b0, Pc_b0} = 2'b10;
417 
                B0_row_addr = Addr [addr_bits - 1 : 0];
418 
                RCD_chk0 = $time;
419 
                RAS_chk0 = $time;
420 
                if (Debug) $display ("%m at time %t ACT  : Bank = 0 Row = %d",$time, Addr);
421 
                // Precharge to Activate Bank 0
422 
                if ($time - RP_chk0 < tRP) begin
423 
                    $display ("%m at time %t ERROR: tRP violation during Activate bank 0", $time);
424 
                end
425 
            end else if (Ba == 2'b01 && Pc_b1 == 1'b1) begin
426 
                {Act_b1, Pc_b1} = 2'b10;
427 
                B1_row_addr = Addr [addr_bits - 1 : 0];
428 
                RCD_chk1 = $time;
429 
                RAS_chk1 = $time;
430 
                if (Debug) $display ("%m at time %t ACT  : Bank = 1 Row = %d",$time, Addr);
431 
                // Precharge to Activate Bank 1
432 
                if ($time - RP_chk1 < tRP) begin
433 
                    $display ("%m at time %t ERROR: tRP violation during Activate bank 1", $time);
434 
                end
435 
            end else if (Ba == 2'b10 && Pc_b2 == 1'b1) begin
436 
                {Act_b2, Pc_b2} = 2'b10;
437 
                B2_row_addr = Addr [addr_bits - 1 : 0];
438 
                RCD_chk2 = $time;
439 
                RAS_chk2 = $time;
440 
                if (Debug) $display ("%m at time %t ACT  : Bank = 2 Row = %d",$time, Addr);
441 
                // Precharge to Activate Bank 2
442 
                if ($time - RP_chk2 < tRP) begin
443 
                    $display ("%m at time %t ERROR: tRP violation during Activate bank 2", $time);
444 
                end
445 
            end else if (Ba == 2'b11 && Pc_b3 == 1'b1) begin
446 
                {Act_b3, Pc_b3} = 2'b10;
447 
                B3_row_addr = Addr [addr_bits - 1 : 0];
448 
                RCD_chk3 = $time;
449 
                RAS_chk3 = $time;
450 
                if (Debug) $display ("%m at time %t ACT  : Bank = 3 Row = %d",$time, Addr);
451 
                // Precharge to Activate Bank 3
452 
                if ($time - RP_chk3 < tRP) begin
453 
                    $display ("%m at time %t ERROR: tRP violation during Activate bank 3", $time);
454 
                end
455 
            end else if (Ba == 2'b00 && Pc_b0 == 1'b0) begin
456 
                $display ("%m at time %t ERROR: Bank 0 is already Activated (not Precharged)", $time);
457 
            end else if (Ba == 2'b01 && Pc_b1 == 1'b0) begin
458 
                $display ("%m at time %t ERROR: Bank 1 is already Activated (not Precharged)", $time);
459 
            end else if (Ba == 2'b10 && Pc_b2 == 1'b0) begin
460 
                $display ("%m at time %t ERROR: Bank 2 is already Activated (not Precharged)", $time);
461 
            end else if (Ba == 2'b11 && Pc_b3 == 1'b0) begin
462 
                $display ("%m at time %t ERROR: Bank 3 is already Activated (not Precharged)", $time);
463 
            end
464 
            // Active Bank A to Active Bank B
465 
            if ((Previous_bank != Ba) && ($time - RRD_chk < tRRD)) begin
466 
                $display ("%m at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba);
467 
            end
468 
            // Load Mode Register to Active
469 
            if (MRD_chk < tMRD ) begin
470 
                $display ("%m at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba);
471 
            end
472 
            // Auto Refresh to Activate
473 
            if ($time - RC_chk < tRC) begin
474 
                $display ("%m at time %t ERROR: tRC violation during Activate bank = %d", $time, Ba);
475 
            end
476 
            // Record variables for checking violation
477 
            RRD_chk = $time;
478 
            Previous_bank = Ba;
479 
        end
480 
 
481 
        // Precharge Block
482 
        if (Prech_enable == 1'b1) begin
483 
            if (Addr[10] == 1'b1) begin
484 
                {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b1111;
485 
                {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000;
486 
                RP_chk0 = $time;
487 
                RP_chk1 = $time;
488 
                RP_chk2 = $time;
489 
                RP_chk3 = $time;
490 
                if (Debug) $display ("%m at time %t PRE  : Bank = ALL",$time);
491 
                // Activate to Precharge all banks
492 
                if (($time - RAS_chk0 < tRAS) || ($time - RAS_chk1 < tRAS) ||
493 
                    ($time - RAS_chk2 < tRAS) || ($time - RAS_chk3 < tRAS)) begin
494 
                    $display ("%m at time %t ERROR: tRAS violation during Precharge all bank", $time);
495 
                end
496 
                // tWR violation check for write
497 
                if (($time - WR_chkp[0] < tWRp) || ($time - WR_chkp[1] < tWRp) ||
498 
                    ($time - WR_chkp[2] < tWRp) || ($time - WR_chkp[3] < tWRp)) begin
499 
                    $display ("%m at time %t ERROR: tWR violation during Precharge all bank", $time);
500 
                end
501 
            end else if (Addr[10] == 1'b0) begin
502 
                if (Ba == 2'b00) begin
503 
                    {Pc_b0, Act_b0} = 2'b10;
504 
                    RP_chk0 = $time;
505 
                    if (Debug) $display ("%m at time %t PRE  : Bank = 0",$time);
506 
                    // Activate to Precharge Bank 0
507 
                    if ($time - RAS_chk0 < tRAS) begin
508 
                        $display ("%m at time %t ERROR: tRAS violation during Precharge bank 0", $time);
509 
                    end
510 
                end else if (Ba == 2'b01) begin
511 
                    {Pc_b1, Act_b1} = 2'b10;
512 
                    RP_chk1 = $time;
513 
                    if (Debug) $display ("%m at time %t PRE  : Bank = 1",$time);
514 
                    // Activate to Precharge Bank 1
515 
                    if ($time - RAS_chk1 < tRAS) begin
516 
                        $display ("%m at time %t ERROR: tRAS violation during Precharge bank 1", $time);
517 
                    end
518 
                end else if (Ba == 2'b10) begin
519 
                    {Pc_b2, Act_b2} = 2'b10;
520 
                    RP_chk2 = $time;
521 
                    if (Debug) $display ("%m at time %t PRE  : Bank = 2",$time);
522 
                    // Activate to Precharge Bank 2
523 
                    if ($time - RAS_chk2 < tRAS) begin
524 
                        $display ("%m at time %t ERROR: tRAS violation during Precharge bank 2", $time);
525 
                    end
526 
                end else if (Ba == 2'b11) begin
527 
                    {Pc_b3, Act_b3} = 2'b10;
528 
                    RP_chk3 = $time;
529 
                    if (Debug) $display ("%m at time %t PRE  : Bank = 3",$time);
530 
                    // Activate to Precharge Bank 3
531 
                    if ($time - RAS_chk3 < tRAS) begin
532 
                        $display ("%m at time %t ERROR: tRAS violation during Precharge bank 3", $time);
533 
                    end
534 
                end
535 
                // tWR violation check for write
536 
                if ($time - WR_chkp[Ba] < tWRp) begin
537 
                    $display ("%m at time %t ERROR: tWR violation during Precharge bank %d", $time, Ba);
538 
                end
539 
            end
540 
 
541 
            // Terminate a Write Immediately (if same bank or all banks)
542 
            if (Data_in_enable == 1'b1 && (Bank == Ba || Addr[10] == 1'b1)) begin
543 
                Data_in_enable = 1'b0;
544 
            end
545 
 
546 
            // Precharge Command Pipeline for Read
547 
            if (Cas_latency_3 == 1'b1) begin
548 
                Command[2] = `PRECH;
549 
                Bank_precharge[2] = Ba;
550 
                A10_precharge[2] = Addr[10];
551 
            end else if (Cas_latency_2 == 1'b1) begin
552 
                Command[1] = `PRECH;
553 
                Bank_precharge[1] = Ba;
554 
                A10_precharge[1] = Addr[10];
555 
            end else if (Cas_latency_1 == 1'b1) begin
556 
                Command[0] = `PRECH;
557 
                Bank_precharge[0] = Ba;
558 
                A10_precharge[0] = Addr[10];
559 
            end
560 
        end
561 
 
562 
        // Burst terminate
563 
        if (Burst_term == 1'b1) begin
564 
            // Terminate a Write Immediately
565 
            if (Data_in_enable == 1'b1) begin
566 
                Data_in_enable = 1'b0;
567 
            end
568 
            // Terminate a Read Depend on CAS Latency
569 
            if (Cas_latency_3 == 1'b1) begin
570 
                Command[2] = `BST;
571 
            end else if (Cas_latency_2 == 1'b1) begin
572 
                Command[1] = `BST;
573 
            end else if (Cas_latency_1 == 1'b1) begin
574 
                Command[0] = `BST;
575 
            end
576 
            if (Debug) $display ("%m at time %t BST  : Burst Terminate",$time);
577 
        end
578 
 
579 
        // Read, Write, Column Latch
580 
        if (Read_enable == 1'b1 || Write_enable == 1'b1) begin
581 
            // Check to see if bank is open (ACT)
582 
            if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) ||
583 
                (Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin
584 
                $display("%m at time %t ERROR: Cannot Read or Write - Bank %d is not Activated", $time, Ba);
585 
            end
586 
            // Activate to Read or Write
587 
            if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD))
588 
                $display("%m at time %t ERROR: tRCD violation during Read or Write to Bank 0", $time);
589 
            if ((Ba == 2'b01) && ($time - RCD_chk1 < tRCD))
590 
                $display("%m at time %t ERROR: tRCD violation during Read or Write to Bank 1", $time);
591 
            if ((Ba == 2'b10) && ($time - RCD_chk2 < tRCD))
592 
                $display("%m at time %t ERROR: tRCD violation during Read or Write to Bank 2", $time);
593 
            if ((Ba == 2'b11) && ($time - RCD_chk3 < tRCD))
594 
                $display("%m at time %t ERROR: tRCD violation during Read or Write to Bank 3", $time);
595 
            // Read Command
596 
            if (Read_enable == 1'b1) begin
597 
                // CAS Latency pipeline
598 
                if (Cas_latency_3 == 1'b1) begin
599 
                    if (Addr[10] == 1'b1) begin
600 
                        Command[2] = `READ_A;
601 
                    end else begin
602 
                        Command[2] = `READ;
603 
                    end
604 
                    Col_addr[2] = Addr;
605 
                    Bank_addr[2] = Ba;
606 
                end else if (Cas_latency_2 == 1'b1) begin
607 
                    if (Addr[10] == 1'b1) begin
608 
                        Command[1] = `READ_A;
609 
                    end else begin
610 
                        Command[1] = `READ;
611 
                    end
612 
                    Col_addr[1] = Addr;
613 
                    Bank_addr[1] = Ba;
614 
                end else if (Cas_latency_1 == 1'b1) begin
615 
                    if (Addr[10] == 1'b1) begin
616 
                        Command[0] = `READ_A;
617 
                    end else begin
618 
                        Command[0] = `READ;
619 
                    end
620 
                    Col_addr[0] = Addr;
621 
                    Bank_addr[0] = Ba;
622 
                end
623 
 
624 
                // Read interrupt Write (terminate Write immediately)
625 
                if (Data_in_enable == 1'b1) begin
626 
                    Data_in_enable = 1'b0;
627 
                end
628 
 
629 
            // Write Command
630 
            end else if (Write_enable == 1'b1) begin
631 
                if (Addr[10] == 1'b1) begin
632 
                    Command[0] = `WRITE_A;
633 
                end else begin
634 
                    Command[0] = `WRITE;
635 
                end
636 
                Col_addr[0] = Addr;
637 
                Bank_addr[0] = Ba;
638 
 
639 
                // Write interrupt Write (terminate Write immediately)
640 
                if (Data_in_enable == 1'b1) begin
641 
                    Data_in_enable = 1'b0;
642 
                end
643 
 
644 
                // Write interrupt Read (terminate Read immediately)
645 
                if (Data_out_enable == 1'b1) begin
646 
                    Data_out_enable = 1'b0;
647 
                end
648 
            end
649 
 
650 
            // Interrupting a Write with Autoprecharge
651 
            if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
652 
                RW_interrupt_write[RW_interrupt_bank] = 1'b1;
653 
                WR_time[RW_interrupt_bank] = $time;
654 
                if (Debug) $display ("%m at time %t NOTE : Read/Write Bank %d interrupt Write Bank %d with Autoprecharge", $time, Ba, RW_interrupt_bank);
655 
            end
656 
 
657 
            // Interrupting a Read with Autoprecharge
658 
            if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Read_precharge[RW_interrupt_bank] == 1'b1) begin
659 
                RW_interrupt_read[RW_interrupt_bank] = 1'b1;
660 
                if (Debug) $display ("%m at time %t NOTE : Read/Write Bank %d interrupt Read Bank %d with Autoprecharge", $time, Ba, RW_interrupt_bank);
661 
            end
662 
 
663 
            // Read or Write with Auto Precharge
664 
            if (Addr[10] == 1'b1) begin
665 
                Auto_precharge[Ba] = 1'b1;
666 
                Count_precharge[Ba] = 0;
667 
                RW_interrupt_bank = Ba;
668 
                if (Read_enable == 1'b1) begin
669 
                    Read_precharge[Ba] = 1'b1;
670 
                end else if (Write_enable == 1'b1) begin
671 
                    Write_precharge[Ba] = 1'b1;
672 
                end
673 
            end
674 
        end
675 
 
676 
        //  Read with Auto Precharge Calculation
677 
        //      The device start internal precharge:
678 
        //          1.  CAS Latency - 1 cycles before last burst
679 
        //      and 2.  Meet minimum tRAS requirement
680 
        //       or 3.  Interrupt by a Read or Write (with or without AutoPrecharge)
681 
        if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin
682 
            if ((($time - RAS_chk0 >= tRAS) &&                                                      // Case 2
683 
                ((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) ||                             // Case 1
684 
                 (Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) ||
685 
                 (Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) ||
686 
                 (Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) ||
687 
                 (RW_interrupt_read[0] == 1'b1)) begin                                              // Case 3
688 
                    Pc_b0 = 1'b1;
689 
                    Act_b0 = 1'b0;
690 
                    RP_chk0 = $time;
691 
                    Auto_precharge[0] = 1'b0;
692 
                    Read_precharge[0] = 1'b0;
693 
                    RW_interrupt_read[0] = 1'b0;
694 
                    if (Debug) $display ("%m at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
695 
            end
696 
        end
697 
        if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin
698 
            if ((($time - RAS_chk1 >= tRAS) &&
699 
                ((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) ||
700 
                 (Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) ||
701 
                 (Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) ||
702 
                 (Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) ||
703 
                 (RW_interrupt_read[1] == 1'b1)) begin
704 
                    Pc_b1 = 1'b1;
705 
                    Act_b1 = 1'b0;
706 
                    RP_chk1 = $time;
707 
                    Auto_precharge[1] = 1'b0;
708 
                    Read_precharge[1] = 1'b0;
709 
                    RW_interrupt_read[1] = 1'b0;
710 
                    if (Debug) $display ("%m at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
711 
            end
712 
        end
713 
        if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin
714 
            if ((($time - RAS_chk2 >= tRAS) &&
715 
                ((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) ||
716 
                 (Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) ||
717 
                 (Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) ||
718 
                 (Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) ||
719 
                 (RW_interrupt_read[2] == 1'b1)) begin
720 
                    Pc_b2 = 1'b1;
721 
                    Act_b2 = 1'b0;
722 
                    RP_chk2 = $time;
723 
                    Auto_precharge[2] = 1'b0;
724 
                    Read_precharge[2] = 1'b0;
725 
                    RW_interrupt_read[2] = 1'b0;
726 
                    if (Debug) $display ("%m at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
727 
            end
728 
        end
729 
        if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin
730 
            if ((($time - RAS_chk3 >= tRAS) &&
731 
                ((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) ||
732 
                 (Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) ||
733 
                 (Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) ||
734 
                 (Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) ||
735 
                 (RW_interrupt_read[3] == 1'b1)) begin
736 
                    Pc_b3 = 1'b1;
737 
                    Act_b3 = 1'b0;
738 
                    RP_chk3 = $time;
739 
                    Auto_precharge[3] = 1'b0;
740 
                    Read_precharge[3] = 1'b0;
741 
                    RW_interrupt_read[3] = 1'b0;
742 
                    if (Debug) $display ("%m at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
743 
            end
744 
        end
745 
 
746 
        // Internal Precharge or Bst
747 
        if (Command[0] == `PRECH) begin                         // Precharge terminate a read with same bank or all banks
748 
            if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin
749 
                if (Data_out_enable == 1'b1) begin
750 
                    Data_out_enable = 1'b0;
751 
                end
752 
            end
753 
        end else if (Command[0] == `BST) begin                  // BST terminate a read to current bank
754 
            if (Data_out_enable == 1'b1) begin
755 
                Data_out_enable = 1'b0;
756 
            end
757 
        end
758 
 
759 
        if (Data_out_enable == 1'b0) begin
760 
            Dq_reg <= #tOH {data_bits{1'bz}};
761 
        end
762 
 
763 
        // Detect Read or Write command
764 
        if (Command[0] == `READ || Command[0] == `READ_A) begin
765 
            Bank = Bank_addr[0];
766 
            Col = Col_addr[0];
767 
            Col_brst = Col_addr[0];
768 
            if (Bank_addr[0] == 2'b00) begin
769 
                Row = B0_row_addr;
770 
            end else if (Bank_addr[0] == 2'b01) begin
771 
                Row = B1_row_addr;
772 
            end else if (Bank_addr[0] == 2'b10) begin
773 
                Row = B2_row_addr;
774 
            end else if (Bank_addr[0] == 2'b11) begin
775 
                Row = B3_row_addr;
776 
            end
777 
            Burst_counter = 0;
778 
            Data_in_enable = 1'b0;
779 
            Data_out_enable = 1'b1;
780 
        end else if (Command[0] == `WRITE || Command[0] == `WRITE_A) begin
781 
            Bank = Bank_addr[0];
782 
            Col = Col_addr[0];
783 
            Col_brst = Col_addr[0];
784 
            if (Bank_addr[0] == 2'b00) begin
785 
                Row = B0_row_addr;
786 
            end else if (Bank_addr[0] == 2'b01) begin
787 
                Row = B1_row_addr;
788 
            end else if (Bank_addr[0] == 2'b10) begin
789 
                Row = B2_row_addr;
790 
            end else if (Bank_addr[0] == 2'b11) begin
791 
                Row = B3_row_addr;
792 
            end
793 
            Burst_counter = 0;
794 
            Data_in_enable = 1'b1;
795 
            Data_out_enable = 1'b0;
796 
        end
797 
 
798 
        // DQ buffer (Driver/Receiver)
799 
        if (Data_in_enable == 1'b1) begin                                   // Writing Data to Memory
800 
            // Array buffer
801 
            if (Bank == 2'b00) Dq_dqm [31 : 0] = Bank0 [{Row, Col}];
802 
            if (Bank == 2'b01) Dq_dqm [31 : 0] = Bank1 [{Row, Col}];
803 
            if (Bank == 2'b10) Dq_dqm [31 : 0] = Bank2 [{Row, Col}];
804 
            if (Bank == 2'b11) Dq_dqm [31 : 0] = Bank3 [{Row, Col}];
805 
            // Dqm operation
806 
            if (Dqm[0] == 1'b0) Dq_dqm [ 7 :  0] = Dq [ 7 :  0];
807 
            if (Dqm[1] == 1'b0) Dq_dqm [15 :  8] = Dq [15 :  8];
808 
            if (Dqm[2] == 1'b0) Dq_dqm [23 : 16] = Dq [23 : 16];
809 
            if (Dqm[3] == 1'b0) Dq_dqm [31 : 24] = Dq [31 : 24];
810 
            // Write to memory
811 
            if (Bank == 2'b00) Bank0 [{Row, Col}] = Dq_dqm;
812 
            if (Bank == 2'b01) Bank1 [{Row, Col}] = Dq_dqm;
813 
            if (Bank == 2'b10) Bank2 [{Row, Col}] = Dq_dqm;
814 
            if (Bank == 2'b11) Bank3 [{Row, Col}] = Dq_dqm;
815 
            // Output result
816 
            if (Dqm == 4'b1111) begin
817 
                if (Debug) $display("%m at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
818 
            end else begin
819 
                if (Debug) $display("%m at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %x, Dqm = %b", $time, Bank, Row, Col, Dq_dqm, Dqm);
820 
                // Record tWR time and reset counter
821 
                WR_chkp [Bank] = $time;
822 
                WR_counter [Bank] = 0;
823 
            end
824 
            // Advance burst counter subroutine
825 
            #tHZ Burst;
826 
        end else if (Data_out_enable == 1'b1) begin                         // Reading Data from Memory
827 
            // Array Buffer
828 
            if (Bank == 2'b00) Dq_dqm = Bank0[{Row, Col}];
829 
            if (Bank == 2'b01) Dq_dqm = Bank1[{Row, Col}];
830 
            if (Bank == 2'b10) Dq_dqm = Bank2[{Row, Col}];
831 
            if (Bank == 2'b11) Dq_dqm = Bank3[{Row, Col}];
832 
            // Dqm operation
833 
            if (Dqm_reg0[0] == 1'b1) Dq_dqm [ 7 :  0] = 8'bz;
834 
            if (Dqm_reg0[1] == 1'b1) Dq_dqm [15 :  8] = 8'bz;
835 
            if (Dqm_reg0[2] == 1'b1) Dq_dqm [23 : 16] = 8'bz;
836 
            if (Dqm_reg0[3] == 1'b1) Dq_dqm [31 : 24] = 8'bz;
837 
            // Display Result
838 
            Dq_reg [31 : 0] = #tAC Dq_dqm [31 : 0];
839 
            if (Dqm_reg0 == 4'b1111) begin
840 
                if (Debug) $display("%m at time %t READ : Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
841 
            end else begin
842 
                if (Debug) $display("%m at time %t READ : Bank = %d Row = %d, Col = %d, Data = %x, Dqm = %b", $time, Bank, Row, Col, Dq_reg, Dqm_reg0);
843 
            end
844 
            // Advance burst counter subroutine
845 
            Burst;
846 
        end
847 
    end
848 
 
849 
    //  Write with Auto Precharge Calculation
850 
    //      The device start internal precharge:
851 
    //          1.  tWR Clock after last burst
852 
    //      and 2.  Meet minimum tRAS requirement
853 
    //       or 3.  Interrupt by a Read or Write (with or without AutoPrecharge)
854 
    always @ (RAS_clk) begin
855 
        if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin
856 
            if ((($time - RAS_chk0 >= tRAS) &&                                                          // Case 2
857 
               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1 && $time - Count_time[0] >= tWRa) ||   // Case 1
858 
                 (Burst_length_2 == 1'b1 && Count_precharge [0] >= 2 && $time - Count_time[0] >= tWRa) ||
859 
                 (Burst_length_4 == 1'b1 && Count_precharge [0] >= 4 && $time - Count_time[0] >= tWRa) ||
860 
                 (Burst_length_8 == 1'b1 && Count_precharge [0] >= 8 && $time - Count_time[0] >= tWRa))) ||
861 
                 (RW_interrupt_write[0] == 1'b1 && WR_counter[0] >= 1 && $time - WR_time[0] >= tWRa)) begin                           // Case 3 (stop count when interrupt)
862 
                    Auto_precharge[0] = 1'b0;
863 
                    Write_precharge[0] = 1'b0;
864 
                    RW_interrupt_write[0] = 1'b0;
865 
                    Pc_b0 = 1'b1;
866 
                    Act_b0 = 1'b0;
867 
                    RP_chk0 = $time;
868 
                    if (Debug) $display ("%m at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
869 
            end
870 
        end
871 
        if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin
872 
            if ((($time - RAS_chk1 >= tRAS) &&
873 
               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1 && $time - Count_time[1] >= tWRa) ||
874 
                 (Burst_length_2 == 1'b1 && Count_precharge [1] >= 2 && $time - Count_time[1] >= tWRa) ||
875 
                 (Burst_length_4 == 1'b1 && Count_precharge [1] >= 4 && $time - Count_time[1] >= tWRa) ||
876 
                 (Burst_length_8 == 1'b1 && Count_precharge [1] >= 8 && $time - Count_time[1] >= tWRa))) ||
877 
                 (RW_interrupt_write[1] == 1'b1 && WR_counter[1] >= 1 && $time - WR_time[1] >= tWRa)) begin
878 
                    Auto_precharge[1] = 1'b0;
879 
                    Write_precharge[1] = 1'b0;
880 
                    RW_interrupt_write[1] = 1'b0;
881 
                    Pc_b1 = 1'b1;
882 
                    Act_b1 = 1'b0;
883 
                    RP_chk1 = $time;
884 
                    if (Debug) $display ("%m at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
885 
            end
886 
        end
887 
        if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin
888 
            if ((($time - RAS_chk2 >= tRAS) &&
889 
               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1 && $time - Count_time[2] >= tWRa) ||
890 
                 (Burst_length_2 == 1'b1 && Count_precharge [2] >= 2 && $time - Count_time[2] >= tWRa) ||
891 
                 (Burst_length_4 == 1'b1 && Count_precharge [2] >= 4 && $time - Count_time[2] >= tWRa) ||
892 
                 (Burst_length_8 == 1'b1 && Count_precharge [2] >= 8 && $time - Count_time[2] >= tWRa))) ||
893 
                 (RW_interrupt_write[2] == 1'b1 && WR_counter[2] >= 1 && $time - WR_time[2] >= tWRa)) begin
894 
                    Auto_precharge[2] = 1'b0;
895 
                    Write_precharge[2] = 1'b0;
896 
                    RW_interrupt_write[2] = 1'b0;
897 
                    Pc_b2 = 1'b1;
898 
                    Act_b2 = 1'b0;
899 
                    RP_chk2 = $time;
900 
                    if (Debug) $display ("%m at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
901 
            end
902 
        end
903 
        if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin
904 
            if ((($time - RAS_chk3 >= tRAS) &&
905 
               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1 && $time - Count_time[3] >= tWRa) ||
906 
                 (Burst_length_2 == 1'b1 && Count_precharge [3] >= 2 && $time - Count_time[3] >= tWRa) ||
907 
                 (Burst_length_4 == 1'b1 && Count_precharge [3] >= 4 && $time - Count_time[3] >= tWRa) ||
908 
                 (Burst_length_8 == 1'b1 && Count_precharge [3] >= 8 && $time - Count_time[3] >= tWRa))) ||
909 
                 (RW_interrupt_write[3] == 1'b1 && WR_counter[3] >= 1 && $time - WR_time[3] >= tWRa)) begin
910 
                    Auto_precharge[3] = 1'b0;
911 
                    Write_precharge[3] = 1'b0;
912 
                    RW_interrupt_write[3] = 1'b0;
913 
                    Pc_b3 = 1'b1;
914 
                    Act_b3 = 1'b0;
915 
                    RP_chk3 = $time;
916 
                    if (Debug) $display ("%m at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
917 
            end
918 
        end
919 
    end
920 
 
921 
    task Burst;
922 
        begin
923 
            // Advance Burst Counter
924 
            Burst_counter = Burst_counter + 1;
925 
 
926 
            // Burst Type
927 
            if (Mode_reg[3] == 1'b0) begin                                  // Sequential Burst
928 
                Col_temp = Col + 1;
929 
            end else if (Mode_reg[3] == 1'b1) begin                         // Interleaved Burst
930 
                Col_temp[2] =  Burst_counter[2] ^  Col_brst[2];
931 
                Col_temp[1] =  Burst_counter[1] ^  Col_brst[1];
932 
                Col_temp[0] =  Burst_counter[0] ^  Col_brst[0];
933 
            end
934 
 
935 
            // Burst Length
936 
            if (Burst_length_2) begin                                       // Burst Length = 2
937 
                Col [0] = Col_temp [0];
938 
            end else if (Burst_length_4) begin                              // Burst Length = 4
939 
                Col [1 : 0] = Col_temp [1 : 0];
940 
            end else if (Burst_length_8) begin                              // Burst Length = 8
941 
                Col [2 : 0] = Col_temp [2 : 0];
942 
            end else begin                                                  // Burst Length = FULL
943 
                Col = Col_temp;
944 
            end
945 
 
946 
            // Burst Read Single Write
947 
            if (Write_burst_mode == 1'b1) begin
948 
                Data_in_enable = 1'b0;
949 
            end
950 
 
951 
            // Data Counter
952 
            if (Burst_length_1 == 1'b1) begin
953 
                if (Burst_counter >= 1) begin
954 
                    Data_in_enable = 1'b0;
955 
                    Data_out_enable = 1'b0;
956 
                end
957 
            end else if (Burst_length_2 == 1'b1) begin
958 
                if (Burst_counter >= 2) begin
959 
                    Data_in_enable = 1'b0;
960 
                    Data_out_enable = 1'b0;
961 
                end
962 
            end else if (Burst_length_4 == 1'b1) begin
963 
                if (Burst_counter >= 4) begin
964 
                    Data_in_enable = 1'b0;
965 
                    Data_out_enable = 1'b0;
966 
                end
967 
            end else if (Burst_length_8 == 1'b1) begin
968 
                if (Burst_counter >= 8) begin
969 
                    Data_in_enable = 1'b0;
970 
                    Data_out_enable = 1'b0;
971 
                end
972 
            end
973 
        end
974 
    endtask
975 
 
976 
    // Timing Parameters for -7 and CAS Latency = 3
977 
    specify
978 
        specparam
979 
            tAH  =  1.00,                                       // Addr, Ba Hold Time
980 
            tAS  =  2.00,                                       // Addr, Ba Setup Time
981 
            tCH  =  2.75,                                       // Clock High-Level Width
982 
            tCL  =  2.75,                                       // Clock Low-Level Width
983 
            tCK  =  7.00,                                       // Clock Cycle Time
984 
            tDH  =  1.00,                                       // Data-in Hold Time
985 
            tDS  =  2.00,                                       // Data-in Setup Time
986 
            tCKH =  1.00,                                       // CKE Hold  Time
987 
            tCKS =  2.00,                                       // CKE Setup Time
988 
            tCMH =  1.00,                                       // CS#, RAS#, CAS#, WE#, DQM# Hold  Time
989 
            tCMS =  2.00;                                       // CS#, RAS#, CAS#, WE#, DQM# Setup Time
990 
        $width    (posedge Clk,           tCH);
991 
        $width    (negedge Clk,           tCL);
992 
        $period   (negedge Clk,           tCK);
993 
        $period   (posedge Clk,           tCK);
994 
        $setuphold(posedge Clk,    Cke,   tCKS, tCKH);
995 
        $setuphold(posedge Clk,    Cs_n,  tCMS, tCMH);
996 
        $setuphold(posedge Clk,    Cas_n, tCMS, tCMH);
997 
        $setuphold(posedge Clk,    Ras_n, tCMS, tCMH);
998 
        $setuphold(posedge Clk,    We_n,  tCMS, tCMH);
999 
        $setuphold(posedge Clk,    Addr,  tAS,  tAH);
1000 
        $setuphold(posedge Clk,    Ba,    tAS,  tAH);
1001 
        $setuphold(posedge Clk,    Dqm,   tCMS, tCMH);
1002 
        $setuphold(posedge Dq_chk, Dq,    tDS,  tDH);
1003 
    endspecify
1004 
 
1005 
endmodule
1006 
 

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