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[/] [mem_ctrl/] [trunk/] [bench/] [verilog/] [sdram_models/] [8Mx8/] [mt48lc8m8a2.v] - Blame information for rev 28

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1 4 rudi
/****************************************************************************************
2
*
3
*    File Name:  MT48LC8M8A2.V
4
*      Version:  0.0g
5
*         Date:  January 5th, 2000
6
*        Model:  BUS Functional
7
*    Simulator:  Model Technology (PC version 5.3)
8
*
9
* Dependencies:  None
10
*
11
*       Author:  Son P. Huynh
12
*        Email:  sphuynh@micron.com
13
*        Phone:  (208) 368-3825
14
*      Company:  Micron Technology, Inc.
15
*        Model:  MT48LC8M8A2 (2Meg x 8 x 4 Banks)
16
*
17
*  Description:  Micron 64Mb SDRAM Verilog model
18
*
19
*   Limitation:  - Doesn't check for 4096 cycle refresh
20
*
21
*         Note:  - Set simulator resolution to "ps" accuracy
22
*                - Set Debug = 0 to disable $display messages
23
*
24
*   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
25
*                WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
26
*                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
27
*                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
28
*
29
*                Copyright © 1998 Micron Semiconductor Products, Inc.
30
*                All rights researved
31
*
32
* Rev   Author          Phone         Date        Changes
33
* ----  ----------------------------  ----------  ---------------------------------------
34
* 0.0g  Son Huynh       208-368-3825  01/05/2000  - Change tRAS + tWR timing check
35
*       Micron Technology Inc.                    - Change some error messages
36
*
37
* 0.0f  Son Huynh       208-368-3825  07/08/1999  - Fix tWR = 1 Clk + 7.5 ns (Auto)
38
*       Micron Technology Inc.                    - Fix tWR = 15 ns (Manual)
39
*                                                 - Fix tRP (Autoprecharge to AutoRefresh)
40
*
41
* 0.0e  Son Huynh       208-368-3825  12/17/1998  - Fix new problem in 0.0d
42
*       Micron Technology Inc.
43
*
44
* 0.0d  Son Huynh       208-368-3825  12/11/1998  - Fix tWR check for WRITE
45
*       Micron Technology Inc.                    - Fix Precharge pipeline for R/W
46
*                                                 - Fix R/W with Concurrent Auto Precharge
47
*
48
* 0.0c  Son Huynh       208-368-3825  09/28/1998  - Fix DQM problem
49
*       Micron Technology Inc.                    - Fix Interleave Burst Mode
50
*
51
* 0.0b  Son Huynh       208-368-3825  05/19/1998  - Improve model functionalities
52
*       Micron Technology Inc.                    - Add more timing check
53
*
54
* 0.0a  Son Huynh       208-368-3825  05/13/1998  - First Release
55
*       Micron Technology Inc.                    - Simple testbench included
56
****************************************************************************************/
57
 
58
`timescale 1ns / 100ps
59
 
60
module mt48lc8m8a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
61
 
62
    parameter addr_bits =      12;
63
    parameter data_bits =       8;
64
    parameter col_bits  =       9;
65
    parameter mem_sizes = 2097151;
66
 
67
    inout     [data_bits - 1 : 0] Dq;
68
    input     [addr_bits - 1 : 0] Addr;
69
    input                 [1 : 0] Ba;
70
    input                         Clk;
71
    input                         Cke;
72
    input                         Cs_n;
73
    input                         Ras_n;
74
    input                         Cas_n;
75
    input                         We_n;
76
    input                         Dqm;
77
 
78
    reg       [data_bits - 1 : 0] Bank0 [0 : mem_sizes];
79
    reg       [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
80
    reg       [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
81
    reg       [data_bits - 1 : 0] Bank3 [0 : mem_sizes];
82
 
83
    reg                   [1 : 0] Bank_addr [0 : 3];                // Bank Address Pipeline
84
    reg        [col_bits - 1 : 0] Col_addr [0 : 3];                 // Column Address Pipeline
85
    reg                   [3 : 0] Command [0 : 3];                  // Command Operation Pipeline
86
    reg                           Dqm_reg0, Dqm_reg1;               // DQM Operation Pipeline
87
    reg       [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
88
 
89
    reg       [addr_bits - 1 : 0] Mode_reg;
90
    reg       [data_bits - 1 : 0] Dq_reg, Dq_dqm;
91
    reg        [col_bits - 1 : 0] Col_temp, Burst_counter;
92
 
93
    reg                           Act_b0, Act_b1, Act_b2, Act_b3;   // Bank Activate
94
    reg                           Pc_b0, Pc_b1, Pc_b2, Pc_b3;       // Bank Precharge
95
 
96
    reg                   [1 : 0] Bank_precharge     [0 : 3];       // Precharge Command
97
    reg                           A10_precharge      [0 : 3];       // Addr[10] = 1 (All banks)
98
    reg                           Auto_precharge     [0 : 3];       // RW AutoPrecharge (Bank)
99
    reg                           Read_precharge     [0 : 3];       // R  AutoPrecharge
100
    reg                           Write_precharge    [0 : 3];       //  W AutoPrecharge
101
    reg                           RW_interrupt_read  [0 : 3];       // RW Interrupt Read with Auto Precharge
102
    reg                           RW_interrupt_write [0 : 3];       // RW Interrupt Write with Auto Precharge
103
    reg                   [1 : 0] RW_interrupt_bank;                // RW interrupt Bank
104
    time                          Count_time         [0 : 3];       // RW AutoPrecharge (time after tWR = 1)
105
    integer                       Count_precharge    [0 : 3];       // RW AutoPrecharge (Counter)
106
 
107
    reg                           Data_in_enable;
108
    reg                           Data_out_enable;
109
 
110
    reg                   [1 : 0] Bank, Previous_bank;
111
    reg       [addr_bits - 1 : 0] Row;
112
    reg        [col_bits - 1 : 0] Col, Col_brst;
113
 
114
    // Internal system clock
115
    reg                           CkeZ, Sys_clk, RAS_clk;
116
 
117
    // Commands Decode
118
    wire      Active_enable    = ~Cs_n & ~Ras_n &  Cas_n &  We_n;
119
    wire      Aref_enable      = ~Cs_n & ~Ras_n & ~Cas_n &  We_n;
120
    wire      Burst_term       = ~Cs_n &  Ras_n &  Cas_n & ~We_n;
121
    wire      Mode_reg_enable  = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n;
122
    wire      Prech_enable     = ~Cs_n & ~Ras_n &  Cas_n & ~We_n;
123
    wire      Read_enable      = ~Cs_n &  Ras_n & ~Cas_n &  We_n;
124
    wire      Write_enable     = ~Cs_n &  Ras_n & ~Cas_n & ~We_n;
125
 
126
    // Burst Length Decode
127
    wire      Burst_length_1   = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0];
128
    wire      Burst_length_2   = ~Mode_reg[2] & ~Mode_reg[1] &  Mode_reg[0];
129
    wire      Burst_length_4   = ~Mode_reg[2] &  Mode_reg[1] & ~Mode_reg[0];
130
    wire      Burst_length_8   = ~Mode_reg[2] &  Mode_reg[1] &  Mode_reg[0];
131
 
132
    // CAS Latency Decode
133
    wire      Cas_latency_2    = ~Mode_reg[6] &  Mode_reg[5] & ~Mode_reg[4];
134
    wire      Cas_latency_3    = ~Mode_reg[6] &  Mode_reg[5] &  Mode_reg[4];
135
 
136
    // Write Burst Mode
137
    wire      Write_burst_mode = Mode_reg[9];
138
 
139
    wire      Debug            = 1'b0;                          // Debug messages : 1 = On
140
    wire      Dq_chk           = Sys_clk & Data_in_enable;      // Check setup/hold time for DQ
141
 
142
    assign    Dq               = Dq_reg;                        // DQ buffer
143
 
144
    // Commands Operation
145
    `define   ACT       0
146
    `define   NOP       1
147
    `define   READ      2
148
    `define   READ_A    3
149
    `define   WRITE     4
150
    `define   WRITE_A   5
151
    `define   PRECH     6
152
    `define   A_REF     7
153
    `define   BST       8
154
    `define   LMR       9
155
 
156
    // Timing Parameters for -7E and CAS Latency = 2
157
    parameter tAC  =   5.4;
158
    parameter tHZ  =   5.4;
159
    parameter tOH  =   2.7;
160
    parameter tMRD =   2.0;     // 2 Clk Cycles
161
    parameter tRAS =  37.0;
162
    parameter tRC  =  60.0;
163
    parameter tRCD =  15.0;
164
    parameter tRP  =  15.0;
165
    parameter tRRD =  14.0;
166
    parameter tWRa =   7.0;     // A2 Version - Auto precharge mode (1 Clk + 7 ns)
167
    parameter tWRp =  14.0;     // A2 Version - Manual precharge mode (14 ns)
168
 
169
    // Timing Check variable
170
    integer   MRD_chk;
171
    integer   WR_counter [0 : 3];
172
    time      WR_time [0 : 3];
173
    time      WR_chkp [0 : 3];
174
    time      RC_chk, RRD_chk;
175
    time      RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
176
    time      RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
177
    time      RP_chk0, RP_chk1, RP_chk2, RP_chk3;
178
 
179
    initial begin
180
        Dq_reg = {data_bits{1'bz}};
181
        {Data_in_enable, Data_out_enable} = 0;
182
        {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000;
183
        {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000;
184
        {WR_chkp[0], WR_chkp[1], WR_chkp[2], WR_chkp[3]} = 0;
185
        {WR_counter[0], WR_counter[1], WR_counter[2], WR_counter[3]} = 0;
186
        {WR_time[0], WR_time[1], WR_time[2], WR_time[3]} = 0;
187
        {RW_interrupt_read[0], RW_interrupt_read[1], RW_interrupt_read[2], RW_interrupt_read[3]} = 0;
188
        {RW_interrupt_write[0], RW_interrupt_write[1], RW_interrupt_write[2], RW_interrupt_write[3]} = 0;
189
        {MRD_chk, RC_chk, RRD_chk} = 0;
190
        {RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3} = 0;
191
        {RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3} = 0;
192
        {RP_chk0, RP_chk1, RP_chk2, RP_chk3} = 0;
193
        $timeformat (-9, 1, " ns", 12);
194
        //$readmemh("bank0.txt", Bank0);
195
        //$readmemh("bank1.txt", Bank1);
196
        //$readmemh("bank2.txt", Bank2);
197
        //$readmemh("bank3.txt", Bank3);
198
        RAS_clk = 1'b0;
199
    end
200
 
201
 
202
 
203
 
204
integer n;
205
 
206
task mem_fill;
207
input   size;
208
 
209
integer         size;
210
 
211
begin
212
        for(n=0;n<size;n=n+1)
213
           begin
214
                Bank0[n] = $random;
215
                Bank1[n] = $random;
216
                Bank2[n] = $random;
217
                Bank3[n] = $random;
218
           end
219
 
220
end
221
endtask
222
 
223
 
224
 
225
 
226
    // RAS Clk for checking tWR
227
    always RAS_clk = #0.5 ~RAS_clk;
228
 
229
    // System clock generator
230
    always begin
231
        @ (posedge Clk) begin
232
            Sys_clk = CkeZ;
233
            CkeZ = Cke;
234
        end
235
        @ (negedge Clk) begin
236
            Sys_clk = 1'b0;
237
        end
238
    end
239
 
240
    always @ (posedge Sys_clk) begin
241
        // Internal Commamd Pipelined
242
        Command[0] = Command[1];
243
        Command[1] = Command[2];
244
        Command[2] = Command[3];
245
        Command[3] = `NOP;
246
 
247
        Col_addr[0] = Col_addr[1];
248
        Col_addr[1] = Col_addr[2];
249
        Col_addr[2] = Col_addr[3];
250
        Col_addr[3] = {col_bits{1'b0}};
251
 
252
        Bank_addr[0] = Bank_addr[1];
253
        Bank_addr[1] = Bank_addr[2];
254
        Bank_addr[2] = Bank_addr[3];
255
        Bank_addr[3] = 2'b0;
256
 
257
        Bank_precharge[0] = Bank_precharge[1];
258
        Bank_precharge[1] = Bank_precharge[2];
259
        Bank_precharge[2] = Bank_precharge[3];
260
        Bank_precharge[3] = 2'b0;
261
 
262
        A10_precharge[0] = A10_precharge[1];
263
        A10_precharge[1] = A10_precharge[2];
264
        A10_precharge[2] = A10_precharge[3];
265
        A10_precharge[3] = 1'b0;
266
 
267
        // Dqm pipeline for Read
268
        Dqm_reg0 = Dqm_reg1;
269
        Dqm_reg1 = Dqm;
270
 
271
        // Read or Write with Auto Precharge Counter
272
        if (Auto_precharge[0] == 1'b1) begin
273
            Count_precharge[0] = Count_precharge[0] + 1;
274
        end
275
        if (Auto_precharge[1] == 1'b1) begin
276
            Count_precharge[1] = Count_precharge[1] + 1;
277
        end
278
        if (Auto_precharge[2] == 1'b1) begin
279
            Count_precharge[2] = Count_precharge[2] + 1;
280
        end
281
        if (Auto_precharge[3] == 1'b1) begin
282
            Count_precharge[3] = Count_precharge[3] + 1;
283
        end
284
 
285
        // Auto Precharge Timer for tWR
286
        if (Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) begin
287
            if (Count_precharge[0] == 1) begin
288
                Count_time[0] = $time;
289
            end
290
            if (Count_precharge[1] == 1) begin
291
                Count_time[1] = $time;
292
            end
293
            if (Count_precharge[2] == 1) begin
294
                Count_time[2] = $time;
295
            end
296
            if (Count_precharge[3] == 1) begin
297
                Count_time[3] = $time;
298
            end
299
        end else if (Burst_length_2 == 1'b1) begin
300
            if (Count_precharge[0] == 2) begin
301
                Count_time[0] = $time;
302
            end
303
            if (Count_precharge[1] == 2) begin
304
                Count_time[1] = $time;
305
            end
306
            if (Count_precharge[2] == 2) begin
307
                Count_time[2] = $time;
308
            end
309
            if (Count_precharge[3] == 2) begin
310
                Count_time[3] = $time;
311
            end
312
        end else if (Burst_length_4 == 1'b1) begin
313
            if (Count_precharge[0] == 4) begin
314
                Count_time[0] = $time;
315
            end
316
            if (Count_precharge[1] == 4) begin
317
                Count_time[1] = $time;
318
            end
319
            if (Count_precharge[2] == 4) begin
320
                Count_time[2] = $time;
321
            end
322
            if (Count_precharge[3] == 4) begin
323
                Count_time[3] = $time;
324
            end
325
        end else if (Burst_length_8 == 1'b1) begin
326
            if (Count_precharge[0] == 8) begin
327
                Count_time[0] = $time;
328
            end
329
            if (Count_precharge[1] == 8) begin
330
                Count_time[1] = $time;
331
            end
332
            if (Count_precharge[2] == 8) begin
333
                Count_time[2] = $time;
334
            end
335
            if (Count_precharge[3] == 8) begin
336
                Count_time[3] = $time;
337
            end
338
        end
339
 
340
        // tMRD Counter
341
        MRD_chk = MRD_chk + 1;
342
 
343
        // tWR Counter for Write
344
        WR_counter[0] = WR_counter[0] + 1;
345
        WR_counter[1] = WR_counter[1] + 1;
346
        WR_counter[2] = WR_counter[2] + 1;
347
        WR_counter[3] = WR_counter[3] + 1;
348
 
349
        // Auto Refresh
350
        if (Aref_enable == 1'b1) begin
351
            if (Debug) $display ("at time %t AREF : Auto Refresh", $time);
352
            // Auto Refresh to Auto Refresh
353
            if ($time - RC_chk < tRC) begin
354
                $display ("at time %t ERROR: tRC violation during Auto Refresh", $time);
355
            end
356
 
357
            // Precharge to Auto Refresh
358
            if ($time - RP_chk0 < tRP || $time - RP_chk1 < tRP || $time - RP_chk2 < tRP || $time - RP_chk3 < tRP) begin
359
                $display ("at time %t ERROR: tRP violation during Auto Refresh", $time);
360
            end
361
 
362
            // Precharge to Refresh
363
            if (Pc_b0 == 1'b0 || Pc_b1 == 1'b0 || Pc_b2 == 1'b0 || Pc_b3 == 1'b0) begin
364
                $display ("at time %t ERROR: All banks must be Precharge before Auto Refresh", $time);
365
            end
366
 
367
            // Record Current tRC time
368
            RC_chk = $time;
369
        end
370
 
371
        // Load Mode Register
372
        if (Mode_reg_enable == 1'b1) begin
373
            // Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode
374
            if (Pc_b0 == 1'b1 && Pc_b1 == 1'b1 && Pc_b2 == 1'b1 && Pc_b3 == 1'b1) begin
375
                Mode_reg = Addr;
376
                if (Debug) begin
377
                    $display ("at time %t LMR  : Load Mode Register", $time);
378
                    // CAS Latency
379
                    if (Addr[6 : 4] == 3'b010)
380
                        $display ("                            CAS Latency      = 2");
381
                    else if (Addr[6 : 4] == 3'b011)
382
                        $display ("                            CAS Latency      = 3");
383
                    else
384
                        $display ("                            CAS Latency      = Reserved");
385
                    // Burst Length
386
                    if (Addr[2 : 0] == 3'b000)
387
                        $display ("                            Burst Length     = 1");
388
                    else if (Addr[2 : 0] == 3'b001)
389
                        $display ("                            Burst Length     = 2");
390
                    else if (Addr[2 : 0] == 3'b010)
391
                        $display ("                            Burst Length     = 4");
392
                    else if (Addr[2 : 0] == 3'b011)
393
                        $display ("                            Burst Length     = 8");
394
                    else if (Addr[3 : 0] == 4'b0111)
395
                        $display ("                            Burst Length     = Full");
396
                    else
397
                        $display ("                            Burst Length     = Reserved");
398
                    // Burst Type
399
                    if (Addr[3] == 1'b0)
400
                        $display ("                            Burst Type       = Sequential");
401
                    else if (Addr[3] == 1'b1)
402
                        $display ("                            Burst Type       = Interleaved");
403
                    else
404
                        $display ("                            Burst Type       = Reserved");
405
                    // Write Burst Mode
406
                    if (Addr[9] == 1'b0)
407
                        $display ("                            Write Burst Mode = Programmed Burst Length");
408
                    else if (Addr[9] == 1'b1)
409
                        $display ("                            Write Burst Mode = Single Location Access");
410
                    else
411
                        $display ("                            Write Burst Mode = Reserved");
412
                end
413
            end else begin
414
                $display ("at time %t ERROR: all banks must be Precharge before Load Mode Register", $time);
415
            end
416
            // REF to LMR
417
            if ($time - RC_chk < tRC) begin
418
                $display ("at time %t ERROR: tRC violation during Load Mode Register", $time);
419
            end
420
            // LMR to LMR
421
            if (MRD_chk < tMRD) begin
422
                $display ("at time %t ERROR: tMRD violation during Load Mode Register", $time);
423
            end
424
            MRD_chk = 0;
425
        end
426
 
427
        // Active Block (Latch Bank Address and Row Address)
428
        if (Active_enable == 1'b1) begin
429
            if (Ba == 2'b00 && Pc_b0 == 1'b1) begin
430
                {Act_b0, Pc_b0} = 2'b10;
431
                B0_row_addr = Addr [addr_bits - 1 : 0];
432
                RCD_chk0 = $time;
433
                RAS_chk0 = $time;
434
                if (Debug) $display ("at time %t ACT  : Bank = 0 Row = %d",$time, Addr);
435
                // Precharge to Activate Bank 0
436
                if ($time - RP_chk0 < tRP) begin
437
                    $display ("at time %t ERROR: tRP violation during Activate bank 0", $time);
438
                end
439
            end else if (Ba == 2'b01 && Pc_b1 == 1'b1) begin
440
                {Act_b1, Pc_b1} = 2'b10;
441
                B1_row_addr = Addr [addr_bits - 1 : 0];
442
                RCD_chk1 = $time;
443
                RAS_chk1 = $time;
444
                if (Debug) $display ("at time %t ACT  : Bank = 1 Row = %d",$time, Addr);
445
                // Precharge to Activate Bank 1
446
                if ($time - RP_chk1 < tRP) begin
447
                    $display ("at time %t ERROR: tRP violation during Activate bank 1", $time);
448
                end
449
            end else if (Ba == 2'b10 && Pc_b2 == 1'b1) begin
450
                {Act_b2, Pc_b2} = 2'b10;
451
                B2_row_addr = Addr [addr_bits - 1 : 0];
452
                RCD_chk2 = $time;
453
                RAS_chk2 = $time;
454
                if (Debug) $display ("at time %t ACT  : Bank = 2 Row = %d",$time, Addr);
455
                // Precharge to Activate Bank 2
456
                if ($time - RP_chk2 < tRP) begin
457
                    $display ("at time %t ERROR: tRP violation during Activate bank 2", $time);
458
                end
459
            end else if (Ba == 2'b11 && Pc_b3 == 1'b1) begin
460
                {Act_b3, Pc_b3} = 2'b10;
461
                B3_row_addr = Addr [addr_bits - 1 : 0];
462
                RCD_chk3 = $time;
463
                RAS_chk3 = $time;
464
                if (Debug) $display ("at time %t ACT  : Bank = 3 Row = %d",$time, Addr);
465
                // Precharge to Activate Bank 3
466
                if ($time - RP_chk3 < tRP) begin
467
                    $display ("at time %t ERROR: tRP violation during Activate bank 3", $time);
468
                end
469
            end else if (Ba == 2'b00 && Pc_b0 == 1'b0) begin
470
                $display ("at time %t ERROR: Bank 0 is already Activated (not Precharged)", $time);
471
            end else if (Ba == 2'b01 && Pc_b1 == 1'b0) begin
472
                $display ("at time %t ERROR: Bank 1 is already Activated (not Precharged)", $time);
473
            end else if (Ba == 2'b10 && Pc_b2 == 1'b0) begin
474
                $display ("at time %t ERROR: Bank 2 is already Activated (not Precharged)", $time);
475
            end else if (Ba == 2'b11 && Pc_b3 == 1'b0) begin
476
                $display ("at time %t ERROR: Bank 3 is already Activated (not Precharged)", $time);
477
            end
478
 
479
            // Active Bank A to Active Bank B
480
            if ((Previous_bank != Ba) && ($time - RRD_chk < tRRD)) begin
481
                $display ("at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba);
482
            end
483
 
484
            // Load Mode Register to Active
485
            if (MRD_chk < tMRD ) begin
486
                $display ("at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba);
487
            end
488
 
489
            // Auto Refresh to Activate
490
            if ($time - RC_chk < tRC) begin
491
                $display ("at time %t ERROR: tRC violation during Activate bank = %d", $time, Ba);
492
            end
493
 
494
            // Record variables for checking violation
495
            RRD_chk = $time;
496
            Previous_bank = Ba;
497
        end
498
 
499
        // Precharge Block
500
        if (Prech_enable == 1'b1) begin
501
            if (Addr[10] == 1'b1) begin
502
                {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b1111;
503
                {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000;
504
                RP_chk0 = $time;
505
                RP_chk1 = $time;
506
                RP_chk2 = $time;
507
                RP_chk3 = $time;
508
                if (Debug) $display ("at time %t PRE  : Bank = ALL",$time);
509
                // Activate to Precharge all banks
510
                if (($time - RAS_chk0 < tRAS) || ($time - RAS_chk1 < tRAS) ||
511
                    ($time - RAS_chk2 < tRAS) || ($time - RAS_chk3 < tRAS)) begin
512
                    $display ("at time %t ERROR: tRAS violation during Precharge all bank", $time);
513
                end
514
                // tWR violation check for write
515
                if (($time - WR_chkp[0] < tWRp) || ($time - WR_chkp[1] < tWRp) ||
516
                    ($time - WR_chkp[2] < tWRp) || ($time - WR_chkp[3] < tWRp)) begin
517
                    $display ("at time %t ERROR: tWR violation during Precharge all bank", $time);
518
                end
519
            end else if (Addr[10] == 1'b0) begin
520
                if (Ba == 2'b00) begin
521
                    {Pc_b0, Act_b0} = 2'b10;
522
                    RP_chk0 = $time;
523
                    if (Debug) $display ("at time %t PRE  : Bank = 0",$time);
524
                    // Activate to Precharge Bank 0
525
                    if ($time - RAS_chk0 < tRAS) begin
526
                        $display ("at time %t ERROR: tRAS violation during Precharge bank 0", $time);
527
                    end
528
                end else if (Ba == 2'b01) begin
529
                    {Pc_b1, Act_b1} = 2'b10;
530
                    RP_chk1 = $time;
531
                    if (Debug) $display ("at time %t PRE  : Bank = 1",$time);
532
                    // Activate to Precharge Bank 1
533
                    if ($time - RAS_chk1 < tRAS) begin
534
                        $display ("at time %t ERROR: tRAS violation during Precharge bank 1", $time);
535
                    end
536
                end else if (Ba == 2'b10) begin
537
                    {Pc_b2, Act_b2} = 2'b10;
538
                    RP_chk2 = $time;
539
                    if (Debug) $display ("at time %t PRE  : Bank = 2",$time);
540
                    // Activate to Precharge Bank 2
541
                    if ($time - RAS_chk2 < tRAS) begin
542
                        $display ("at time %t ERROR: tRAS violation during Precharge bank 2", $time);
543
                    end
544
                end else if (Ba == 2'b11) begin
545
                    {Pc_b3, Act_b3} = 2'b10;
546
                    RP_chk3 = $time;
547
                    if (Debug) $display ("at time %t PRE  : Bank = 3",$time);
548
                    // Activate to Precharge Bank 3
549
                    if ($time - RAS_chk3 < tRAS) begin
550
                        $display ("at time %t ERROR: tRAS violation during Precharge bank 3", $time);
551
                    end
552
                end
553
                // tWR violation check for write
554
                if ($time - WR_chkp[Ba] < tWRp) begin
555
                    $display ("at time %t ERROR: tWR violation during Precharge bank %d", $time, Ba);
556
                end
557
            end
558
            // Terminate a Write Immediately (if same bank or all banks)
559
            if (Data_in_enable == 1'b1 && (Bank == Ba || Addr[10] == 1'b1)) begin
560
                Data_in_enable = 1'b0;
561
            end
562
            // Precharge Command Pipeline for Read
563
            if (Cas_latency_3 == 1'b1) begin
564
                Command[2] = `PRECH;
565
                Bank_precharge[2] = Ba;
566
                A10_precharge[2] = Addr[10];
567
            end else if (Cas_latency_2 == 1'b1) begin
568
                Command[1] = `PRECH;
569
                Bank_precharge[1] = Ba;
570
                A10_precharge[1] = Addr[10];
571
            end
572
        end
573
 
574
        // Burst terminate
575
        if (Burst_term == 1'b1) begin
576
            // Terminate a Write Immediately
577
            if (Data_in_enable == 1'b1) begin
578
                Data_in_enable = 1'b0;
579
            end
580
            // Terminate a Read Depend on CAS Latency
581
            if (Cas_latency_3 == 1'b1) begin
582
                Command[2] = `BST;
583
            end else if (Cas_latency_2 == 1'b1) begin
584
                Command[1] = `BST;
585
            end
586
            if (Debug) $display ("at time %t BST  : Burst Terminate",$time);
587
        end
588
 
589
        // Read, Write, Column Latch
590
        if (Read_enable == 1'b1 || Write_enable == 1'b1) begin
591
            // Check to see if bank is open (ACT)
592
            if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) ||
593
                (Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin
594
                $display("at time %t ERROR: Cannot Read or Write - Bank %d is not Activated", $time, Ba);
595
            end
596
 
597
            // Activate to Read or Write
598
            if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD))
599
                $display("at time %t ERROR: tRCD violation during Read or Write to Bank 0", $time);
600
            if ((Ba == 2'b01) && ($time - RCD_chk1 < tRCD))
601
                $display("at time %t ERROR: tRCD violation during Read or Write to Bank 1", $time);
602
            if ((Ba == 2'b10) && ($time - RCD_chk2 < tRCD))
603
                $display("at time %t ERROR: tRCD violation during Read or Write to Bank 2", $time);
604
            if ((Ba == 2'b11) && ($time - RCD_chk3 < tRCD))
605
                $display("at time %t ERROR: tRCD violation during Read or Write to Bank 3", $time);
606
 
607
            // Read Command
608
            if (Read_enable == 1'b1) begin
609
                // CAS Latency pipeline
610
                if (Cas_latency_3 == 1'b1) begin
611
                    if (Addr[10] == 1'b1) begin
612
                        Command[2] = `READ_A;
613
                    end else begin
614
                        Command[2] = `READ;
615
                    end
616
                    Col_addr[2] = Addr;
617
                    Bank_addr[2] = Ba;
618
                end else if (Cas_latency_2 == 1'b1) begin
619
                    if (Addr[10] == 1'b1) begin
620
                        Command[1] = `READ_A;
621
                    end else begin
622
                        Command[1] = `READ;
623
                    end
624
                    Col_addr[1] = Addr;
625
                    Bank_addr[1] = Ba;
626
                end
627
 
628
                // Read interrupt Write (terminate Write immediately)
629
                if (Data_in_enable == 1'b1) begin
630
                    Data_in_enable = 1'b0;
631
                end
632
 
633
            // Write Command
634
            end else if (Write_enable == 1'b1) begin
635
                if (Addr[10] == 1'b1) begin
636
                    Command[0] = `WRITE_A;
637
                end else begin
638
                    Command[0] = `WRITE;
639
                end
640
                Col_addr[0] = Addr;
641
                Bank_addr[0] = Ba;
642
 
643
                // Write interrupt Write (terminate Write immediately)
644
                if (Data_in_enable == 1'b1) begin
645
                    Data_in_enable = 1'b0;
646
                end
647
 
648
                // Write interrupt Read (terminate Read immediately)
649
                if (Data_out_enable == 1'b1) begin
650
                    Data_out_enable = 1'b0;
651
                end
652
            end
653
 
654
            // Interrupting a Write with Autoprecharge
655
            if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
656
                RW_interrupt_write[RW_interrupt_bank] = 1'b1;
657
                WR_time[RW_interrupt_bank] = $time;
658
                if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Write Bank %d with Autoprecharge", $time, Ba, RW_interrupt_bank);
659
            end
660
 
661
            // Interrupting a Read with Autoprecharge
662
            if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Read_precharge[RW_interrupt_bank] == 1'b1) begin
663
                RW_interrupt_read[RW_interrupt_bank] = 1'b1;
664
                if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Read Bank %d with Autoprecharge", $time, Ba, RW_interrupt_bank);
665
            end
666
 
667
            // Read or Write with Auto Precharge
668
            if (Addr[10] == 1'b1) begin
669
                Auto_precharge[Ba] = 1'b1;
670
                Count_precharge[Ba] = 0;
671
                RW_interrupt_bank = Ba;
672
                if (Read_enable == 1'b1) begin
673
                    Read_precharge[Ba] = 1'b1;
674
                end else if (Write_enable == 1'b1) begin
675
                    Write_precharge[Ba] = 1'b1;
676
                end
677
            end
678
        end
679
 
680
        //  Read with Auto Precharge Calculation
681
        //      The device start internal precharge:
682
        //          1.  CAS Latency - 1 cycles before last burst
683
        //      and 2.  Meet minimum tRAS requirement
684
        //       or 3.  Interrupt by a Read or Write (with or without AutoPrecharge)
685
        if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin
686
            if ((($time - RAS_chk0 >= tRAS) &&                                                      // Case 2
687
                ((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) ||                             // Case 1
688
                 (Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) ||
689
                 (Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) ||
690
                 (Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) ||
691
                 (RW_interrupt_read[0] == 1'b1)) begin                                              // Case 3
692
                    Pc_b0 = 1'b1;
693
                    Act_b0 = 1'b0;
694
                    RP_chk0 = $time;
695
                    Auto_precharge[0] = 1'b0;
696
                    Read_precharge[0] = 1'b0;
697
                    RW_interrupt_read[0] = 1'b0;
698
                    if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
699
            end
700
        end
701
        if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin
702
            if ((($time - RAS_chk1 >= tRAS) &&
703
                ((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) ||
704
                 (Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) ||
705
                 (Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) ||
706
                 (Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) ||
707
                 (RW_interrupt_read[1] == 1'b1)) begin
708
                    Pc_b1 = 1'b1;
709
                    Act_b1 = 1'b0;
710
                    RP_chk1 = $time;
711
                    Auto_precharge[1] = 1'b0;
712
                    Read_precharge[1] = 1'b0;
713
                    RW_interrupt_read[1] = 1'b0;
714
                    if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
715
            end
716
        end
717
        if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin
718
            if ((($time - RAS_chk2 >= tRAS) &&
719
                ((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) ||
720
                 (Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) ||
721
                 (Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) ||
722
                 (Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) ||
723
                 (RW_interrupt_read[2] == 1'b1)) begin
724
                    Pc_b2 = 1'b1;
725
                    Act_b2 = 1'b0;
726
                    RP_chk2 = $time;
727
                    Auto_precharge[2] = 1'b0;
728
                    Read_precharge[2] = 1'b0;
729
                    RW_interrupt_read[2] = 1'b0;
730
                    if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
731
            end
732
        end
733
        if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin
734
            if ((($time - RAS_chk3 >= tRAS) &&
735
                ((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) ||
736
                 (Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) ||
737
                 (Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) ||
738
                 (Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) ||
739
                 (RW_interrupt_read[3] == 1'b1)) begin
740
                    Pc_b3 = 1'b1;
741
                    Act_b3 = 1'b0;
742
                    RP_chk3 = $time;
743
                    Auto_precharge[3] = 1'b0;
744
                    Read_precharge[3] = 1'b0;
745
                    RW_interrupt_read[3] = 1'b0;
746
                    if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
747
            end
748
        end
749
 
750
        // Internal Precharge or Bst
751
        if (Command[0] == `PRECH) begin                         // Precharge terminate a read with same bank or all banks
752
            if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin
753
                if (Data_out_enable == 1'b1) begin
754
                    Data_out_enable = 1'b0;
755
                end
756
            end
757
        end else if (Command[0] == `BST) begin                  // BST terminate a read to current bank
758
            if (Data_out_enable == 1'b1) begin
759
                Data_out_enable = 1'b0;
760
            end
761
        end
762
 
763
        if (Data_out_enable == 1'b0) begin
764
            Dq_reg <= #tOH {data_bits{1'bz}};
765
        end
766
 
767
        // Detect Read or Write command
768
        if (Command[0] == `READ || Command[0] == `READ_A) begin
769
            Bank = Bank_addr[0];
770
            Col = Col_addr[0];
771
            Col_brst = Col_addr[0];
772
            if (Bank_addr[0] == 2'b00) begin
773
                Row = B0_row_addr;
774
            end else if (Bank_addr[0] == 2'b01) begin
775
                Row = B1_row_addr;
776
            end else if (Bank_addr[0] == 2'b10) begin
777
                Row = B2_row_addr;
778
            end else if (Bank_addr[0] == 2'b11) begin
779
                Row = B3_row_addr;
780
            end
781
            Burst_counter = 0;
782
            Data_in_enable = 1'b0;
783
            Data_out_enable = 1'b1;
784
        end else if (Command[0] == `WRITE || Command[0] == `WRITE_A) begin
785
            Bank = Bank_addr[0];
786
            Col = Col_addr[0];
787
            Col_brst = Col_addr[0];
788
            if (Bank_addr[0] == 2'b00) begin
789
                Row = B0_row_addr;
790
            end else if (Bank_addr[0] == 2'b01) begin
791
                Row = B1_row_addr;
792
            end else if (Bank_addr[0] == 2'b10) begin
793
                Row = B2_row_addr;
794
            end else if (Bank_addr[0] == 2'b11) begin
795
                Row = B3_row_addr;
796
            end
797
            Burst_counter = 0;
798
            Data_in_enable = 1'b1;
799
            Data_out_enable = 1'b0;
800
        end
801
 
802
        // DQ buffer (Driver/Receiver)
803
        if (Data_in_enable == 1'b1) begin                                   // Writing Data to Memory
804
            if (Dqm == 1'b0) begin
805
                if (Bank == 2'b00) Bank0 [{Row, Col}] = Dq;
806
                if (Bank == 2'b01) Bank1 [{Row, Col}] = Dq;
807
                if (Bank == 2'b10) Bank2 [{Row, Col}] = Dq;
808
                if (Bank == 2'b11) Bank3 [{Row, Col}] = Dq;
809
                if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %d", $time, Bank, Row, Col, Dq);
810
                // Record tWR time and reset counter
811
                WR_chkp [Bank] = $time;
812
                WR_counter [Bank] = 0;
813
            end else begin
814
                if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
815
            end
816
            // Advance burst counter subroutine
817
            #tHZ Burst;
818
        end else if (Data_out_enable == 1'b1) begin                         // Reading Data from Memory
819
            if (Dqm_reg0 == 1'b0) begin
820
                if (Bank == 2'b00) Dq_reg = #tAC Bank0[{Row, Col}];
821
                if (Bank == 2'b01) Dq_reg = #tAC Bank1[{Row, Col}];
822
                if (Bank == 2'b10) Dq_reg = #tAC Bank2[{Row, Col}];
823
                if (Bank == 2'b11) Dq_reg = #tAC Bank3[{Row, Col}];
824
                if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = %d", $time, Bank, Row, Col, Dq_reg);
825
            end else begin
826
                Dq_reg = #tHZ {data_bits{1'bz}};
827
                if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
828
            end
829
            // Advance burst counter subroutine
830
            Burst;
831
        end
832
    end
833
 
834
    //  Write with Auto Precharge Calculation
835
    //      The device start internal precharge:
836
    //          1.  tWR Clock after last burst
837
    //      and 2.  Meet minimum tRAS requirement
838
    //       or 3.  Interrupt by a Read or Write (with or without AutoPrecharge)
839
    always @ (RAS_clk) begin
840
        if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin
841
            if ((($time - RAS_chk0 >= tRAS) &&                                                          // Case 2
842
               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1 && $time - Count_time[0] >= tWRa) ||   // Case 1
843
                 (Burst_length_2 == 1'b1 && Count_precharge [0] >= 2 && $time - Count_time[0] >= tWRa) ||
844
                 (Burst_length_4 == 1'b1 && Count_precharge [0] >= 4 && $time - Count_time[0] >= tWRa) ||
845
                 (Burst_length_8 == 1'b1 && Count_precharge [0] >= 8 && $time - Count_time[0] >= tWRa))) ||
846
                 (RW_interrupt_write[0] == 1'b1 && WR_counter[0] >= 1 && $time - WR_time[0] >= tWRa)) begin                           // Case 3 (stop count when interrupt)
847
                    Auto_precharge[0] = 1'b0;
848
                    Write_precharge[0] = 1'b0;
849
                    RW_interrupt_write[0] = 1'b0;
850
                    Pc_b0 = 1'b1;
851
                    Act_b0 = 1'b0;
852
                    RP_chk0 = $time;
853
                    if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
854
            end
855
        end
856
        if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin
857
            if ((($time - RAS_chk1 >= tRAS) &&
858
               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1 && $time - Count_time[1] >= tWRa) ||
859
                 (Burst_length_2 == 1'b1 && Count_precharge [1] >= 2 && $time - Count_time[1] >= tWRa) ||
860
                 (Burst_length_4 == 1'b1 && Count_precharge [1] >= 4 && $time - Count_time[1] >= tWRa) ||
861
                 (Burst_length_8 == 1'b1 && Count_precharge [1] >= 8 && $time - Count_time[1] >= tWRa))) ||
862
                 (RW_interrupt_write[1] == 1'b1 && WR_counter[1] >= 1 && $time - WR_time[1] >= tWRa)) begin
863
                    Auto_precharge[1] = 1'b0;
864
                    Write_precharge[1] = 1'b0;
865
                    RW_interrupt_write[1] = 1'b0;
866
                    Pc_b1 = 1'b1;
867
                    Act_b1 = 1'b0;
868
                    RP_chk1 = $time;
869
                    if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
870
            end
871
        end
872
        if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin
873
            if ((($time - RAS_chk2 >= tRAS) &&
874
               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1 && $time - Count_time[2] >= tWRa) ||
875
                 (Burst_length_2 == 1'b1 && Count_precharge [2] >= 2 && $time - Count_time[2] >= tWRa) ||
876
                 (Burst_length_4 == 1'b1 && Count_precharge [2] >= 4 && $time - Count_time[2] >= tWRa) ||
877
                 (Burst_length_8 == 1'b1 && Count_precharge [2] >= 8 && $time - Count_time[2] >= tWRa))) ||
878
                 (RW_interrupt_write[2] == 1'b1 && WR_counter[2] >= 1 && $time - WR_time[2] >= tWRa)) begin
879
                    Auto_precharge[2] = 1'b0;
880
                    Write_precharge[2] = 1'b0;
881
                    RW_interrupt_write[2] = 1'b0;
882
                    Pc_b2 = 1'b1;
883
                    Act_b2 = 1'b0;
884
                    RP_chk2 = $time;
885
                    if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
886
            end
887
        end
888
        if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin
889
            if ((($time - RAS_chk3 >= tRAS) &&
890
               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1 && $time - Count_time[3] >= tWRa) ||
891
                 (Burst_length_2 == 1'b1 && Count_precharge [3] >= 2 && $time - Count_time[3] >= tWRa) ||
892
                 (Burst_length_4 == 1'b1 && Count_precharge [3] >= 4 && $time - Count_time[3] >= tWRa) ||
893
                 (Burst_length_8 == 1'b1 && Count_precharge [3] >= 8 && $time - Count_time[3] >= tWRa))) ||
894
                 (RW_interrupt_write[3] == 1'b1 && WR_counter[3] >= 1 && $time - WR_time[3] >= tWRa)) begin
895
                    Auto_precharge[3] = 1'b0;
896
                    Write_precharge[3] = 1'b0;
897
                    RW_interrupt_write[3] = 1'b0;
898
                    Pc_b3 = 1'b1;
899
                    Act_b3 = 1'b0;
900
                    RP_chk3 = $time;
901
                    if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
902
            end
903
        end
904
    end
905
 
906
    task Burst;
907
        begin
908
            // Advance Burst Counter
909
            Burst_counter = Burst_counter + 1;
910
 
911
            // Burst Type
912
            if (Mode_reg[3] == 1'b0) begin                                  // Sequential Burst
913
                Col_temp = Col + 1;
914
            end else if (Mode_reg[3] == 1'b1) begin                         // Interleaved Burst
915
                Col_temp[2] =  Burst_counter[2] ^  Col_brst[2];
916
                Col_temp[1] =  Burst_counter[1] ^  Col_brst[1];
917
                Col_temp[0] =  Burst_counter[0] ^  Col_brst[0];
918
            end
919
 
920
            // Burst Length
921
            if (Burst_length_2) begin                                       // Burst Length = 2
922
                Col [0] = Col_temp [0];
923
            end else if (Burst_length_4) begin                              // Burst Length = 4
924
                Col [1 : 0] = Col_temp [1 : 0];
925
            end else if (Burst_length_8) begin                              // Burst Length = 8
926
                Col [2 : 0] = Col_temp [2 : 0];
927
            end else begin                                                  // Burst Length = FULL
928
                Col = Col_temp;
929
            end
930
 
931
            // Burst Read Single Write            
932
            if (Write_burst_mode == 1'b1) begin
933
                Data_in_enable = 1'b0;
934
            end
935
 
936
            // Data Counter
937
            if (Burst_length_1 == 1'b1) begin
938
                if (Burst_counter >= 1) begin
939
                    Data_in_enable = 1'b0;
940
                    Data_out_enable = 1'b0;
941
                end
942
            end else if (Burst_length_2 == 1'b1) begin
943
                if (Burst_counter >= 2) begin
944
                    Data_in_enable = 1'b0;
945
                    Data_out_enable = 1'b0;
946
                end
947
            end else if (Burst_length_4 == 1'b1) begin
948
                if (Burst_counter >= 4) begin
949
                    Data_in_enable = 1'b0;
950
                    Data_out_enable = 1'b0;
951
                end
952
            end else if (Burst_length_8 == 1'b1) begin
953
                if (Burst_counter >= 8) begin
954
                    Data_in_enable = 1'b0;
955
                    Data_out_enable = 1'b0;
956
                end
957
            end
958
        end
959
    endtask
960
 
961
    // Timing Parameters for -7E and CAS Latency = 2
962
    specify
963
        specparam
964
                    tAH  =  0.8,                                        // Addr, Ba Hold Time
965
                    tAS  =  1.5,                                        // Addr, Ba Setup Time
966
                    tCH  =  2.5,                                        // Clock High-Level Width
967
                    tCL  =  2.5,                                        // Clock Low-Level Width
968
                    tCK  = 10,                                          // Clock Cycle Time
969
                    tDH  =  0.8,                                        // Data-in Hold Time
970
                    tDS  =  1.5,                                        // Data-in Setup Time
971
                    tCKH =  0.8,                                        // CKE Hold  Time
972
                    tCKS =  1.5,                                        // CKE Setup Time
973
                    tCMH =  0.8,                                        // CS#, RAS#, CAS#, WE#, DQM# Hold  Time
974
                    tCMS =  1.5;                                        // CS#, RAS#, CAS#, WE#, DQM# Setup Time
975
        $width    (posedge Clk,           tCH);
976
        $width    (negedge Clk,           tCL);
977
        $period   (negedge Clk,           tCK);
978
        $period   (posedge Clk,           tCK);
979
        $setuphold(posedge Clk,    Cke,   tCKS, tCKH);
980
        $setuphold(posedge Clk,    Cs_n,  tCMS, tCMH);
981
        $setuphold(posedge Clk,    Cas_n, tCMS, tCMH);
982
        $setuphold(posedge Clk,    Ras_n, tCMS, tCMH);
983
        $setuphold(posedge Clk,    We_n,  tCMS, tCMH);
984
        $setuphold(posedge Clk,    Addr,  tAS,  tAH);
985
        $setuphold(posedge Clk,    Ba,    tAS,  tAH);
986
        $setuphold(posedge Clk,    Dqm,   tCMS, tCMH);
987
        $setuphold(posedge Dq_chk, Dq,    tDS,  tDH);
988
    endspecify
989
 
990
endmodule
991
 

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