URL https://opencores.org/ocsvn/mem_ctrl/mem_ctrl/trunk

Subversion Repositories mem_ctrl

[/] [mem_ctrl/] [trunk/] [bench/] [verilog/] [sram_models/] [IDT71T67802/] [readme_71T67802] - Blame information for rev 28

Line No.	Rev	Author	Line
1	4	rudi	`IDT71V2578 - s133/150/166/183/200 verilog models/testbench`
2			`----------------------------------------------------------`
3			`07/09/99`
4			`rev01 - devoloped from IDT71V2576_rev01`
5
6			`----------------------------------------------------------`
7			`03/23/00`
8			`built from 71V2578 verilog file`
9			`----------------------------------------------------------`
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