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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Top Level Test Bench                                       ////
////  Task Library                                               ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: test_lib.v,v 1.4 2002-01-21 13:10:37 rudi Exp $
//
//  $Date: 2002-01-21 13:10:37 $
//  $Revision: 1.4 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.3  2001/11/11 01:52:03  rudi
//
//               Minor fixes to testbench ...
//
//               Revision 1.2  2001/09/02 02:29:43  rudi
//
//               Fixed the TMS register setup to be tight and correct.
//
//               Revision 1.1  2001/07/29 07:34:40  rudi
//
//
//               1) Changed Directory Structure
//               2) Fixed several minor bugs
//
//               Revision 1.1.1.1  2001/05/13 09:36:38  rudi
//               Created Directory Structure
//
//
//
//                        
 
 
/////////////////////////////////////////////////////////////////////
//
// Bandwidth Monitor
//
 
always @(posedge clk)
        if(wb_cyc_i)    cyc_cnt = cyc_cnt + 1;
 
always @(posedge clk)
        if(wb_ack_o)    ack_cnt = ack_cnt + 1;
 
task bw_report;
 
integer bytes;
 
begin
 
bytes = ack_cnt * 4;
$display("Last WB Bandwidth: %0d Mbytes/sec", bytes * 1000/(cyc_cnt * 10));
end
endtask
 
task bw_clear;
 
begin
cyc_cnt = 0;
ack_cnt = 0;
end
endtask
 
/////////////////////////////////////////////////////////////////////
//
// Suspend Resume Task
//
 
task susp_res;
begin
 
        #1;
        susp_req = 1;
        while(!suspended)       @(posedge clk);
        #1;
        susp_req = 0;
        repeat(20)              @(posedge clk);
        #1;
        resume_req = 1;
        while(suspended)        @(posedge clk);
        #1;
        resume_req = 0;
        repeat(1)               @(posedge clk);
 
end
endtask
 
/////////////////////////////////////////////////////////////////////
//
// Bus Request/Grant Task
//
task bus_req;
begin
        mc_br = 1;
        while(!mc_bg)   @(posedge clk);
        repeat(40)      @(posedge clk);
        mc_br = 0;
        repeat(2)       @(posedge clk);
end
endtask
 
/////////////////////////////////////////////////////////////////////
//
// Monitor CKE
//
time    cke_low;
 
always @(negedge mc_cke_)
        cke_low = $time;
 
always @(posedge mc_cke_)
        if(($time-cke_low) < 10)
        $display("WARNING: Cke low period was %t. (%t, %t)",($time-cke_low), cke_low, $time);
 
/////////////////////////////////////////////////////////////////////
//
// Monitor wb_err_o
//
always @(posedge clk)
        if(wb_err_o & !wb_err_check_dis)
                $display("WARNING: WB_ERR_O was asserted at time %0t",$time);
 
/////////////////////////////////////////////////////////////////////
//
// Watchdog Counter
//
 
always @(wb_ack_o or wb_stb_i)
        wd_cnt = 0;
 
always @(posedge clk)
        wd_cnt = wd_cnt + 1;
 
always @(wd_cnt)
        if(wd_cnt>6000)
           begin
                $display("\n\n*************************************\n");
                $display("ERROR: Watch Dog Counter Expired\n");
                $display("*************************************\n\n\n");
                $finish;
           end
 
/////////////////////////////////////////////////////////////////////
//
// Show Errors
//
 
task show_errors;
 
begin
 
$display("\n");
$display("     +--------------------+");
$display("     |  Total ERRORS: %0d   |", error_cnt);
$display("     +--------------------+");
 
end
endtask
 
/////////////////////////////////////////////////////////////////////
//
// Reset Memory Controller
//
 
task mc_reset;
 
begin
repeat(10)      @(posedge clk);
rst = 1;
repeat(10)      @(posedge clk);
rst = 0;
repeat(20)      @(posedge clk);
end
endtask
 
/////////////////////////////////////////////////////////////////////
//
// Fill SDRAMs
//
 
task fill_mem;
input   size;
 
integer         size, n;
reg     [31:0]   data;
 
begin
sdram0.mem_fill(size);
 
for(n=0;n<size;n=n+1)
   begin
        data = sdram0.Bank0[n];
        sdram0p.Bank0[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
        data = sdram0.Bank1[n];
        sdram0p.Bank1[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
        data = sdram0.Bank2[n];
        sdram0p.Bank2[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
        data = sdram0.Bank3[n];
        sdram0p.Bank3[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
   end
 
end
endtask
 
 
task fill_mem1;
input   size;
 
integer         size, n;
reg     [31:0]   data;
 
begin
sdram1.mem_fill(size);
 
for(n=0;n<size;n=n+1)
   begin
        data = sdram1.Bank0[n];
        sdram1p.Bank0[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
        data = sdram1.Bank1[n];
        sdram1p.Bank1[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
        data = sdram1.Bank2[n];
        sdram1p.Bank2[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
        data = sdram1.Bank3[n];
        sdram1p.Bank3[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
   end
 
end
endtask
 
task fill_mem2;
input   size;
 
integer         size, n;
reg     [31:0]   data;
 
begin
sdram2.mem_fill(size);
 
for(n=0;n<size;n=n+1)
   begin
        data = sdram2.Bank0[n];
        sdram2p.Bank0[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
        data = sdram2.Bank1[n];
        sdram2p.Bank1[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
        data = sdram2.Bank2[n];
        sdram2p.Bank2[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
        data = sdram2.Bank3[n];
        sdram2p.Bank3[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
   end
 
end
endtask
 
 

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Top Level Test Bench ////`
4			`//// Task Library ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15	23	rudi	`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
16			`//// www.asics.ws ////`
17			`//// rudi@asics.ws ////`
18	4	rudi	`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer.////`
23			`//// ////`
24			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
25			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
26			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
27			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
28			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
29			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
30			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
31			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
32			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
33			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
34			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
35			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
36			`//// POSSIBILITY OF SUCH DAMAGE. ////`
37			`//// ////`
38			`/////////////////////////////////////////////////////////////////////`
39
40			`// CVS Log`
41			`//`
42	23	rudi	`// $Id: test_lib.v,v 1.4 2002-01-21 13:10:37 rudi Exp $`
43	4	rudi	`//`
44	23	rudi	`// $Date: 2002-01-21 13:10:37 $`
45			`// $Revision: 1.4 $`
46	4	rudi	`// $Author: rudi $`
47			`// $Locker: $`
48			`// $State: Exp $`
49			`//`
50			`// Change History:`
51			`// $Log: not supported by cvs2svn $`
52	23	rudi	`// Revision 1.3 2001/11/11 01:52:03 rudi`
53			`//`
54			`// Minor fixes to testbench ...`
55			`//`
56	14	rudi	`// Revision 1.2 2001/09/02 02:29:43 rudi`
57			`//`
58			`// Fixed the TMS register setup to be tight and correct.`
59			`//`
60	10	rudi	`// Revision 1.1 2001/07/29 07:34:40 rudi`
61			`//`
62			`//`
63			`// 1) Changed Directory Structure`
64			`// 2) Fixed several minor bugs`
65			`//`
66	4	rudi	`// Revision 1.1.1.1 2001/05/13 09:36:38 rudi`
67			`// Created Directory Structure`
68			`//`
69			`//`
70			`//`
71			`//`
72
73
74			`/////////////////////////////////////////////////////////////////////`
75			`//`
76			`// Bandwidth Monitor`
77			`//`
78
79			`always @(posedge clk)`
80			`if(wb_cyc_i) cyc_cnt = cyc_cnt + 1;`
81
82			`always @(posedge clk)`
83			`if(wb_ack_o) ack_cnt = ack_cnt + 1;`
84
85			`task bw_report;`
86
87			`integer bytes;`
88
89			`begin`
90
91			`bytes = ack_cnt * 4;`
92			`$display("Last WB Bandwidth: %0d Mbytes/sec", bytes * 1000/(cyc_cnt * 10));`
93			`end`
94			`endtask`
95
96			`task bw_clear;`
97
98			`begin`
99			`cyc_cnt = 0;`
100			`ack_cnt = 0;`
101			`end`
102			`endtask`
103
104			`/////////////////////////////////////////////////////////////////////`
105			`//`
106			`// Suspend Resume Task`
107			`//`
108
109			`task susp_res;`
110			`begin`
111
112	10	rudi	`#1;`
113	4	rudi	`susp_req = 1;`
114			`while(!suspended) @(posedge clk);`
115	10	rudi	`#1;`
116	4	rudi	`susp_req = 0;`
117	23	rudi	`repeat(20) @(posedge clk);`
118	10	rudi	`#1;`
119	4	rudi	`resume_req = 1;`
120			`while(suspended) @(posedge clk);`
121	10	rudi	`#1;`
122	4	rudi	`resume_req = 0;`
123	23	rudi	`repeat(1) @(posedge clk);`
124	4	rudi
125			`end`
126			`endtask`
127
128			`/////////////////////////////////////////////////////////////////////`
129			`//`
130			`// Bus Request/Grant Task`
131			`//`
132			`task bus_req;`
133			`begin`
134			`mc_br = 1;`
135			`while(!mc_bg) @(posedge clk);`
136			`repeat(40) @(posedge clk);`
137			`mc_br = 0;`
138			`repeat(2) @(posedge clk);`
139			`end`
140			`endtask`
141
142			`/////////////////////////////////////////////////////////////////////`
143			`//`
144			`// Monitor CKE`
145			`//`
146			`time cke_low;`
147
148			`always @(negedge mc_cke_)`
149			`cke_low = $time;`
150
151			`always @(posedge mc_cke_)`
152			`if(($time-cke_low) < 10)`
153			`$display("WARNING: Cke low period was %t. (%t, %t)",($time-cke_low), cke_low, $time);`
154
155			`/////////////////////////////////////////////////////////////////////`
156			`//`
157			`// Monitor wb_err_o`
158			`//`
159			`always @(posedge clk)`
160			`if(wb_err_o & !wb_err_check_dis)`
161			`$display("WARNING: WB_ERR_O was asserted at time %0t",$time);`
162
163			`/////////////////////////////////////////////////////////////////////`
164			`//`
165			`// Watchdog Counter`
166			`//`
167
168			`always @(wb_ack_o or wb_stb_i)`
169			`wd_cnt = 0;`
170
171			`always @(posedge clk)`
172			`wd_cnt = wd_cnt + 1;`
173
174			`always @(wd_cnt)`
175	10	rudi	`if(wd_cnt>6000)`
176	4	rudi	`begin`
177			`$display("\n\n*************************************\n");`
178			`$display("ERROR: Watch Dog Counter Expired\n");`
179			`$display("*************************************\n\n\n");`
180			`$finish;`
181			`end`
182
183	23	rudi	`/////////////////////////////////////////////////////////////////////`
184			`//`
185			`// Show Errors`
186			`//`
187	4	rudi
188			`task show_errors;`
189
190			`begin`
191
192			`$display("\n");`
193			`$display(" +--------------------+");`
194			`$display(" \| Total ERRORS: %0d \|", error_cnt);`
195			`$display(" +--------------------+");`
196
197			`end`
198			`endtask`
199
200	23	rudi	`/////////////////////////////////////////////////////////////////////`
201			`//`
202			`// Reset Memory Controller`
203			`//`
204	4	rudi
205			`task mc_reset;`
206
207			`begin`
208	10	rudi	`repeat(10) @(posedge clk);`
209	14	rudi	`rst = 1;`
210			`repeat(10) @(posedge clk);`
211	4	rudi	`rst = 0;`
212	10	rudi	`repeat(20) @(posedge clk);`
213	4	rudi	`end`
214			`endtask`
215
216	23	rudi	`/////////////////////////////////////////////////////////////////////`
217			`//`
218			`// Fill SDRAMs`
219			`//`
220
221			`task fill_mem;`
222			`input size;`
223
224			`integer size, n;`
225			`reg [31:0] data;`
226
227			`begin`
228			`sdram0.mem_fill(size);`
229
230			`for(n=0;n<size;n=n+1)`
231			`begin`
232			`data = sdram0.Bank0[n];`
233			`sdram0p.Bank0[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };`
234			`data = sdram0.Bank1[n];`
235			`sdram0p.Bank1[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };`
236			`data = sdram0.Bank2[n];`
237			`sdram0p.Bank2[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };`
238			`data = sdram0.Bank3[n];`
239			`sdram0p.Bank3[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };`
240			`end`
241
242			`end`
243			`endtask`
244
245
246			`task fill_mem1;`
247			`input size;`
248
249			`integer size, n;`
250			`reg [31:0] data;`
251
252			`begin`
253			`sdram1.mem_fill(size);`
254
255			`for(n=0;n<size;n=n+1)`
256			`begin`
257			`data = sdram1.Bank0[n];`
258			`sdram1p.Bank0[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };`
259			`data = sdram1.Bank1[n];`
260			`sdram1p.Bank1[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };`
261			`data = sdram1.Bank2[n];`
262			`sdram1p.Bank2[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };`
263			`data = sdram1.Bank3[n];`
264			`sdram1p.Bank3[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };`
265			`end`
266
267			`end`
268			`endtask`
269
270			`task fill_mem2;`
271			`input size;`
272
273			`integer size, n;`
274			`reg [31:0] data;`
275
276			`begin`
277			`sdram2.mem_fill(size);`
278
279			`for(n=0;n<size;n=n+1)`
280			`begin`
281			`data = sdram2.Bank0[n];`
282			`sdram2p.Bank0[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };`
283			`data = sdram2.Bank1[n];`
284			`sdram2p.Bank1[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };`
285			`data = sdram2.Bank2[n];`
286			`sdram2p.Bank2[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };`
287			`data = sdram2.Bank3[n];`
288			`sdram2p.Bank3[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };`
289			`end`
290
291			`end`
292			`endtask`
293
294

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[/] [mem_ctrl/] [trunk/] [bench/] [verilog/] [test_lib.v] - Blame information for rev 28