Subversion Repositories mem_ctrl

/////////////////////////////////////////////////////////////////////

////                                                             ////

////  Top Level Test Bench                                       ////

////                                                             ////

////                                                             ////

////  Author: Rudolf Usselmann                                   ////

////          rudi@asics.ws                                      ////

////                                                             ////

////                                                             ////

////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

////                                                             ////

//// Copyright (C) 2000 Rudolf Usselmann                         ////

////                    rudi@asics.ws                            ////

////                                                             ////

//// This source file may be used and distributed without        ////

//// restriction provided that this copyright statement is not   ////

//// removed from the file and that any derivative work contains ////

//// the original copyright notice and the associated disclaimer.////

////                                                             ////

////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////

//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////

//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////

//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////

//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////

//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////

//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////

//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////

//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////

//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////

//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////

//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////

//// POSSIBILITY OF SUCH DAMAGE.                                 ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

//  CVS Log

//

//  $Id: tests.v,v 1.3 2001-09-02 02:29:43 rudi Exp $

//

//  $Date: 2001-09-02 02:29:43 $

//  $Revision: 1.3 $

//  $Author: rudi $

//  $Locker:  $

//  $State: Exp $

//

// Change History:

//               $Log: not supported by cvs2svn $

//               Revision 1.2  2001/08/10 08:16:21  rudi

//

//               - Changed IO names to be more clear.

//               - Uniquifyed define names to be core specific.

//               - Removed "Refresh Early" configuration

//

//               Revision 1.1  2001/07/29 07:34:40  rudi

//

//

//               1) Changed Directory Structure

//               2) Fixed several minor bugs

//

//               Revision 1.1.1.1  2001/05/13 09:36:38  rudi

//               Created Directory Structure

//

//

//

//                        

task sdram_rd1;

input           quick;

integer         quick;

integer         n;

integer         del, size;

reg     [7:0]    mode;

reg     [2:0]    bs;

integer         sz_inc;

integer         sz_max, del_max;

integer         write;

begin

$display("\n\n");

$display("*****************************************************");

$display("*** SDRAM Size, Delay & Mode Read test 1 ...      ***");

$display("*****************************************************\n");

m0.wb_wr1(`REG_BASE + `CSR,     4'hf, 32'h6030_0300);

m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);

m0.wb_wr1(`REG_BASE + `TMS0,    4'hf, {

                                        4'd0,           // RESERVED [31:28]

                                        4'd7,           // Trfc [27:24]

                                        4'd2,           // Trp [23:20]

                                        3'd2,           // Trcd [19:17]

                                        2'd1,           // Twr [16:15]

                                        5'd0,           // RESERVED [14:10]

                                        1'd0,   // Wr. Burst Len (1=Single)

                                        2'd0,   // Op Mode

                                        3'd2,   // CL

                                        1'b0,   // Burst Type (0=Seq;1=Inter)

                                        3'd3    // Burst Length

                                        });

//m0.wb_wr1(`REG_BASE + `CSC0,  4'hf, 32'h0000_0821);

m0.wb_wr1(`REG_BASE + `CSC0,    4'hf, 32'h0000_0021);

case(quick)

 0: sz_max = 64;

 1: sz_max = 32;

 2: sz_max = 16;

endcase

case(quick)

 0: del_max = 16;

 1: del_max = 8;

 2: del_max = 4;

endcase

size = 4;

del = 1;

mode = 2;

write = 0;

//force sdram0.Debug = 1;

for(mode=0;mode<10;mode=mode+1)

begin

        sdram0.mem_fill(1024);

        //sdram0p.mem_fill(1024);

        case(mode[3:1])

           0: bs = 0;

           1: bs = 1;

           2: bs = 2;

           3: bs = 3;

           4: bs = 7;

        endcase

        case(mode[3:1])

           0: sz_inc = 1;

           1: sz_inc = 2;

           2: sz_inc = 4;

           3: sz_inc = 8;

           4: sz_inc = 1;

        endcase

        m0.wb_wr1(`REG_BASE + `TMS0,    4'hf, {

                                        4'd0,           // RESERVED [31:28]

                                        4'd7,           // Trfc [27:24]

                                        4'd2,           // Trp [23:20]

                                        3'd2,           // Trcd [19:17]

                                        2'd1,           // Twr [16:15]

                                        5'd0,           // RESERVED [14:10]

                                        1'd0,           // Wr. Burst Len (1=Single)

                                        2'd0,           // Op Mode

                                        3'd2+mode[0],    // CL

                                        1'b0,           // Burst Type (0=Seq;1=Inter)

                                        3'd0+bs         // Burst Length

                                        });

if(!verbose)    $display("Mode: %b", mode);

for(del=0;del<del_max;del=del+1)

for(size=sz_inc;size<sz_max;size=size+sz_inc)

   begin

        m0.mem_fill;

        if(verbose)     $display("Mode: %b, Size: %0d, Delay: %0d", mode,  size, del);

        if(write)       m0.wb_wr_mult(`MEM_BASE +        0, 4'hf, del, size);

        m0.wb_rd_mult(`MEM_BASE +        0, 4'hf, del, size);

        if(write)       m0.wb_wr_mult(`MEM_BASE + size*1*4, 4'hf, del, size);

        m0.wb_rd_mult(`MEM_BASE + size*1*4, 4'hf, del, size);

        if(write)       m0.wb_wr_mult(`MEM_BASE + size*2*4, 4'hf, del, size);

        m0.wb_rd_mult(`MEM_BASE + size*2*4, 4'hf, del, size);

        if(write)       m0.wb_wr_mult(`MEM_BASE + size*3*4, 4'hf, del, size);

        m0.wb_rd_mult(`MEM_BASE + size*3*4, 4'hf, del, size);

        for(n=0;n<(size*4);n=n+1)

           begin

                if((sdram0.Bank0[n] !== m0.rd_mem[n]) |

                        (|sdram0.Bank0[n] === 1'bx) |

                        (|m0.rd_mem[n] === 1'bx)         )

                   begin

                        $display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",

                        n, sdram0.Bank0[n], m0.rd_mem[n],  $time);

                        error_cnt = error_cnt + 1;

                   end

           end

   end

end

show_errors;

$display("*****************************************************");

$display("*** Test DONE ...                                 ***");

$display("*****************************************************\n\n");

end

endtask

task sdram_wr1;

input           quick;

integer         quick;

integer         n;

integer         del, size;

reg     [7:0]    mode;

reg     [2:0]    bs;

integer         sz_inc;

integer         sz_max, del_max;

integer         read;

begin

$display("\n\n");

$display("*****************************************************");

$display("*** SDRAM Size, Delay & Mode Write test 1 ...     ***");

$display("*****************************************************\n");

m0.wb_wr1(`REG_BASE + `CSR,     4'hf, 32'h6030_0300);

m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);

m0.wb_wr1(`REG_BASE + `TMS0,    4'hf, {

                                        4'd0,           // RESERVED [31:28]

                                        4'd7,           // Trfc [27:24]

                                        4'd2,           // Trp [23:20]

                                        3'd2,           // Trcd [19:17]

                                        2'd1,           // Twr [16:15]

                                        5'd0,           // RESERVED [14:10]

                                        1'd0,   // Wr. Burst Len (1=Single)

                                        2'd0,   // Op Mode

                                        3'd2,   // CL

                                        1'b0,   // Burst Type (0=Seq;1=Inter)

                                        3'd3    // Burst Length

                                        });

m0.wb_wr1(`REG_BASE + `CSC0,    4'hf, 32'h0000_0821);

case(quick)

 0: sz_max = 64;

 1: sz_max = 32;

 2: sz_max = 16;

endcase

case(quick)

 0: del_max = 16;

 1: del_max = 8;

 2: del_max = 4;

endcase

size = 1;

del = 0;

mode = 0;

read = 1;

//force sdram0.Debug = 1;

for(mode=0;mode<20;mode=mode+1)

begin

        sdram0.mem_fill(1024);

        case(mode[4:2])

           0: bs = 0;

           1: bs = 1;

           2: bs = 2;

           3: bs = 3;

           4: bs = 7;

        endcase

        if(mode[1])

           sz_inc = 1;

        else

                case(mode[4:2])

                   0: sz_inc = 1;

                   1: sz_inc = 2;

                   2: sz_inc = 4;

                   3: sz_inc = 8;

                   4: sz_inc = 1;

                endcase

        m0.wb_wr1(`REG_BASE + `TMS0,    4'hf, {

                                        4'd0,           // RESERVED [31:28]

                                        4'd7,           // Trfc [27:24]

                                        4'd2,           // Trp [23:20]

                                        3'd2,           // Trcd [19:17]

                                        2'd1,           // Twr [16:15]

                                        5'd0,           // RESERVED [14:10]

                                        1'd0+mode[1],   // Wr. Burst Len (1=Single)

                                        2'd0,           // Op Mode

                                        3'd2+mode[0],    // CL

                                        1'b0,           // Burst Type (0=Seq;1=Inter)

                                        3'd0+bs         // Burst Length

                                        });

if(!verbose)    $display("Mode: %b", mode);

for(del=0;del<del_max;del=del+1)

for(size=sz_inc;size<sz_max;size=size+sz_inc)

   begin

        m0.mem_fill;

        if(verbose)     $display("Mode: %b, Size: %0d, Delay: %0d", mode,  size, del);

        m0.wb_wr_mult(`MEM_BASE +        0, 4'hf, del, size);

        if(read)        m0.wb_rd_mult(`MEM_BASE +        0, 4'hf, del, size);

        m0.wb_wr_mult(`MEM_BASE + size*1*4, 4'hf, del, size);

        if(read)        m0.wb_rd_mult(`MEM_BASE + size*1*4, 4'hf, del, size);

        m0.wb_wr_mult(`MEM_BASE + size*2*4, 4'hf, del, size);

        if(read)        m0.wb_rd_mult(`MEM_BASE + size*2*4, 4'hf, del, size);

        m0.wb_wr_mult(`MEM_BASE + size*3*4, 4'hf, del, size);

        if(read)        m0.wb_rd_mult(`MEM_BASE + size*3*4, 4'hf, del, size);

        repeat(10)      @(posedge clk);

        for(n=0;n< (size*4);n=n+1)

           begin

                if((sdram0.Bank0[n] !== m0.wr_mem[n]) |

                        (|sdram0.Bank0[n] === 1'bx) |

                        (|m0.wr_mem[n] === 1'bx)         )

                   begin

                        $display("ERROR: WR Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",

                        n, sdram0.Bank0[n], m0.wr_mem[n],  $time);

                        error_cnt = error_cnt + 1;

                   end

           end

   end

end

show_errors;

$display("*****************************************************");

$display("*** Test DONE ...                                 ***");

$display("*****************************************************\n\n");

end

endtask

task sdram_rd2;

input           quick;

integer         quick;

integer         n,m,adr;

integer         del, size;

reg     [7:0]    mode;

reg     [2:0]    bs;

integer         sz_inc;

integer         sz_max, del_max;

reg     [2:0]    bas;

reg     [31:0]   data;

integer         page_size;

begin

$display("\n\n");

$display("*****************************************************");

$display("*** SDRAM Size, Delay & Mode Read test 2 ...      ***");

$display("*** Different Row and Bank                        ***");

$display("*****************************************************\n");

page_size = 256; // 64 mbit x 32 SDRAM

case(quick)

 0: sz_max = 32;

 1: sz_max = 32;

 2: sz_max = 16;

endcase

case(quick)

 0: del_max = 16;

 1: del_max = 8;

 2: del_max = 4;

endcase

m0.wb_wr1(`REG_BASE + `CSR,     4'hf, 32'h6030_0300);

m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);

m0.wb_wr1(`REG_BASE + `TMS0,    4'hf, {

                                        4'd0,           // RESERVED [31:28]

                                        4'd7,           // Trfc [27:24]

                                        4'd2,           // Trp [23:20]

                                        3'd2,           // Trcd [19:17]

                                        2'd1,           // Twr [16:15]

                                        5'd0,           // RESERVED [14:10]

                                        1'd0,   // Wr. Burst Len (1=Single)

                                        2'd0,   // Op Mode

                                        3'd2,   // CL

                                        1'b0,   // Burst Type (0=Seq;1=Inter)

                                        3'd3    // Burst Length

                                        });

bas = 0;

for(bas=0;bas<2;bas=bas+1)

begin

m0.wb_wr1(`REG_BASE + `CSC0,    4'hf, 32'h0000_0821 | (bas[0]<<9));

size = 33;

del = 0;

mode = 0;

//force sdram0.Debug = 1;

for(mode=0;mode<10;mode=mode+1)

begin

        sdram0.mem_fill(1024);

        case(mode[3:1])

           0: bs = 0;

           1: bs = 1;

           2: bs = 2;

           3: bs = 3;

           4: bs = 7;

        endcase

        case(mode[3:1])

           0: sz_inc = 1;

           1: sz_inc = 2;

           2: sz_inc = 4;

           3: sz_inc = 8;

           4: sz_inc = 1;

        endcase

        m0.wb_wr1(`REG_BASE + `TMS0,    4'hf, {

                                        4'd0,           // RESERVED [31:28]

                                        4'd7,           // Trfc [27:24]

                                        4'd2,           // Trp [23:20]

                                        3'd2,           // Trcd [19:17]

                                        2'd1,           // Twr [16:15]

                                        5'd0,           // RESERVED [14:10]

                                        1'd0,           // Wr. Burst Len (1=Single)

                                        2'd0,           // Op Mode

                                        3'd2+mode[0],    // CL

                                        1'b0,           // Burst Type (0=Seq;1=Inter)

                                        3'd0+bs         // Burst Length

                                        });

if(!verbose)    $display("BAS: %0d, Mode: %b", bas, mode);

for(del=0;del<del_max;del=del+1)

for(size=sz_inc;size<sz_max;size=size+sz_inc)

   begin

        m0.mem_fill;

        if(verbose)     $display("BAS: %0d, Mode: %b, Size: %0d, Delay: %0d",

                                bas, mode,  size, del);

        m0.wb_wr_mult(`MEM_BASE + (page_size*0*4) + size*0*4, 4'hf, del, size);

        m0.wb_rd_mult(`MEM_BASE + (page_size*0*4) + size*0*4, 4'hf, del, size);

        m0.wb_wr_mult(`MEM_BASE + (page_size*0*4) + size*1*4, 4'hf, del, size);

        m0.wb_rd_mult(`MEM_BASE + (page_size*0*4) + size*1*4, 4'hf, del, size);

        m0.wb_wr_mult(`MEM_BASE + (page_size*1*4) + size*2*4, 4'hf, del, size);

        m0.wb_rd_mult(`MEM_BASE + (page_size*1*4) + size*2*4, 4'hf, del, size);

        m0.wb_wr_mult(`MEM_BASE + (page_size*1*4) + size*3*4, 4'hf, del, size);

        m0.wb_rd_mult(`MEM_BASE + (page_size*1*4) + size*3*4, 4'hf, del, size);

        m0.wb_wr_mult(`MEM_BASE + (page_size*2*4) + size*4*4, 4'hf, del, size);

        m0.wb_rd_mult(`MEM_BASE + (page_size*2*4) + size*4*4, 4'hf, del, size);

        m0.wb_wr_mult(`MEM_BASE + (page_size*2*4) + size*5*4, 4'hf, del, size);

        m0.wb_rd_mult(`MEM_BASE + (page_size*2*4) + size*5*4, 4'hf, del, size);

        m0.wb_wr_mult(`MEM_BASE + (page_size*3*4) + size*6*4, 4'hf, del, size);

        m0.wb_rd_mult(`MEM_BASE + (page_size*3*4) + size*6*4, 4'hf, del, size);

        m0.wb_wr_mult(`MEM_BASE + (page_size*3*4) + size*7*4, 4'hf, del, size);

        m0.wb_rd_mult(`MEM_BASE + (page_size*3*4) + size*7*4, 4'hf, del, size);

        for(m=0;m<4;m=m+1)

        for(n=0;n<(size*2);n=n+1)

           begin

                adr = (m * page_size) + (m*size*2) + n;

                if(bas[0])       data = sdram0.Bank0[adr];

                else

                case(m)

                   0: data = sdram0.Bank0[n];

                   1: data = sdram0.Bank1[n+1*size*2];

                   2: data = sdram0.Bank2[n+2*size*2];

                   3: data = sdram0.Bank3[n+3*size*2];

                endcase

                if((data !== m0.rd_mem[(m*size*2)+n]) | (|data === 1'bx) |

                        (|m0.rd_mem[(m*size*2)+n] === 1'bx) )

                   begin

                        $display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",

                        (m*size*2)+n, data, m0.rd_mem[(m*size*2)+n],  $time);

                        error_cnt = error_cnt + 1;

                   end

           end

   end

end

end

show_errors;

$display("*****************************************************");

$display("*** Test DONE ...                                 ***");

$display("*****************************************************\n\n");

end

endtask

task sdram_wr2;

input           quick;

integer         quick;

integer         n,m,adr;

integer         del, size;

reg     [7:0]    mode;

reg     [2:0]    bs;

integer         sz_inc;

integer         sz_max, del_max;

integer         read;

reg     [2:0]    bas;

reg     [31:0]   data;

integer         page_size;

begin

$display("\n\n");

$display("*****************************************************");

$display("*** SDRAM Size, Delay & Mode Write test 2 ...     ***");

$display("*** Different Row and Bank                        ***");

$display("*****************************************************\n");

page_size = 256; // 64 mbit x 32 SDRAM

m0.wb_wr1(`REG_BASE + `CSR,     4'hf, 32'h6030_0300);

m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);

m0.wb_wr1(`REG_BASE + `TMS0,    4'hf, {

                                        4'd0,           // RESERVED [31:28]

                                        4'd7,           // Trfc [27:24]

                                        4'd2,           // Trp [23:20]

                                        3'd2,           // Trcd [19:17]

                                        2'd1,           // Twr [16:15]

                                        5'd0,           // RESERVED [14:10]

                                        1'd0,   // Wr. Burst Len (1=Single)

                                        2'd0,   // Op Mode

                                        3'd2,   // CL

                                        1'b0,   // Burst Type (0=Seq;1=Inter)

                                        3'd3    // Burst Length

                                        });

bas = 0;

for(bas=0;bas<2;bas=bas+1)

begin

//m0.wb_wr1(`REG_BASE + `CSC0,  4'hf, 32'h0000_0821 | (bas[0]<<9));

m0.wb_wr1(`REG_BASE + `CSC0,    4'hf, 32'h0000_0021 | (bas[0]<<9));

case(quick)

 0: sz_max = 32;

 1: sz_max = 32;

 2: sz_max = 16;

endcase

case(quick)

 0: del_max = 16;

 1: del_max = 8;

 2: del_max = 4;

endcase

size = 3;

del = 0;

mode = 10;

read = 1;

//force sdram0.Debug = 1;

for(mode=0;mode<20;mode=mode+1)

begin

        sdram0.mem_fill(1024);

        case(mode[4:2])

           0: bs = 0;     // 1 Transfer

           1: bs = 1;   // 2 Transfers

           2: bs = 2;   // 4 Transfers