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[/] [mem_ctrl/] [trunk/] [bench/] [verilog/] [wb_mast_model.v] - Blame information for rev 28

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Master Model                                      ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
///                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_mast_model.v,v 1.3 2001-11-29 02:17:36 rudi Exp $
//
//  $Date: 2001-11-29 02:17:36 $
//  $Revision: 1.3 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.2  2001/11/11 01:52:03  rudi
//
//               Minor fixes to testbench ...
//
//               Revision 1.1  2001/07/29 07:34:40  rudi
//
//
//               1) Changed Directory Structure
//               2) Fixed several minor bugs
//
//               Revision 1.1.1.1  2001/05/13 09:36:33  rudi
//               Created Directory Structure
//
//
//
//
//                        
 
`include "wb_model_defines.v"
 
module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
 
input           clk, rst;
output  [31:0]   adr;
input   [31:0]   din;
output  [31:0]   dout;
output          cyc, stb;
output  [3:0]    sel;
output          we;
input           ack, err, rty;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
parameter mem_size = 4096;
 
reg     [31:0]   adr;
reg     [31:0]   dout;
reg             cyc, stb;
reg     [3:0]    sel;
reg             we;
 
reg     [31:0]   rd_mem[mem_size:0];
reg     [31:0]   wr_mem[mem_size:0];
integer         rd_cnt;
integer         wr_cnt;
 
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
 
initial
   begin
        //adr = 32'hxxxx_xxxx;
        //adr = 0;
        adr = 32'hffff_ffff;
        dout = 32'hxxxx_xxxx;
        cyc = 0;
        stb = 0;
        sel = 4'hx;
        we = 1'hx;
        rd_cnt = 0;
        wr_cnt = 0;
        #1;
        $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
   end
 
 
 
task mem_fill;
 
integer n;
begin
rd_cnt = 0;
wr_cnt = 0;
for(n=0;n<mem_size;n=n+1)
   begin
        rd_mem[n] = $random;
        wr_mem[n] = $random;
   end
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Write 1 Word Task
//
 
task wb_wr1;
input   [31:0]   a;
input   [3:0]    s;
input   [31:0]   d;
 
begin
 
//@(posedge clk);
#1;
adr = a;
dout = d;
cyc = 1;
stb = 1;
we=1;
sel = s;
 
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#1;
cyc=0;
stb=0;
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
//adr = 0;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Write 4 Words Task
//
 
task wb_wr4;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input   [31:0]   d1;
input   [31:0]   d2;
input   [31:0]   d3;
input   [31:0]   d4;
 
integer         delay;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
sel = s;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
adr = a;
dout = d1;
stb = 1;
we=1;
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+4;
dout = d2;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+8;
dout = d3;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+12;
dout = d4;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#1;
stb=0;
cyc=0;
 
adr = 32'hxxxx_xxxx;
//adr = 0;
//adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
 
task wb_wr_mult;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           count;
 
integer         delay;
integer         count;
integer         n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
 
for(n=0;n<count;n=n+1)
   begin
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        adr = a + (n*4);
        dout = wr_mem[n + wr_cnt];
        stb = 1;
        we=1;
        sel = s;
        if(n!=0) @(posedge clk);
        while(~ack & ~err)      @(posedge clk);
        #2;
        stb=0;
        we=1'bx;
        sel = 4'hx;
        dout = 32'hxxxx_xxxx;
        adr = 32'hxxxx_xxxx;
   end
 
cyc=0;
 
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
 
wr_cnt = wr_cnt + count;
end
endtask
 
 
task wb_rmw;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           rcount;
input           wcount;
 
integer         delay;
integer         rcount;
integer         wcount;
 
begin
wb_rmw2(a,a,s,delay,rcount,wcount);
end
endtask
 
 
task wb_rmw2;
input   [31:0]   ra;
input   [31:0]   wa;
input   [3:0]    s;
input           delay;
input           rcount;
input           wcount;
 
integer         delay;
integer         rcount;
integer         wcount;
integer         n;
 
begin
 
//@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)   @(posedge clk);
 
for(n=0;n<rcount-1;n=n+1)
   begin
        adr = ra + (n*4);
        stb = 1;
        while(~ack & ~err)      @(posedge clk);
        rd_mem[n + rd_cnt] = din;
        //$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
        #2;
        stb=0;
        we = 1'hx;
        sel = 4'hx;
        adr = 32'hxxxx_xxxx;
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        we = 0;
        sel = s;
   end
 
adr = ra+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
rd_mem[n + rd_cnt] = din;
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
#1;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
 
rd_cnt = rd_cnt + rcount;
 
//@(posedge clk);
 
 
for(n=0;n<wcount;n=n+1)
   begin
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        adr = wa + (n*4);
        dout = wr_mem[n + wr_cnt];
        stb = 1;
        we=1;
        sel = s;
//      if(n!=0)
                @(posedge clk);
        while(~ack & ~err)      @(posedge clk);
        #2;
        stb=0;
        we=1'bx;
        sel = 4'hx;
        dout = 32'hxxxx_xxxx;
        adr = 32'hxxxx_xxxx;
   end
 
cyc=0;
 
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
 
wr_cnt = wr_cnt + wcount;
end
endtask
 
 
 
 
task wb_wmr;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           rcount;
input           wcount;
 
integer         delay;
integer         rcount;
integer         wcount;
integer         n;
 
begin
 
//@(posedge clk);
#1;
cyc = 1;
we = 1'bx;
sel = 4'hx;
sel = s;
 
for(n=0;n<wcount;n=n+1)
   begin
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        adr = a + (n*4);
        dout = wr_mem[n + wr_cnt];
        stb = 1;
        we=1;
        sel = s;
        @(posedge clk);
        while(~ack & ~err)      @(posedge clk);
        #2;
        stb=0;
        we=1'bx;
        sel = 4'hx;
        dout = 32'hxxxx_xxxx;
        adr = 32'hxxxx_xxxx;
   end
 
wr_cnt = wr_cnt + wcount;
stb=0;
repeat(delay)   @(posedge clk);
#1;
 
sel = s;
we = 0;
for(n=0;n<rcount-1;n=n+1)
   begin
        adr = a + (n*4);
        stb = 1;
        while(~ack & ~err)      @(posedge clk);
        rd_mem[n + rd_cnt] = din;
        //$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
        #2;
        stb=0;
        we = 1'hx;
        sel = 4'hx;
        adr = 32'hxxxx_xxxx;
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        we = 0;
        sel = s;
   end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
rd_mem[n + rd_cnt] = din;
rd_cnt = rd_cnt + rcount;
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
#1;
 
cyc = 0;
stb = 0;
we  = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
 
end
endtask
 
 
 
 
////////////////////////////////////////////////////////////////////
//
// Read 1 Word Task
//
 
task wb_rd1;
input   [31:0]   a;
input   [3:0]    s;
output  [31:0]   d;
 
begin
 
//@(posedge clk);
#1;
adr = a;
cyc = 1;
stb = 1;
we  = 0;
sel = s;
 
//@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d = din;
#1;
cyc=0;
stb=0;
//adr = 32'hxxxx_xxxx;
//adr = 0;
adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
 
////////////////////////////////////////////////////////////////////
//
// Read 4 Words Task
//
 
 
task wb_rd4;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
output  [31:0]   d1;
output  [31:0]   d2;
output  [31:0]   d3;
output  [31:0]   d4;
 
integer         delay;
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)   @(posedge clk);
 
adr = a;
stb = 1;
while(~ack & ~err)      @(posedge clk);
d1 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
adr = a+4;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d2 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
 
adr = a+8;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d3 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
adr = a+12;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d4 = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hffff_ffff;
end
endtask
 
 
 
task wb_rd_mult;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           count;
 
integer         delay;
integer         count;
integer         n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)   @(posedge clk);
 
for(n=0;n<count-1;n=n+1)
   begin
        adr = a + (n*4);
        stb = 1;
        while(~ack & ~err)      @(posedge clk);
        rd_mem[n + rd_cnt] = din;
        #2;
        stb=0;
        we = 1'hx;
        sel = 4'hx;
        adr = 32'hxxxx_xxxx;
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        we = 0;
        sel = s;
   end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
rd_mem[n + rd_cnt] = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hffff_ffff;
adr = 32'hxxxx_xxxx;
 
rd_cnt = rd_cnt + count;
end
endtask
 
endmodule

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Subversion Repositories mem_ctrl

[/] [mem_ctrl/] [trunk/] [bench/] [verilog/] [wb_mast_model.v] - Blame information for rev 28

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Master Model ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16	16	rudi	`/// ////`
17	4	rudi	`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40	16	rudi	`// $Id: wb_mast_model.v,v 1.3 2001-11-29 02:17:36 rudi Exp $`
41	4	rudi	`//`
42	16	rudi	`// $Date: 2001-11-29 02:17:36 $`
43			`// $Revision: 1.3 $`
44	4	rudi	`// $Author: rudi $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	16	rudi	`// Revision 1.2 2001/11/11 01:52:03 rudi`
51			`//`
52			`// Minor fixes to testbench ...`
53			`//`
54	14	rudi	`// Revision 1.1 2001/07/29 07:34:40 rudi`
55			`//`
56			`//`
57			`// 1) Changed Directory Structure`
58			`// 2) Fixed several minor bugs`
59			`//`
60	4	rudi	`// Revision 1.1.1.1 2001/05/13 09:36:33 rudi`
61			`// Created Directory Structure`
62			`//`
63			`//`
64			`//`
65			`//`
66			`//`
67
68			`include "wb_model_defines.v"
69
70			`module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);`
71
72			`input clk, rst;`
73			`output [31:0] adr;`
74			`input [31:0] din;`
75			`output [31:0] dout;`
76			`output cyc, stb;`
77			`output [3:0] sel;`
78			`output we;`
79			`input ack, err, rty;`
80
81			`////////////////////////////////////////////////////////////////////`
82			`//`
83			`// Local Wires`
84			`//`
85
86			`parameter mem_size = 4096;`
87
88			`reg [31:0] adr;`
89			`reg [31:0] dout;`
90			`reg cyc, stb;`
91			`reg [3:0] sel;`
92			`reg we;`
93
94			`reg [31:0] rd_mem[mem_size:0];`
95			`reg [31:0] wr_mem[mem_size:0];`
96			`integer rd_cnt;`
97			`integer wr_cnt;`
98
99			`////////////////////////////////////////////////////////////////////`
100			`//`
101			`// Memory Logic`
102			`//`
103
104			`initial`
105			`begin`
106			`//adr = 32'hxxxx_xxxx;`
107			`//adr = 0;`
108			`adr = 32'hffff_ffff;`
109			`dout = 32'hxxxx_xxxx;`
110			`cyc = 0;`
111			`stb = 0;`
112			`sel = 4'hx;`
113			`we = 1'hx;`
114			`rd_cnt = 0;`
115			`wr_cnt = 0;`
116			`#1;`
117			`$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");`
118			`end`
119
120
121
122			`task mem_fill;`
123
124			`integer n;`
125			`begin`
126			`rd_cnt = 0;`
127			`wr_cnt = 0;`
128			`for(n=0;n<mem_size;n=n+1)`
129			`begin`
130			`rd_mem[n] = $random;`
131			`wr_mem[n] = $random;`
132			`end`
133			`end`
134			`endtask`
135
136			`////////////////////////////////////////////////////////////////////`
137			`//`
138			`// Write 1 Word Task`
139			`//`
140
141			`task wb_wr1;`
142			`input [31:0] a;`
143			`input [3:0] s;`
144			`input [31:0] d;`
145
146			`begin`
147
148	14	rudi	`//@(posedge clk);`
149	4	rudi	`#1;`
150			`adr = a;`
151			`dout = d;`
152			`cyc = 1;`
153			`stb = 1;`
154			`we=1;`
155			`sel = s;`
156
157			`@(posedge clk);`
158			`while(~ack & ~err) @(posedge clk);`
159			`#1;`
160			`cyc=0;`
161			`stb=0;`
162			`adr = 32'hxxxx_xxxx;`
163			`//adr = 32'hffff_ffff;`
164			`//adr = 0;`
165			`dout = 32'hxxxx_xxxx;`
166			`we = 1'hx;`
167			`sel = 4'hx;`
168
169			`end`
170			`endtask`
171
172			`////////////////////////////////////////////////////////////////////`
173			`//`
174			`// Write 4 Words Task`
175			`//`
176
177			`task wb_wr4;`
178			`input [31:0] a;`
179			`input [3:0] s;`
180			`input delay;`
181			`input [31:0] d1;`
182			`input [31:0] d2;`
183			`input [31:0] d3;`
184			`input [31:0] d4;`
185
186			`integer delay;`
187
188			`begin`
189
190			`@(posedge clk);`
191			`#1;`
192			`cyc = 1;`
193			`sel = s;`
194
195			`repeat(delay)`
196			`begin`
197			`@(posedge clk);`
198			`#1;`
199			`end`
200			`adr = a;`
201			`dout = d1;`
202			`stb = 1;`
203			`we=1;`
204			`while(~ack & ~err) @(posedge clk);`
205			`#2;`
206			`stb=0;`
207			`we=1'bx;`
208			`dout = 32'hxxxx_xxxx;`
209
210
211			`repeat(delay)`
212			`begin`
213			`@(posedge clk);`
214			`#1;`
215			`end`
216			`stb=1;`
217			`adr = a+4;`
218			`dout = d2;`
219			`we=1;`
220			`@(posedge clk);`
221			`while(~ack & ~err) @(posedge clk);`
222			`#2;`
223			`stb=0;`
224			`we=1'bx;`
225			`dout = 32'hxxxx_xxxx;`
226
227			`repeat(delay)`
228			`begin`
229			`@(posedge clk);`
230			`#1;`
231			`end`
232			`stb=1;`
233			`adr = a+8;`
234			`dout = d3;`
235			`we=1;`
236			`@(posedge clk);`
237			`while(~ack & ~err) @(posedge clk);`
238			`#2;`
239			`stb=0;`
240			`we=1'bx;`
241			`dout = 32'hxxxx_xxxx;`
242
243			`repeat(delay)`
244			`begin`
245			`@(posedge clk);`
246			`#1;`
247			`end`
248			`stb=1;`
249			`adr = a+12;`
250			`dout = d4;`
251			`we=1;`
252			`@(posedge clk);`
253			`while(~ack & ~err) @(posedge clk);`
254			`#1;`
255			`stb=0;`
256			`cyc=0;`
257
258			`adr = 32'hxxxx_xxxx;`
259			`//adr = 0;`
260			`//adr = 32'hffff_ffff;`
261			`dout = 32'hxxxx_xxxx;`
262			`we = 1'hx;`
263			`sel = 4'hx;`
264
265			`end`
266			`endtask`
267
268
269			`task wb_wr_mult;`
270			`input [31:0] a;`
271			`input [3:0] s;`
272			`input delay;`
273			`input count;`
274
275			`integer delay;`
276			`integer count;`
277			`integer n;`
278
279			`begin`
280
281			`@(posedge clk);`
282			`#1;`
283			`cyc = 1;`
284
285			`for(n=0;n<count;n=n+1)`
286			`begin`
287			`repeat(delay)`
288			`begin`
289			`@(posedge clk);`
290			`#1;`
291			`end`
292			`adr = a + (n*4);`
293			`dout = wr_mem[n + wr_cnt];`
294			`stb = 1;`
295			`we=1;`
296			`sel = s;`
297			`if(n!=0) @(posedge clk);`
298			`while(~ack & ~err) @(posedge clk);`
299			`#2;`
300			`stb=0;`
301			`we=1'bx;`
302			`sel = 4'hx;`
303			`dout = 32'hxxxx_xxxx;`
304			`adr = 32'hxxxx_xxxx;`
305			`end`
306
307			`cyc=0;`
308
309			`adr = 32'hxxxx_xxxx;`
310			`//adr = 32'hffff_ffff;`
311
312			`wr_cnt = wr_cnt + count;`
313			`end`
314			`endtask`
315
316
317			`task wb_rmw;`
318			`input [31:0] a;`
319			`input [3:0] s;`
320			`input delay;`
321			`input rcount;`
322			`input wcount;`
323
324			`integer delay;`
325			`integer rcount;`
326			`integer wcount;`
327	16	rudi
328			`begin`
329			`wb_rmw2(a,a,s,delay,rcount,wcount);`
330			`end`
331			`endtask`
332
333
334			`task wb_rmw2;`
335			`input [31:0] ra;`
336			`input [31:0] wa;`
337			`input [3:0] s;`
338			`input delay;`
339			`input rcount;`
340			`input wcount;`
341
342			`integer delay;`
343			`integer rcount;`
344			`integer wcount;`
345	4	rudi	`integer n;`
346
347			`begin`
348
349	16	rudi	`//@(posedge clk);`
350	4	rudi	`#1;`
351			`cyc = 1;`
352			`we = 0;`
353			`sel = s;`
354			`repeat(delay) @(posedge clk);`
355
356			`for(n=0;n<rcount-1;n=n+1)`
357			`begin`
358	16	rudi	`adr = ra + (n*4);`
359	4	rudi	`stb = 1;`
360			`while(~ack & ~err) @(posedge clk);`
361			`rd_mem[n + rd_cnt] = din;`
362			`//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );`
363			`#2;`
364			`stb=0;`
365			`we = 1'hx;`
366			`sel = 4'hx;`
367			`adr = 32'hxxxx_xxxx;`
368			`repeat(delay)`
369			`begin`
370			`@(posedge clk);`
371			`#1;`
372			`end`
373			`we = 0;`
374			`sel = s;`
375			`end`
376
377	16	rudi	`adr = ra+(n*4);`
378	4	rudi	`stb = 1;`
379			`@(posedge clk);`
380			`while(~ack & ~err) @(posedge clk);`
381			`rd_mem[n + rd_cnt] = din;`
382			`//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );`
383			`#1;`
384			`stb=0;`
385			`we = 1'hx;`
386			`sel = 4'hx;`
387			`adr = 32'hxxxx_xxxx;`
388
389			`rd_cnt = rd_cnt + rcount;`
390
391			`//@(posedge clk);`
392
393
394			`for(n=0;n<wcount;n=n+1)`
395			`begin`
396			`repeat(delay)`
397			`begin`
398			`@(posedge clk);`
399			`#1;`
400			`end`
401	16	rudi	`adr = wa + (n*4);`
402	4	rudi	`dout = wr_mem[n + wr_cnt];`
403			`stb = 1;`
404			`we=1;`
405			`sel = s;`
406			`// if(n!=0)`
407			`@(posedge clk);`
408			`while(~ack & ~err) @(posedge clk);`
409			`#2;`
410			`stb=0;`
411			`we=1'bx;`
412			`sel = 4'hx;`
413			`dout = 32'hxxxx_xxxx;`
414			`adr = 32'hxxxx_xxxx;`
415			`end`
416
417			`cyc=0;`
418
419			`adr = 32'hxxxx_xxxx;`
420			`//adr = 32'hffff_ffff;`
421
422			`wr_cnt = wr_cnt + wcount;`
423			`end`
424			`endtask`
425
426
427
428
429			`task wb_wmr;`
430			`input [31:0] a;`
431			`input [3:0] s;`
432			`input delay;`
433			`input rcount;`
434			`input wcount;`
435
436			`integer delay;`
437			`integer rcount;`
438			`integer wcount;`
439			`integer n;`
440
441			`begin`
442
443	16	rudi	`//@(posedge clk);`
444	4	rudi	`#1;`
445			`cyc = 1;`
446			`we = 1'bx;`
447			`sel = 4'hx;`
448			`sel = s;`
449
450			`for(n=0;n<wcount;n=n+1)`
451			`begin`
452			`repeat(delay)`
453			`begin`
454			`@(posedge clk);`
455			`#1;`
456			`end`
457			`adr = a + (n*4);`
458			`dout = wr_mem[n + wr_cnt];`
459			`stb = 1;`
460			`we=1;`
461			`sel = s;`
462			`@(posedge clk);`
463			`while(~ack & ~err) @(posedge clk);`
464			`#2;`
465			`stb=0;`
466			`we=1'bx;`
467			`sel = 4'hx;`
468			`dout = 32'hxxxx_xxxx;`
469			`adr = 32'hxxxx_xxxx;`
470			`end`
471
472			`wr_cnt = wr_cnt + wcount;`
473			`stb=0;`
474			`repeat(delay) @(posedge clk);`
475			`#1;`
476
477			`sel = s;`
478			`we = 0;`
479			`for(n=0;n<rcount-1;n=n+1)`
480			`begin`
481			`adr = a + (n*4);`
482			`stb = 1;`
483			`while(~ack & ~err) @(posedge clk);`
484			`rd_mem[n + rd_cnt] = din;`
485			`//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );`
486			`#2;`
487			`stb=0;`
488			`we = 1'hx;`
489			`sel = 4'hx;`
490			`adr = 32'hxxxx_xxxx;`
491			`repeat(delay)`
492			`begin`
493			`@(posedge clk);`
494			`#1;`
495			`end`
496			`we = 0;`
497			`sel = s;`
498			`end`
499
500			`adr = a+(n*4);`
501			`stb = 1;`
502			`@(posedge clk);`
503			`while(~ack & ~err) @(posedge clk);`
504			`rd_mem[n + rd_cnt] = din;`
505			`rd_cnt = rd_cnt + rcount;`
506			`//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );`
507			`#1;`
508
509			`cyc = 0;`
510			`stb = 0;`
511			`we = 1'hx;`
512			`sel = 4'hx;`
513			`adr = 32'hxxxx_xxxx;`
514
515			`end`
516			`endtask`
517
518
519
520
521			`////////////////////////////////////////////////////////////////////`
522			`//`
523			`// Read 1 Word Task`
524			`//`
525
526			`task wb_rd1;`
527			`input [31:0] a;`
528			`input [3:0] s;`
529			`output [31:0] d;`
530
531			`begin`
532
533	14	rudi	`//@(posedge clk);`
534	4	rudi	`#1;`
535			`adr = a;`
536			`cyc = 1;`
537			`stb = 1;`
538			`we = 0;`
539			`sel = s;`
540
541			`//@(posedge clk);`
542			`while(~ack & ~err) @(posedge clk);`
543			`d = din;`
544			`#1;`
545			`cyc=0;`
546			`stb=0;`
547			`//adr = 32'hxxxx_xxxx;`
548			`//adr = 0;`
549			`adr = 32'hffff_ffff;`
550			`dout = 32'hxxxx_xxxx;`
551			`we = 1'hx;`
552			`sel = 4'hx;`
553
554			`end`
555			`endtask`
556
557
558			`////////////////////////////////////////////////////////////////////`
559			`//`
560			`// Read 4 Words Task`
561			`//`
562
563
564			`task wb_rd4;`
565			`input [31:0] a;`
566			`input [3:0] s;`
567			`input delay;`
568			`output [31:0] d1;`
569			`output [31:0] d2;`
570			`output [31:0] d3;`
571			`output [31:0] d4;`
572
573			`integer delay;`
574			`begin`
575
576			`@(posedge clk);`
577			`#1;`
578			`cyc = 1;`
579			`we = 0;`
580			`sel = s;`
581			`repeat(delay) @(posedge clk);`
582
583			`adr = a;`
584			`stb = 1;`
585			`while(~ack & ~err) @(posedge clk);`
586			`d1 = din;`
587			`#2;`
588			`stb=0;`
589			`we = 1'hx;`
590			`sel = 4'hx;`
591			`repeat(delay)`
592			`begin`
593			`@(posedge clk);`
594			`#1;`
595			`end`
596			`we = 0;`
597			`sel = s;`
598
599			`adr = a+4;`
600			`stb = 1;`
601			`@(posedge clk);`
602			`while(~ack & ~err) @(posedge clk);`
603			`d2 = din;`
604			`#2;`
605			`stb=0;`
606			`we = 1'hx;`
607			`sel = 4'hx;`
608			`repeat(delay)`
609			`begin`
610			`@(posedge clk);`
611			`#1;`
612			`end`
613			`we = 0;`
614			`sel = s;`
615
616
617			`adr = a+8;`
618			`stb = 1;`
619			`@(posedge clk);`
620			`while(~ack & ~err) @(posedge clk);`
621			`d3 = din;`
622			`#2;`
623			`stb=0;`
624			`we = 1'hx;`
625			`sel = 4'hx;`
626			`repeat(delay)`
627			`begin`
628			`@(posedge clk);`
629			`#1;`
630			`end`
631			`we = 0;`
632			`sel = s;`
633
634			`adr = a+12;`
635			`stb = 1;`
636			`@(posedge clk);`
637			`while(~ack & ~err) @(posedge clk);`
638			`d4 = din;`
639			`#1;`
640			`stb=0;`
641			`cyc=0;`
642			`we = 1'hx;`
643			`sel = 4'hx;`
644			`adr = 32'hffff_ffff;`
645			`end`
646			`endtask`
647
648
649
650			`task wb_rd_mult;`
651			`input [31:0] a;`
652			`input [3:0] s;`
653			`input delay;`
654			`input count;`
655
656			`integer delay;`
657			`integer count;`
658			`integer n;`
659
660			`begin`
661
662			`@(posedge clk);`
663			`#1;`
664			`cyc = 1;`
665			`we = 0;`
666			`sel = s;`
667			`repeat(delay) @(posedge clk);`
668
669			`for(n=0;n<count-1;n=n+1)`
670			`begin`
671			`adr = a + (n*4);`
672			`stb = 1;`
673			`while(~ack & ~err) @(posedge clk);`
674			`rd_mem[n + rd_cnt] = din;`
675			`#2;`
676			`stb=0;`
677			`we = 1'hx;`
678			`sel = 4'hx;`
679			`adr = 32'hxxxx_xxxx;`
680			`repeat(delay)`
681			`begin`
682			`@(posedge clk);`
683			`#1;`
684			`end`
685			`we = 0;`
686			`sel = s;`
687			`end`
688
689			`adr = a+(n*4);`
690			`stb = 1;`
691			`@(posedge clk);`
692			`while(~ack & ~err) @(posedge clk);`
693			`rd_mem[n + rd_cnt] = din;`
694			`#1;`
695			`stb=0;`
696			`cyc=0;`
697			`we = 1'hx;`
698			`sel = 4'hx;`
699			`adr = 32'hffff_ffff;`
700			`adr = 32'hxxxx_xxxx;`
701
702			`rd_cnt = rd_cnt + count;`
703			`end`
704			`endtask`
705
706			`endmodule`