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[/] [mem_ctrl/] [trunk/] [bench/] [vhdl/] [8Kx8_vhdl.vhd] - Blame information for rev 28

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--********************************************************************
--********************************************************************
--** This model is the property of Cypress Semiconductor Corp. and  **
--** is protected by the US copyright laws, any unauthorized copying** 
--** and distribution is prohibited. Cypress reserves the right to  **
--** change any of the functional specifications without any prior  **
--** notice. Cypress is not liable for any damages which may result **
--** from the use of this functional model.                         ** 
--**                                                                **
--** File Name: 8KX8.vhd                                            **
--**                                                                **
--** Revision : 1.0                                                 **
--**                                                                **
--** All the timings to be assigned by the user depending on the    **
--** frequency of operation.                                        **
--**                                                                ** 
--** Model    : 8K x 8 Asynchronous SRAM                            **   
--**                                                                **
--** Queries ?: MPD Applications                                    **
--**            Ph#: (408)-943-2821                                 **
--**            e-mail: mpd_apps@cypress.com                        **
--********************************************************************
--******************************************************************** 
 
Library IEEE;
Use IEEE.Std_Logic_1164.All;
use IEEE.Std_Logic_Signed.All;
 
-- Entity Description for 8K x 8
 
Entity A8Kx8 Is
 Generic (Trc  :   TIME    :=   0 ns;
          Taa  :   TIME    :=   0 ns;
          Toha :   TIME    :=   0 ns;
          Tace :   TIME    :=   0 ns;
          Tdoe :   TIME    :=   0 ns;
          Thzoe:   TIME    :=   0 ns;
          Thzce:   TIME    :=   0 ns;
          Twc  :   TIME    :=   0 ns;
          Tsce :   TIME    :=   0 ns;
          Taw  :   TIME    :=   0 ns;
          Tha  :   TIME    :=   0 ns;
          Tsa  :   TIME    :=   0 ns;
          Tpwe :   TIME    :=   0 ns;
          Tsd  :   TIME    :=   0 ns;
          Thd  :   TIME    :=   0 ns);
 
Port ( CE_b, WE_b, OE_n : IN Std_Logic;
         A : IN Std_Logic_Vector(12 downto 0);
        IO : INOUT Std_Logic_Vector(7 downto 0):=(others=>'Z'));
 
End A8Kx8;
 
-- End Entity Description
 
-- Architecture Description of entity A8Kx8
 
Architecture Behavioral Of A8Kx8 Is
 
   Type array1 Is array (8191 downto 0) of std_logic_vector(7 downto 0);
   Signal rd, wr, oe, ce, we, ce_pipe, we_pipe, r_chk : Std_logic;
   Signal we_chk, ce_chk, wr_sa, wr_sa1 : Std_logic;
   Signal address, A_adr, prev_addr, addr : Std_Logic_Vector(12 downto 0);
   Signal io_reg, io_val : Std_Logic_Vector(7 downto 0);
 
Begin
 
  ce <=  CE_b;
  oe <=  OE_n;
  we <=  WE_b;
  wr <= (NOT CE_b) and (NOT WE_b);
  rd <= (NOT CE_b) and (NOT OE_n) and WE_b;
  io_reg <= IO;
  address(12 downto 0) <= A(12 downto 0);
 
-- Process Description for the write and read cycle 
 
  PROCESS (ce, wr, A, we, oe, io_reg, IO)
 
   VARIABLE mem_array1: array1;
   VARIABLE Troe, Trce, Tro, Trc, Thdrd, Tprev, Tiopr, Tsa1 : Time;
   VARIABLE z : Time := 0 ns;
   VARIABLE wrt, ce_end, wr_end, oe_end, io_end, add_end, A_event_rd : Std_logic ;
 
   begin
 
--- Assign signals and variables for time checks before reading or writing.
 
   ce_pipe <= ce;
   wr_sa <= wr;
 
   if (ce'event and ce'last_value = '0') then
    ce_end := '1';
   else
    ce_end := '0';
   end if;
 
   if (wr'event and wr'last_value = '1') then
    wr_end := '1';
   else
    wr_end := '0';
   end if;
 
   if (io_reg(7 downto 0)'event) then
    io_end := '1';
   else
    io_end := '0';
   end if;
 
   if (oe'event and oe'last_value = '0') then
    oe_end := '1';
   else
    oe_end := '0';
   end if;
 
------ Storing the last event and previous address when address transitions 
------ along with write end.
 
   if (A'event) then
   prev_addr(12 downto 0)  <= address(12 downto 0);
 
   end if;
 
   if (address'event) then
   Add_end := '1';
   else
   Add_end := '0';
   end if;
 
   if (A'event) then
   Tprev := address'last_event;
   end if;
 
 
------ Storing the address setup to write start time for performing the check 
------ before the write.
 
   if (wr_end = '1' and Add_end = '1') then
   Tsa1 := Tprev - wr_sa'last_event;
   elsif (wr_end = '1' and Add_end = '0') then
   Tsa1 := A'last_event -  wr_sa'last_event;
   end if;
 
----- Reading or writing occurs only when CE low or CE has transitioned 
----- from low to high.
 
   if ((CE_b = '0') or (ce_end = '1' and wr_end = '1') or (ce_end = '1')) then
 
      we_pipe <= we;
 
      wrt := '0';
      if  (wr'event and wr'last_value = '1') then
      wrt := '1';
      else
      wrt:= '0';
      end if;
 
------------------------------------------------------------------------------------------------
----- WRITE CYCLE
 
----- Storing the previous value of higher order data bits and storing last event
----- of data for data setup time check if data changes along with the write end transition.
 
      if (io_reg'event) then
      io_val <= io_reg;
      end if;
 
      if (IO'event) then
      Tiopr := io_reg'last_event;
      end if;
 
----- Write the higher order byte after checking for the necessary
----- timings - Tsa, Tpwe, Tsce, Tbw, Taw, Tsd. 
 
       if (wrt = '1') then
         if (we_pipe'last_event >= Tpwe) and (ce_pipe'last_event >= Tsce) and (Tsa1 >= Tsa) then
           if (Add_end = '1') then
             if (Tprev >= Taw) then
               if (io_end = '1') then
                 if (Tiopr > Tsd) then
                  mem_array1(conv_integer(prev_addr)) := io_val;
                 end if;
               else
                 if (IO'last_event >= Tsd) then
                 mem_array1(conv_integer(prev_addr)) := IO(7 downto 0);
                 end if;
               end if;
             end if;
           else
              if (A'last_event >= Taw) then
                if (io_end = '1') then
                  if (Tiopr >= Tsd) then
                   mem_array1(conv_integer(A)) := io_val;
                  end if;
                else
                  if (IO'last_event >= Tsd) then
                   mem_array1(conv_integer(A)) := IO(7 downto 0);
                  end if;
                end if;
              end if;
           end if;
              IO(7 downto 0) <= "ZZZZZZZZ" AFTER Thd;
        end if;
      end if;                               ----- End of write.
 
 
 
----------------------------------------------------------------------------------------------------
----- READ CYCLE.
 
    if (A'event) then
     A_event_rd := '1';
    else
     A_event_rd := '0';
    end if;
 
 
    if (rd'event and rd = '1') then
 
------ Determine the read initiation to data valid time.
 
      Tro := OE_n'last_event;
      Troe := Tdoe-Tro;
      if (Troe < 0 ns) then
        Troe := 0 ns;
      end if;
 
      Trc := 0 ns;
      Trc := CE_b'last_event;
      Trce := Tace-Trc;
      If (Trce < 0 ns) then
        Trce := 0 ns;
      end if;
 
      if (Troe > Trce) then
       if (rd = '1') then
       z := Troe;
       end if;
      else
       if (rd = '1') then
       z := Trce;
       end if;
      end if;
 
       if (address'last_event+z) < Taa then
       z := Taa;
       end if;
      end if;
 
  end if;
 
 
      if (A_event_rd = '0') then
         if (rd'event and rd = '1') then
          IO(7 downto 0) <= mem_array1(conv_integer(A)) after z;
         end if;
      elsif (A_event_rd = '1') then
         if (rd'event and rd = '1') then
          IO(7 downto 0) <= mem_array1(conv_integer(A)) after z;
         elsif (rd = '1') then
          IO(7 downto 0) <= mem_array1(conv_integer(A)) after Taa;
         end if;
      end if;                                                   ------- End of Read
 
 
------ Determine read end to High Z time.
 
------ Higher order bits read. The time is calculated as per which signal(s) terrminates
------ the read.
 
       if (rd'event and rd = '0') then
 
          if (oe_end = '1' and ce_end = '1') then
             Thdrd := Thzoe;
             if (Thdrd < Thzce) then
              Thdrd := Thzce;
             end if;
          else
             if (ce_end = '1') then
              Thdrd := Thzce;
             end if;
 
             if (oe_end = '1') then
              Thdrd := Thzoe;
             end if;
          end if;
 
          if (Thdrd < 0 ns) then
           Thdrd := 0 ns;
          end if;
 
         IO(7 downto 0) <= (others=>'Z') after Thdrd;
 
  end if;
 
 END PROCESS;
 
 
------ Read Cycle (Trc) and Write Cycle (Twc) time checks.
 
Process (A, address, wr, rd)
 
variable A_evnt, A_wr, A_rd, r1 : Std_logic;
variable Trd, Tadr : Time;
 
 Begin
 
   r_chk <= rd;
 
   if (A'event) then
   A_adr(12 downto 0)  <= address(12 downto 0);
   end if;
 
   if (A'event) then
   Tadr := A_adr(12 downto 0)'last_event;
   end if;
 
   if (wr'event and wr'last_value = '1') then
     A_wr := '1';
   end if;
 
   if (rd'event and rd'last_value = '1') then
     A_rd := '1';
     Trd := r_chk'last_event;
   end if;
 
   if address'event then
     A_evnt := '1';
   else
     A_evnt := '0';
   end if;
 
 
      if (rd'event and rd'last_value = '1') then
        if (A_evnt = '1') then
        r1 := '1';
        ASSERT (Trd >= Trc) or (A_adr'LAST_EVENT >= Trc)
        REPORT "READ CYCLE TIME VIOLATION"
        SEVERITY Error;
        elsif (A_evnt = '0') then
        r1 := '0';
        ASSERT (Trd >= Trc) or (A'LAST_EVENT >= Trc)
        REPORT "READ CYCLE TIME VIOLATION"
        SEVERITY Error;
        end if;
      end if;
 
      if (A_evnt = '1') then
       if (rd'event and rd'last_value = '1') then
        r1 := '0';
       elsif rd = '1' then
        ASSERT (A_adr'LAST_EVENT >= Trc) or (Trd >= Trc)
        REPORT "READ CYCLE TIME VIOLATION"
        SEVERITY Error;
      end if;
 
      if (wr'event and wr'last_value = '1') then
        ASSERT (Tadr >= Twc)
        REPORT "WRITE CYCLE TIME VIOLATION"
        SEVERITY Error;
      elsif A_wr = '1' then
        ASSERT (Tadr >= Twc)
        REPORT "WRITE CYCLE TIME VIOLATION"
        SEVERITY Error;
      end if;
 
   A_wr := '0';
   A_rd := '0';
   end if;
 
 End Process;
 
 
------ Checks for Tsce, Taw, Tsa, Tpwe, Tsd and Tbw.     
 
 Process (ce, wr, WE_b, A, IO)
 
 VARIABLE wr_end_chk, A_end : Std_logic := '0';
 VARIABLE Taw_chk, Tsd_chk, Tsa_chk : Time;
 
 begin
 
   ce_chk <= ce;
   we_chk <= we;
   addr(12 downto 0) <= address(12 downto 0);
   wr_sa1 <= wr;
 
   wr_end_chk := '0';
   if (wr'event and wr'last_value = '1') then
    wr_end_chk := '1';
   else
    wr_end_chk := '0';
   end if;
 
   A_end := '0';
   if (address'event) and (wr_end_chk = '1') then
    A_end := '1';
   else
    A_end := '0';
   end if;
 
   if (A'event) then
    Taw_chk := address'last_event;
   end if;
 
   if (IO'event) then
    Tsd_chk := io_reg'last_event;
   end if;
 
   if (wr_end_chk = '1' and A_end = '1') then
   Tsa_chk := Taw_chk - wr_sa1'last_event;
   elsif (wr_end_chk = '1' and A_end = '0') then
   Tsa_chk := A'last_event -  wr_sa1'last_event;
   end if;
 
      if wr_end_chk = '1' then
 
          ASSERT (ce_chk'LAST_EVENT >= Tsce)
          REPORT "CE LOW TO WRITE END TIME VIOLATION"
          SEVERITY Error;
 
          if (we'event) then
          ASSERT (we_chk'LAST_EVENT >= Tpwe)
          REPORT "WE PULSE WIDTH TIME VIOLATION"
          SEVERITY Error;
          else
          ASSERT (WE_b'LAST_EVENT >= Tpwe)
          REPORT "WE PULSE WIDTH TIME VIOLATION"
          SEVERITY Error;
          end if;
 
          if (A_end = '1') then
          ASSERT (Taw_chk >= Taw)
          REPORT "ADDRESS SETUP TO WRITE END TIME VIOLATION"
          SEVERITY Error;
          else
          ASSERT (A'LAST_EVENT >= Taw)
          REPORT "ADDRESS SETUP TO WRITE END TIME VIOLATION"
          SEVERITY Error;
          end if;
 
          if (io_reg'event) then
           ASSERT (Tsd_chk >= Tsd)
           REPORT "DATA SETUP TO WRITE END TIME VIOLATION"
           SEVERITY Error;
          else
           ASSERT (IO'LAST_EVENT >= Tsd)
           REPORT "DATA SETUP TO WRITE END TIME VIOLATION"
           SEVERITY Error;
          end if;
 
          ASSERT (Tsa_chk >= Tsa) or (Tsa_chk < 0 ns)
          REPORT "ADDRESS SETUP TO WRITE START TIME VIOLATION"
          SEVERITY Error;
      end if;
 
   end Process;
 
----- Address Hold (Tha) and Data Hold (Thd) time checks on write.
 
   Process (wr'delayed(Thd), wr'delayed(Tha), A, IO)
 
    begin
 
     if (wr'delayed(Thd) = '0' and wr'delayed(Thd)'last_value = '1') and (wr'delayed(Thd)'event) then
 
         ASSERT (IO'LAST_EVENT = 0 ns) or (IO'LAST_EVENT > Thd)
         REPORT "DATA HOLD FROM WRITE END TIME VIOLATION"
         SEVERITY Error;
 
     end if;
 
     if (wr'delayed(Tha) = '0' and wr'delayed(Tha)'last_value = '1') and (wr'delayed(Tha)'event) then
 
         ASSERT (A'LAST_EVENT = 0 ns) or (A'LAST_EVENT > Tha)
         REPORT "ADDRESS HOLD FROM WRITE END TIME VIOLATION"
         SEVERITY Error;
 
     end if;
 
   End Process;
 
---- Tdoe, Tdbe, Tace, Taa and Toha time checks on read.
 
Process (IO, A'delayed(Toha))
    begin
 
      if ((IO'event) and (rd = '1')) then
 
          if (rd'last_event <= A'last_event) then
           ASSERT (OE_n'LAST_EVENT >= Tdoe)
           REPORT "OE LOW TO DATA VALID TIME VIOLATION"
           SEVERITY Error;
 
           ASSERT (CE_b'LAST_EVENT >= Tace)
           REPORT "CE LOW TO DATA VALID TIME VIOLATION"
           SEVERITY Error;
          end if;
 
          if (rd'last_event > A'last_event) then
           ASSERT (A'LAST_EVENT >= Taa)
           REPORT "ADDRESS TO DATA VALID TIME VIOLATION"
           SEVERITY Error;
          end if;
 
      end if;
 
     if (A'delayed(Toha)'event and (rd = '1')) then
 
      if (rd'last_event > Toha) then
         ASSERT (IO'LAST_EVENT = 0 ns) or (IO'LAST_EVENT > Toha)
         REPORT "DATA HOLD FROM ADDRESS CHANGE TIME VIOLATION"
         SEVERITY Error;
      end if;
 
    end if;
 
End Process;
 
------ Thzbe, Thzoe and Thzce time checks.
 
Process (OE_n'delayed(Thzoe), CE_b'delayed(Thzce))
   begin
 
   if (OE_n'delayed(Thzoe)'event and OE_n'delayed'last_value = '0' and OE_n'delayed(Thzoe) = '1') then
 
       ASSERT (IO'LAST_EVENT = 0 ns) or (IO'LAST_EVENT > Thzoe)
       REPORT "OE DISABLE TO HIGH Z TIME VIOLATION"
       SEVERITY Error;
 
   end if;
 
   if (CE_b'delayed(Thzce)'event and CE_b'delayed'last_value = '0' and CE_b'delayed(Thzce) = '1') then
 
       ASSERT (IO'LAST_EVENT = 0 ns) or (IO'LAST_EVENT > Thzce)
       REPORT "CE DISABLE TO HIGH Z TIME VIOLATION"
       SEVERITY Error;
 
   end if;
 
End Process;
End Behavioral;
 

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Subversion Repositories mem_ctrl

[/] [mem_ctrl/] [trunk/] [bench/] [vhdl/] [8Kx8_vhdl.vhd] - Blame information for rev 28

Line No.	Rev	Author	Line
1	4	rudi	`--********************************************************************`
2			`--********************************************************************`
3			`-- This model is the property of Cypress Semiconductor Corp. and `
4			`-- is protected by the US copyright laws, any unauthorized copying`
5			`-- and distribution is prohibited. Cypress reserves the right to `
6			`-- change any of the functional specifications without any prior `
7			`-- notice. Cypress is not liable for any damages which may result `
8			`-- from the use of this functional model. `
9			`-- `
10			`-- File Name: 8KX8.vhd `
11			`-- `
12			`-- Revision : 1.0 `
13			`-- `
14			`-- All the timings to be assigned by the user depending on the `
15			`-- frequency of operation. `
16			`-- `
17			`-- Model : 8K x 8 Asynchronous SRAM `
18			`-- `
19			`-- Queries ?: MPD Applications `
20			`-- Ph#: (408)-943-2821 `
21			`-- e-mail: mpd_apps@cypress.com `
22			`--********************************************************************`
23			`--********************************************************************`
24
25			`Library IEEE;`
26			`Use IEEE.Std_Logic_1164.All;`
27			`use IEEE.Std_Logic_Signed.All;`
28
29			`-- Entity Description for 8K x 8`
30
31			`Entity A8Kx8 Is`
32			`Generic (Trc : TIME := 0 ns;`
33			`Taa : TIME := 0 ns;`
34			`Toha : TIME := 0 ns;`
35			`Tace : TIME := 0 ns;`
36			`Tdoe : TIME := 0 ns;`
37			`Thzoe: TIME := 0 ns;`
38			`Thzce: TIME := 0 ns;`
39			`Twc : TIME := 0 ns;`
40			`Tsce : TIME := 0 ns;`
41			`Taw : TIME := 0 ns;`
42			`Tha : TIME := 0 ns;`
43			`Tsa : TIME := 0 ns;`
44			`Tpwe : TIME := 0 ns;`
45			`Tsd : TIME := 0 ns;`
46			`Thd : TIME := 0 ns);`
47
48			`Port ( CE_b, WE_b, OE_n : IN Std_Logic;`
49			`A : IN Std_Logic_Vector(12 downto 0);`
50			`IO : INOUT Std_Logic_Vector(7 downto 0):=(others=>'Z'));`
51
52			`End A8Kx8;`
53
54			`-- End Entity Description`
55
56			`-- Architecture Description of entity A8Kx8`
57
58			`Architecture Behavioral Of A8Kx8 Is`
59
60			`Type array1 Is array (8191 downto 0) of std_logic_vector(7 downto 0);`
61			`Signal rd, wr, oe, ce, we, ce_pipe, we_pipe, r_chk : Std_logic;`
62			`Signal we_chk, ce_chk, wr_sa, wr_sa1 : Std_logic;`
63			`Signal address, A_adr, prev_addr, addr : Std_Logic_Vector(12 downto 0);`
64			`Signal io_reg, io_val : Std_Logic_Vector(7 downto 0);`
65
66			`Begin`
67
68			`ce <= CE_b;`
69			`oe <= OE_n;`
70			`we <= WE_b;`
71			`wr <= (NOT CE_b) and (NOT WE_b);`
72			`rd <= (NOT CE_b) and (NOT OE_n) and WE_b;`
73			`io_reg <= IO;`
74			`address(12 downto 0) <= A(12 downto 0);`
75
76			`-- Process Description for the write and read cycle`
77
78			`PROCESS (ce, wr, A, we, oe, io_reg, IO)`
79
80			`VARIABLE mem_array1: array1;`
81			`VARIABLE Troe, Trce, Tro, Trc, Thdrd, Tprev, Tiopr, Tsa1 : Time;`
82			`VARIABLE z : Time := 0 ns;`
83			`VARIABLE wrt, ce_end, wr_end, oe_end, io_end, add_end, A_event_rd : Std_logic ;`
84
85			`begin`
86
87			`--- Assign signals and variables for time checks before reading or writing.`
88
89			`ce_pipe <= ce;`
90			`wr_sa <= wr;`
91
92			`if (ce'event and ce'last_value = '0') then`
93			`ce_end := '1';`
94			`else`
95			`ce_end := '0';`
96			`end if;`
97
98			`if (wr'event and wr'last_value = '1') then`
99			`wr_end := '1';`
100			`else`
101			`wr_end := '0';`
102			`end if;`
103
104			`if (io_reg(7 downto 0)'event) then`
105			`io_end := '1';`
106			`else`
107			`io_end := '0';`
108			`end if;`
109
110			`if (oe'event and oe'last_value = '0') then`
111			`oe_end := '1';`
112			`else`
113			`oe_end := '0';`
114			`end if;`
115
116			`------ Storing the last event and previous address when address transitions`
117			`------ along with write end.`
118
119			`if (A'event) then`
120			`prev_addr(12 downto 0) <= address(12 downto 0);`
121
122			`end if;`
123
124			`if (address'event) then`
125			`Add_end := '1';`
126			`else`
127			`Add_end := '0';`
128			`end if;`
129
130			`if (A'event) then`
131			`Tprev := address'last_event;`
132			`end if;`
133
134
135			`------ Storing the address setup to write start time for performing the check`
136			`------ before the write.`
137
138			`if (wr_end = '1' and Add_end = '1') then`
139			`Tsa1 := Tprev - wr_sa'last_event;`
140			`elsif (wr_end = '1' and Add_end = '0') then`
141			`Tsa1 := A'last_event - wr_sa'last_event;`
142			`end if;`
143
144			`----- Reading or writing occurs only when CE low or CE has transitioned`
145			`----- from low to high.`
146
147			`if ((CE_b = '0') or (ce_end = '1' and wr_end = '1') or (ce_end = '1')) then`
148
149			`we_pipe <= we;`
150
151			`wrt := '0';`
152			`if (wr'event and wr'last_value = '1') then`
153			`wrt := '1';`
154			`else`
155			`wrt:= '0';`
156			`end if;`
157
158			`------------------------------------------------------------------------------------------------`
159			`----- WRITE CYCLE`
160
161			`----- Storing the previous value of higher order data bits and storing last event`
162			`----- of data for data setup time check if data changes along with the write end transition.`
163
164			`if (io_reg'event) then`
165			`io_val <= io_reg;`
166			`end if;`
167
168			`if (IO'event) then`
169			`Tiopr := io_reg'last_event;`
170			`end if;`
171
172			`----- Write the higher order byte after checking for the necessary`
173			`----- timings - Tsa, Tpwe, Tsce, Tbw, Taw, Tsd.`
174
175			`if (wrt = '1') then`
176			`if (we_pipe'last_event >= Tpwe) and (ce_pipe'last_event >= Tsce) and (Tsa1 >= Tsa) then`
177			`if (Add_end = '1') then`
178			`if (Tprev >= Taw) then`
179			`if (io_end = '1') then`
180			`if (Tiopr > Tsd) then`
181			`mem_array1(conv_integer(prev_addr)) := io_val;`
182			`end if;`
183			`else`
184			`if (IO'last_event >= Tsd) then`
185			`mem_array1(conv_integer(prev_addr)) := IO(7 downto 0);`
186			`end if;`
187			`end if;`
188			`end if;`
189			`else`
190			`if (A'last_event >= Taw) then`
191			`if (io_end = '1') then`
192			`if (Tiopr >= Tsd) then`
193			`mem_array1(conv_integer(A)) := io_val;`
194			`end if;`
195			`else`
196			`if (IO'last_event >= Tsd) then`
197			`mem_array1(conv_integer(A)) := IO(7 downto 0);`
198			`end if;`
199			`end if;`
200			`end if;`
201			`end if;`
202			`IO(7 downto 0) <= "ZZZZZZZZ" AFTER Thd;`
203			`end if;`
204			`end if; ----- End of write.`
205
206
207
208			`----------------------------------------------------------------------------------------------------`
209			`----- READ CYCLE.`
210
211			`if (A'event) then`
212			`A_event_rd := '1';`
213			`else`
214			`A_event_rd := '0';`
215			`end if;`
216
217
218			`if (rd'event and rd = '1') then`
219
220			`------ Determine the read initiation to data valid time.`
221
222			`Tro := OE_n'last_event;`
223			`Troe := Tdoe-Tro;`
224			`if (Troe < 0 ns) then`
225			`Troe := 0 ns;`
226			`end if;`
227
228			`Trc := 0 ns;`
229			`Trc := CE_b'last_event;`
230			`Trce := Tace-Trc;`
231			`If (Trce < 0 ns) then`
232			`Trce := 0 ns;`
233			`end if;`
234
235			`if (Troe > Trce) then`
236			`if (rd = '1') then`
237			`z := Troe;`
238			`end if;`
239			`else`
240			`if (rd = '1') then`
241			`z := Trce;`
242			`end if;`
243			`end if;`
244
245			`if (address'last_event+z) < Taa then`
246			`z := Taa;`
247			`end if;`
248			`end if;`
249
250			`end if;`
251
252
253			`if (A_event_rd = '0') then`
254			`if (rd'event and rd = '1') then`
255			`IO(7 downto 0) <= mem_array1(conv_integer(A)) after z;`
256			`end if;`
257			`elsif (A_event_rd = '1') then`
258			`if (rd'event and rd = '1') then`
259			`IO(7 downto 0) <= mem_array1(conv_integer(A)) after z;`
260			`elsif (rd = '1') then`
261			`IO(7 downto 0) <= mem_array1(conv_integer(A)) after Taa;`
262			`end if;`
263			`end if; ------- End of Read`
264
265
266			`------ Determine read end to High Z time.`
267
268			`------ Higher order bits read. The time is calculated as per which signal(s) terrminates`
269			`------ the read.`
270
271			`if (rd'event and rd = '0') then`
272
273			`if (oe_end = '1' and ce_end = '1') then`
274			`Thdrd := Thzoe;`
275			`if (Thdrd < Thzce) then`
276			`Thdrd := Thzce;`
277			`end if;`
278			`else`
279			`if (ce_end = '1') then`
280			`Thdrd := Thzce;`
281			`end if;`
282
283			`if (oe_end = '1') then`
284			`Thdrd := Thzoe;`
285			`end if;`
286			`end if;`
287
288			`if (Thdrd < 0 ns) then`
289			`Thdrd := 0 ns;`
290			`end if;`
291
292			`IO(7 downto 0) <= (others=>'Z') after Thdrd;`
293
294			`end if;`
295
296			`END PROCESS;`
297
298
299			`------ Read Cycle (Trc) and Write Cycle (Twc) time checks.`
300
301			`Process (A, address, wr, rd)`
302
303			`variable A_evnt, A_wr, A_rd, r1 : Std_logic;`
304			`variable Trd, Tadr : Time;`
305
306			`Begin`
307
308			`r_chk <= rd;`
309
310			`if (A'event) then`
311			`A_adr(12 downto 0) <= address(12 downto 0);`
312			`end if;`
313
314			`if (A'event) then`
315			`Tadr := A_adr(12 downto 0)'last_event;`
316			`end if;`
317
318			`if (wr'event and wr'last_value = '1') then`
319			`A_wr := '1';`
320			`end if;`
321
322			`if (rd'event and rd'last_value = '1') then`
323			`A_rd := '1';`
324			`Trd := r_chk'last_event;`
325			`end if;`
326
327			`if address'event then`
328			`A_evnt := '1';`
329			`else`
330			`A_evnt := '0';`
331			`end if;`
332
333
334			`if (rd'event and rd'last_value = '1') then`
335			`if (A_evnt = '1') then`
336			`r1 := '1';`
337			`ASSERT (Trd >= Trc) or (A_adr'LAST_EVENT >= Trc)`
338			`REPORT "READ CYCLE TIME VIOLATION"`
339			`SEVERITY Error;`
340			`elsif (A_evnt = '0') then`
341			`r1 := '0';`
342			`ASSERT (Trd >= Trc) or (A'LAST_EVENT >= Trc)`
343			`REPORT "READ CYCLE TIME VIOLATION"`
344			`SEVERITY Error;`
345			`end if;`
346			`end if;`
347
348			`if (A_evnt = '1') then`
349			`if (rd'event and rd'last_value = '1') then`
350			`r1 := '0';`
351			`elsif rd = '1' then`
352			`ASSERT (A_adr'LAST_EVENT >= Trc) or (Trd >= Trc)`
353			`REPORT "READ CYCLE TIME VIOLATION"`
354			`SEVERITY Error;`
355			`end if;`
356
357			`if (wr'event and wr'last_value = '1') then`
358			`ASSERT (Tadr >= Twc)`
359			`REPORT "WRITE CYCLE TIME VIOLATION"`
360			`SEVERITY Error;`
361			`elsif A_wr = '1' then`
362			`ASSERT (Tadr >= Twc)`
363			`REPORT "WRITE CYCLE TIME VIOLATION"`
364			`SEVERITY Error;`
365			`end if;`
366
367			`A_wr := '0';`
368			`A_rd := '0';`
369			`end if;`
370
371			`End Process;`
372
373
374			`------ Checks for Tsce, Taw, Tsa, Tpwe, Tsd and Tbw.`
375
376			`Process (ce, wr, WE_b, A, IO)`
377
378			`VARIABLE wr_end_chk, A_end : Std_logic := '0';`
379			`VARIABLE Taw_chk, Tsd_chk, Tsa_chk : Time;`
380
381			`begin`
382
383			`ce_chk <= ce;`
384			`we_chk <= we;`
385			`addr(12 downto 0) <= address(12 downto 0);`
386			`wr_sa1 <= wr;`
387
388			`wr_end_chk := '0';`
389			`if (wr'event and wr'last_value = '1') then`
390			`wr_end_chk := '1';`
391			`else`
392			`wr_end_chk := '0';`
393			`end if;`
394
395			`A_end := '0';`
396			`if (address'event) and (wr_end_chk = '1') then`
397			`A_end := '1';`
398			`else`
399			`A_end := '0';`
400			`end if;`
401
402			`if (A'event) then`
403			`Taw_chk := address'last_event;`
404			`end if;`
405
406			`if (IO'event) then`
407			`Tsd_chk := io_reg'last_event;`
408			`end if;`
409
410			`if (wr_end_chk = '1' and A_end = '1') then`
411			`Tsa_chk := Taw_chk - wr_sa1'last_event;`
412			`elsif (wr_end_chk = '1' and A_end = '0') then`
413			`Tsa_chk := A'last_event - wr_sa1'last_event;`
414			`end if;`
415
416			`if wr_end_chk = '1' then`
417
418			`ASSERT (ce_chk'LAST_EVENT >= Tsce)`
419			`REPORT "CE LOW TO WRITE END TIME VIOLATION"`
420			`SEVERITY Error;`
421
422			`if (we'event) then`
423			`ASSERT (we_chk'LAST_EVENT >= Tpwe)`
424			`REPORT "WE PULSE WIDTH TIME VIOLATION"`
425			`SEVERITY Error;`
426			`else`
427			`ASSERT (WE_b'LAST_EVENT >= Tpwe)`
428			`REPORT "WE PULSE WIDTH TIME VIOLATION"`
429			`SEVERITY Error;`
430			`end if;`
431
432			`if (A_end = '1') then`
433			`ASSERT (Taw_chk >= Taw)`
434			`REPORT "ADDRESS SETUP TO WRITE END TIME VIOLATION"`
435			`SEVERITY Error;`
436			`else`
437			`ASSERT (A'LAST_EVENT >= Taw)`
438			`REPORT "ADDRESS SETUP TO WRITE END TIME VIOLATION"`
439			`SEVERITY Error;`
440			`end if;`
441
442			`if (io_reg'event) then`
443			`ASSERT (Tsd_chk >= Tsd)`
444			`REPORT "DATA SETUP TO WRITE END TIME VIOLATION"`
445			`SEVERITY Error;`
446			`else`
447			`ASSERT (IO'LAST_EVENT >= Tsd)`
448			`REPORT "DATA SETUP TO WRITE END TIME VIOLATION"`
449			`SEVERITY Error;`
450			`end if;`
451
452			`ASSERT (Tsa_chk >= Tsa) or (Tsa_chk < 0 ns)`
453			`REPORT "ADDRESS SETUP TO WRITE START TIME VIOLATION"`
454			`SEVERITY Error;`
455			`end if;`
456
457			`end Process;`
458
459			`----- Address Hold (Tha) and Data Hold (Thd) time checks on write.`
460
461			`Process (wr'delayed(Thd), wr'delayed(Tha), A, IO)`
462
463			`begin`
464
465			`if (wr'delayed(Thd) = '0' and wr'delayed(Thd)'last_value = '1') and (wr'delayed(Thd)'event) then`
466
467			`ASSERT (IO'LAST_EVENT = 0 ns) or (IO'LAST_EVENT > Thd)`
468			`REPORT "DATA HOLD FROM WRITE END TIME VIOLATION"`
469			`SEVERITY Error;`
470
471			`end if;`
472
473			`if (wr'delayed(Tha) = '0' and wr'delayed(Tha)'last_value = '1') and (wr'delayed(Tha)'event) then`
474
475			`ASSERT (A'LAST_EVENT = 0 ns) or (A'LAST_EVENT > Tha)`
476			`REPORT "ADDRESS HOLD FROM WRITE END TIME VIOLATION"`
477			`SEVERITY Error;`
478
479			`end if;`
480
481			`End Process;`
482
483			`---- Tdoe, Tdbe, Tace, Taa and Toha time checks on read.`
484
485			`Process (IO, A'delayed(Toha))`
486			`begin`
487
488			`if ((IO'event) and (rd = '1')) then`
489
490			`if (rd'last_event <= A'last_event) then`
491			`ASSERT (OE_n'LAST_EVENT >= Tdoe)`
492			`REPORT "OE LOW TO DATA VALID TIME VIOLATION"`
493			`SEVERITY Error;`
494
495			`ASSERT (CE_b'LAST_EVENT >= Tace)`
496			`REPORT "CE LOW TO DATA VALID TIME VIOLATION"`
497			`SEVERITY Error;`
498			`end if;`
499
500			`if (rd'last_event > A'last_event) then`
501			`ASSERT (A'LAST_EVENT >= Taa)`
502			`REPORT "ADDRESS TO DATA VALID TIME VIOLATION"`
503			`SEVERITY Error;`
504			`end if;`
505
506			`end if;`
507
508			`if (A'delayed(Toha)'event and (rd = '1')) then`
509
510			`if (rd'last_event > Toha) then`
511			`ASSERT (IO'LAST_EVENT = 0 ns) or (IO'LAST_EVENT > Toha)`
512			`REPORT "DATA HOLD FROM ADDRESS CHANGE TIME VIOLATION"`
513			`SEVERITY Error;`
514			`end if;`
515
516			`end if;`
517
518			`End Process;`
519
520			`------ Thzbe, Thzoe and Thzce time checks.`
521
522			`Process (OE_n'delayed(Thzoe), CE_b'delayed(Thzce))`
523			`begin`
524
525			`if (OE_n'delayed(Thzoe)'event and OE_n'delayed'last_value = '0' and OE_n'delayed(Thzoe) = '1') then`
526
527			`ASSERT (IO'LAST_EVENT = 0 ns) or (IO'LAST_EVENT > Thzoe)`
528			`REPORT "OE DISABLE TO HIGH Z TIME VIOLATION"`
529			`SEVERITY Error;`
530
531			`end if;`
532
533			`if (CE_b'delayed(Thzce)'event and CE_b'delayed'last_value = '0' and CE_b'delayed(Thzce) = '1') then`
534
535			`ASSERT (IO'LAST_EVENT = 0 ns) or (IO'LAST_EVENT > Thzce)`
536			`REPORT "CE DISABLE TO HIGH Z TIME VIOLATION"`
537			`SEVERITY Error;`
538
539			`end if;`
540
541			`End Process;`
542			`End Behavioral;`
543