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[/] [mem_ctrl/] [trunk/] [bench/] [vhdl/] [mt58l64l32p.v] - Blame information for rev 28

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1 4 rudi 
/****************************************************************************************
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*
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*    File Name:  MT58L64L32P.V
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*      Version:  1.5
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*         Date:  June 29th, 2001
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*        Model:  Behavioral
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*    Simulator:  Model Technology
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*
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* Dependencies:  None
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*
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*       Author:  Son P. Huynh
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*        Email:  sphuynh@micron.com
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*        Phone:  (208) 368-3825
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*      Company:  Micron Technology, Inc.
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*       Part #:  MT58L64L32P (64K x 32)
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*
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*  Description:  This is Micron's Synburst SRAM (Pipelined SCD)
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*
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*   Limitation:
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*
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*   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
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*                WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
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*                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
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*                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
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*
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*                Copyright (c) 1997 Micron Semiconductor Products, Inc.
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*                All rights researved
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*
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* Rev  Author          Phone           Date        Changes
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* ---  --------------  --------------  ----------  --------------------------------------
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* 1.5  Son P. Huynh    (208) 368-3825  04/30/1999  Update timing parameters
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*      Micron Technology, Inc.
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*
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****************************************************************************************/
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// DO NOT CHANGE THE TIMESCALE
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// MAKE SURE YOUR SIMULATOR USE "PS" RESOLUTION
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`timescale 1ns / 100ps
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module mt58l64l32p (Dq, Addr, Mode, Adv_n, Clk, Adsc_n, Adsp_n, Bwa_n, Bwb_n, Bwc_n, Bwd_n, Bwe_n, Gw_n, Ce_n, Ce2, Ce2_n, Oe_n, Zz);
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    // Constant Parameters
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    parameter                       addr_bits =     16;         //  16 bits
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    parameter                       data_bits =     32;         //  32 bits
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    parameter                       mem_sizes =  65535;         //  64 K
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    // Timing Parameters for -5 (200 Mhz)
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    parameter                       tKQHZ     =      2.5;       // Clock to output HiZ
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    // Port Delcarations
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    inout     [(data_bits - 1) : 0] Dq;                         // Data IO
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    input     [(addr_bits - 1) : 0] Addr;                       // Address
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    input                           Mode;                       // Burst Mode
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    input                           Adv_n;                      // Synchronous Address Advance
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    input                           Clk;                        // Clock
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    input                           Adsc_n;                     // Synchronous Address Status Controller
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    input                           Adsp_n;                     // Synchronous Address Status Processor
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    input                           Bwa_n;                      // Synchronous Byte Write Enables
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    input                           Bwb_n;                      // Synchronous Byte Write Enables
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    input                           Bwc_n;                      // Synchronous Byte Write Enables
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    input                           Bwd_n;                      // Synchronous Byte Write Enables
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    input                           Bwe_n;                      // Byte Write Enable
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    input                           Gw_n;                       // Global Write
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    input                           Ce_n;                       // Synchronous Chip Enable
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    input                           Ce2;                        // Synchronous Chip Enable
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    input                           Ce2_n;                      // Synchronous Chip Enable
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    input                           Oe_n;                       // Output Enable
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    input                           Zz;                         // Snooze Mode
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    // Memory Arrays
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    reg [((data_bits / 4) - 1) : 0] bank0 [0 : mem_sizes];      // Memory Bank 0
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    reg [((data_bits / 4) - 1) : 0] bank1 [0 : mem_sizes];      // Memory Bank 1
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    reg [((data_bits / 4) - 1) : 0] bank2 [0 : mem_sizes];      // Memory Bank 2
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    reg [((data_bits / 4) - 1) : 0] bank3 [0 : mem_sizes];      // Memory Bank 3
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    // Declare Connection Variables
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    reg       [(data_bits - 1) : 0] dout;                       // Output Registers
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    reg       [(addr_bits - 1) : 0] addr_reg_in;                // Address Register In
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    reg       [(addr_bits - 1) : 0] addr_reg_read;              // Address Register for Read Operation
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    reg                     [1 : 0] bcount;                     // 2-bit Burst Counter
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    reg                             ce_reg;
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    reg                             pipe_reg;
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    reg                             bwa_reg;
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    reg                             bwb_reg;
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    reg                             bwc_reg;
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    reg                             bwd_reg;
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    reg                             sys_clk;
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    wire                            ce      = (~Ce_n & Ce2 & ~Ce2_n);
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    wire                            bwa_n   = ((Bwa_n | Bwe_n) & Gw_n | (~Ce_n & ~Adsp_n));
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    wire                            bwb_n   = ((Bwb_n | Bwe_n) & Gw_n | (~Ce_n & ~Adsp_n));
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    wire                            bwc_n   = ((Bwc_n | Bwe_n) & Gw_n | (~Ce_n & ~Adsp_n));
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    wire                            bwd_n   = ((Bwd_n | Bwe_n) & Gw_n | (~Ce_n & ~Adsp_n));
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    wire                            clr     = (~Adsc_n | (~Adsp_n & ~Ce_n));
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    wire      [(addr_bits - 1) : 0] addr_reg_write;             // Address Register for Write Operation
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    wire                            baddr1;                     // Burst Address 1
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    wire                            baddr0;                     // Burst Address 0
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    // Initial Conditions
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    initial begin
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        ce_reg = 1'b0;
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        sys_clk = 1'b0;
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        pipe_reg = 1'b0;
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        $timeformat (-9, 1, " ns", 10);                         // Format time unit
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    end
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    // System Clock
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    always begin
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        @ (posedge Clk) begin
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            sys_clk = ~Zz;
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        end
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        @ (negedge Clk) begin
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            sys_clk = 1'b0;
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        end
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    end
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    always @ (posedge sys_clk) begin
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        // Address Register
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        if (clr) addr_reg_in   <= Addr;
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                 addr_reg_read <= {addr_reg_in[addr_bits - 1 : 2], baddr1, baddr0};
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        // Binary Counter and Logic
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        if      ( Mode  &  clr) bcount <= 0;                    // Interleaved Burst
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        else if (~Mode  &  clr) bcount <= Addr [1 : 0];         // Linear Burst
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        else if (~Adv_n & ~clr) bcount <= (bcount + 1);         // Advance Counter
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        // Byte Write Register
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        bwa_reg <= ~bwa_n;
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        bwb_reg <= ~bwb_n;
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        bwc_reg <= ~bwc_n;
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        bwd_reg <= ~bwd_n;
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        // Enable Register
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        if (clr) ce_reg <= ce;
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        // Pipelined Enable
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        pipe_reg <= ce_reg;
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    end
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    // Burst Address Decode
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    assign addr_reg_write = {addr_reg_in [(addr_bits - 1) : 2], baddr1, baddr0};
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    assign baddr1 = Mode ? (bcount [1] ^ addr_reg_in [1]) : bcount [1];
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    assign baddr0 = Mode ? (bcount [0] ^ addr_reg_in [0]) : bcount [0];
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    // Write Driver
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    always @ (posedge Clk) begin
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        #0.1;
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        if (ce_reg & bwa_reg) begin
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            bank0 [addr_reg_write] <= Dq [((data_bits / 4) - 1) : 0];
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        end
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        if (ce_reg & bwb_reg) begin
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            bank1 [addr_reg_write] <= Dq [((data_bits / 2) - 1) : (data_bits / 4)];
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        end
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        if (ce_reg & bwc_reg) begin
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            bank2 [addr_reg_write] <= Dq [(((data_bits / 4) * 3) - 1) : (data_bits / 2)];
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        end
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        if (ce_reg & bwd_reg) begin
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            bank3 [addr_reg_write] <= Dq [(data_bits - 1) : ((data_bits / 4) * 3)];
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        end
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    end
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    // Output Register
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    always @ (posedge Clk) begin
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        #0.1;
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        if (~(bwa_reg | bwb_reg | bwc_reg | bwd_reg)) begin
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            dout [((data_bits / 4) - 1) : 0] <= bank0 [addr_reg_read];
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            dout [((data_bits / 2) - 1) : (data_bits / 4)] <= bank1 [addr_reg_read];
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            dout [(((data_bits / 4) * 3) - 1) : (data_bits / 2)] <= bank2 [addr_reg_read];
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            dout [(data_bits - 1) : ((data_bits / 4) * 3)] <= bank3 [addr_reg_read];
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        end
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    end
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    // Output Buffer
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    assign #tKQHZ Dq = (~Oe_n & ~Zz & ce_reg & pipe_reg & ~(bwa_reg | bwb_reg | bwc_reg | bwd_reg)) ? dout : {data_bits{1'bz}};
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    // Timing Check for -5 (200 Mhz)
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    specify
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        specparam   // Clock
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                    tKC     =  5.0,
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                    tKH     =  1.6,
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                    tKL     =  1.6,
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                    // Setup Times
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                    tAS     =  1.5,
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                    tADSS   =  1.5,
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                    tAAS    =  1.5,
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                    tWS     =  1.5,
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                    tDS     =  1.5,
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                    tCES    =  1.5,
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                    // Hold Times
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                    tAH     =  0.5,
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                    tADSH   =  0.5,
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                    tAAH    =  0.5,
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                    tWH     =  0.5,
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                    tDH     =  0.5,
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                    tCEH    =  0.5;
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        $width      (negedge Clk, tKL);
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        $width      (posedge Clk, tKH);
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        $period     (negedge Clk, tKC);
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        $period     (posedge Clk, tKC);
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        $setuphold  (posedge Clk, Adsp_n, tADSS, tADSH);
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        $setuphold  (posedge Clk, Adsc_n, tADSS, tADSH);
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        $setuphold  (posedge Clk, Addr,   tAS,   tAH);
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        $setuphold  (posedge Clk, Bwa_n,  tWS,   tWH);
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        $setuphold  (posedge Clk, Bwb_n,  tWS,   tWH);
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        $setuphold  (posedge Clk, Bwc_n,  tWS,   tWH);
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        $setuphold  (posedge Clk, Bwd_n,  tWS,   tWH);
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        $setuphold  (posedge Clk, Bwe_n,  tWS,   tWH);
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        $setuphold  (posedge Clk, Gw_n,   tWS,   tWH);
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        $setuphold  (posedge Clk, Ce_n,   tCES,  tCEH);
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        $setuphold  (posedge Clk, Ce2,    tCES,  tCEH);
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        $setuphold  (posedge Clk, Ce2_n,  tCES,  tCEH);
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        $setuphold  (posedge Clk, Adv_n,  tAAS,  tAAH);
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    endspecify
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endmodule
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