Subversion Repositories mem_ctrl

The WISHBONE Advanced Memory Controller

http://www.opencores.org/cores/mem_ctrl

To find out more about me (Rudolf Usselmann), please visit:

http://www.asics.ws

Directory Structure

-------------------

[core_root]

 |

 +-doc                        Documentation

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 +-bench--+                   Test Bench

 |        +- verilog          Verilog Sources

 |        +-vhdl              VHDL Sources

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 +-rtl----+                   Core RTL Sources

 |        +-verilog           Verilog Sources

 |        +-vhdl              VHDL Sources

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 +-sim----+

 |        +-rtl_sim---+       Functional verification Directory

 |        |           +-bin   Makefiles/Run Scripts

 |        |           +-run   Working Directory

 |        |

 |        +-gate_sim--+       Functional & Timing Gate Level

 |                    |       Verification Directory

 |                    +-bin   Makefiles/Run Scripts

 |                    +-run   Working Directory

 |

 +-lint--+                    Lint Directory Tree

 |       +-bin                Makefiles/Run Scripts

 |       +-run                Working Directory

 |       +-log                Linter log & result files

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 +-syn---+                    Synthesis Directory Tree

 |       +-bin                Synthesis Scripts

 |       +-run                Working Directory

 |       +-log                Synthesis log files

 |       +-out                Synthesis Output