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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Memory Controller Address Select Block            ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: mc_adr_sel.v,v 1.3 2001-11-29 02:16:28 rudi Exp $
//
//  $Date: 2001-11-29 02:16:28 $
//  $Revision: 1.3 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.2  2001/08/10 08:16:21  rudi
//
//               - Changed IO names to be more clear.
//               - Uniquifyed define names to be core specific.
//               - Removed "Refresh Early" configuration
//
//               Revision 1.1  2001/07/29 07:34:41  rudi
//
//
//               1) Changed Directory Structure
//               2) Fixed several minor bugs
//
//               Revision 1.2  2001/06/12 15:19:49  rudi
//
//
//               Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
//
//               Revision 1.1.1.1  2001/05/13 09:39:40  rudi
//               Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_adr_sel(clk, csc, tms, wb_ack_o, wb_stb_i, wb_addr_i, wb_we_i,
                wb_write_go, wr_hold, cas_,
                mc_addr, row_adr, bank_adr, rfr_ack,
                cs_le, cmd_a10, row_sel, lmr_sel, next_adr, wr_cycle,
                page_size);
 
input           clk;
input   [31:0]   csc;
input   [31:0]   tms;
input           wb_ack_o, wb_stb_i;
input   [31:0]   wb_addr_i;
input           wb_we_i;
input           wb_write_go;
input           wr_hold;
input           cas_;
output  [23:0]   mc_addr;
output  [12:0]   row_adr;
output  [1:0]    bank_adr;
input           rfr_ack;
input           cs_le;
input           cmd_a10;
input           row_sel;
input           lmr_sel;
input           next_adr;
input           wr_cycle;
output  [10:0]   page_size;
 
////////////////////////////////////////////////////////////////////
//
// Local Registers & Wires
//
 
reg     [23:0]   mc_addr_d;
reg     [23:0]   acs_addr;
wire    [23:0]   acs_addr_pl1;
reg     [23:0]   sram_addr;
wire    [14:0]   sdram_adr;
reg     [12:0]   row_adr;
reg     [9:0]    col_adr;
reg     [1:0]    bank_adr;
reg     [10:0]   page_size;
 
wire    [2:0]    mem_type;
wire    [1:0]    bus_width;
wire    [1:0]    mem_size;
wire            bas;
 
// Aliases
assign mem_type  = csc[3:1];
assign bus_width = csc[5:4];
assign mem_size  = csc[7:6];
assign bas       = csc[9];
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
always @(mem_type or wr_hold or sdram_adr or acs_addr or sram_addr or wb_addr_i)
        if(mem_type == `MC_MEM_TYPE_SDRAM)              mc_addr_d = {9'h0, sdram_adr};
        else
        if(mem_type == `MC_MEM_TYPE_ACS)                mc_addr_d = acs_addr;
        else
        if((mem_type == `MC_MEM_TYPE_SRAM) & wr_hold)   mc_addr_d = sram_addr;
        else                                            mc_addr_d = wb_addr_i[25:2];
 
assign mc_addr = rfr_ack ? {mc_addr_d[23:11], 1'b1, mc_addr_d[9:0]} : mc_addr_d;
 
////////////////////////////////////////////////////////////////////
//
// Async Devices Address Latch & Counter
//
 
mc_incn_r #(24) u0(     .clk(           clk             ),
                        .inc_in(        acs_addr        ),
                        .inc_out(       acs_addr_pl1    ) );
 
always @(posedge clk)
        if(wb_stb_i)    sram_addr <= #1 wb_addr_i[25:2];
 
always @(posedge clk)
        if(cs_le | wb_we_i)
                case(bus_width)         // synopsys full_case parallel_case
                   `MC_BW_8:    acs_addr <= #1 wb_addr_i[23:0];
                   `MC_BW_16:   acs_addr <= #1 wb_addr_i[24:1];
                   `MC_BW_32:   acs_addr <= #1 wb_addr_i[25:2];
                endcase
        else
        if(next_adr)            acs_addr <= #1 acs_addr_pl1;
 
////////////////////////////////////////////////////////////////////
//
// SDRAM Address Mux
//
 
assign sdram_adr[12:0] = (lmr_sel & !cas_) ? tms[12:0] :
                                row_sel ? row_adr :
                                {2'h0, cmd_a10, col_adr};
 
assign sdram_adr[14:13] = bank_adr;
 
always @(posedge clk)
   if(wr_cycle ? wb_ack_o : wb_stb_i)
        casex({bus_width, mem_size})            // synopsys full_case parallel_case
           {`MC_BW_8, `MC_MEM_SIZE_64}:         col_adr <= #1 {1'h0, wb_addr_i[10:2]};
           {`MC_BW_8, `MC_MEM_SIZE_128}:        col_adr <= #1        wb_addr_i[11:2];
           {`MC_BW_8, `MC_MEM_SIZE_256}:        col_adr <= #1        wb_addr_i[11:2];
 
           {`MC_BW_16, `MC_MEM_SIZE_64}:        col_adr <= #1 {2'h0, wb_addr_i[09:2]};
           {`MC_BW_16, `MC_MEM_SIZE_128}:       col_adr <= #1 {1'h0, wb_addr_i[10:2]};
           {`MC_BW_16, `MC_MEM_SIZE_256}:       col_adr <= #1 {1'h0, wb_addr_i[10:2]};
 
           {`MC_BW_32, `MC_MEM_SIZE_64}:        col_adr <= #1 {2'h0, wb_addr_i[09:2]};
           {`MC_BW_32, `MC_MEM_SIZE_128}:       col_adr <= #1 {2'h0, wb_addr_i[09:2]};
           {`MC_BW_32, `MC_MEM_SIZE_256}:       col_adr <= #1 {2'h0, wb_addr_i[09:2]};
        endcase
 
always @(posedge clk)
   if(cs_le)
     begin
        if(!bas)
                casex({bus_width, mem_size})            // synopsys full_case parallel_case
                   {`MC_BW_8, `MC_MEM_SIZE_64}:         row_adr <= #1 {1'h0, wb_addr_i[24:13]};
                   {`MC_BW_8, `MC_MEM_SIZE_128}:        row_adr <= #1 {1'h0, wb_addr_i[25:14]};
                   {`MC_BW_8, `MC_MEM_SIZE_256}:        row_adr <= #1        wb_addr_i[26:14];
 
                   {`MC_BW_16, `MC_MEM_SIZE_64}:        row_adr <= #1 {1'h0, wb_addr_i[23:12]};
                   {`MC_BW_16, `MC_MEM_SIZE_128}:       row_adr <= #1 {1'h0, wb_addr_i[24:13]};
                   {`MC_BW_16, `MC_MEM_SIZE_256}:       row_adr <= #1        wb_addr_i[25:13];
 
                   {`MC_BW_32, `MC_MEM_SIZE_64}:        row_adr <= #1 {2'h0, wb_addr_i[22:12]};
                   {`MC_BW_32, `MC_MEM_SIZE_128}:       row_adr <= #1 {1'h0, wb_addr_i[23:12]};
                   {`MC_BW_32, `MC_MEM_SIZE_256}:       row_adr <= #1        wb_addr_i[24:12];
                endcase
        else
                casex({bus_width, mem_size})            // synopsys full_case parallel_case
                   {`MC_BW_8, `MC_MEM_SIZE_64}:         row_adr <= #1 {1'h0, wb_addr_i[22:11]};
                   {`MC_BW_8, `MC_MEM_SIZE_128}:        row_adr <= #1 {1'h0, wb_addr_i[23:12]};
                   {`MC_BW_8, `MC_MEM_SIZE_256}:        row_adr <= #1        wb_addr_i[24:12];
 
                   {`MC_BW_16, `MC_MEM_SIZE_64}:        row_adr <= #1 {1'h0, wb_addr_i[21:10]};
                   {`MC_BW_16, `MC_MEM_SIZE_128}:       row_adr <= #1 {1'h0, wb_addr_i[22:11]};
                   {`MC_BW_16, `MC_MEM_SIZE_256}:       row_adr <= #1        wb_addr_i[23:11];
 
                   {`MC_BW_32, `MC_MEM_SIZE_64}:        row_adr <= #1 {2'h0, wb_addr_i[20:10]};
                   {`MC_BW_32, `MC_MEM_SIZE_128}:       row_adr <= #1 {1'h0, wb_addr_i[21:10]};
                   {`MC_BW_32, `MC_MEM_SIZE_256}:       row_adr <= #1        wb_addr_i[22:10];
                endcase
     end
 
 
always @(posedge clk)
   if(cs_le)
     begin
        if(!bas)
                casex({bus_width, mem_size})            // synopsys full_case parallel_case
                   {`MC_BW_8, `MC_MEM_SIZE_64}:         bank_adr <= #1 wb_addr_i[12:11];
                   {`MC_BW_8, `MC_MEM_SIZE_128}:        bank_adr <= #1 wb_addr_i[13:12];
                   {`MC_BW_8, `MC_MEM_SIZE_256}:        bank_adr <= #1 wb_addr_i[13:12];
 
                   {`MC_BW_16, `MC_MEM_SIZE_64}:        bank_adr <= #1 wb_addr_i[11:10];
                   {`MC_BW_16, `MC_MEM_SIZE_128}:       bank_adr <= #1 wb_addr_i[12:11];
                   {`MC_BW_16, `MC_MEM_SIZE_256}:       bank_adr <= #1 wb_addr_i[12:11];
 
                   {`MC_BW_32, `MC_MEM_SIZE_64}:        bank_adr <= #1 wb_addr_i[11:10];
                   {`MC_BW_32, `MC_MEM_SIZE_128}:       bank_adr <= #1 wb_addr_i[11:10];
                   {`MC_BW_32, `MC_MEM_SIZE_256}:       bank_adr <= #1 wb_addr_i[11:10];
                endcase
        else
                casex({bus_width, mem_size})            // synopsys full_case parallel_case
                   {`MC_BW_8, `MC_MEM_SIZE_64}:         bank_adr <= #1 wb_addr_i[24:23];
                   {`MC_BW_8, `MC_MEM_SIZE_128}:        bank_adr <= #1 wb_addr_i[25:24];
                   {`MC_BW_8, `MC_MEM_SIZE_256}:        bank_adr <= #1 wb_addr_i[26:25];
 
                   {`MC_BW_16, `MC_MEM_SIZE_64}:        bank_adr <= #1 wb_addr_i[23:22];
                   {`MC_BW_16, `MC_MEM_SIZE_128}:       bank_adr <= #1 wb_addr_i[24:23];
                   {`MC_BW_16, `MC_MEM_SIZE_256}:       bank_adr <= #1 wb_addr_i[25:24];
 
                   {`MC_BW_32, `MC_MEM_SIZE_64}:        bank_adr <= #1 wb_addr_i[22:21];
                   {`MC_BW_32, `MC_MEM_SIZE_128}:       bank_adr <= #1 wb_addr_i[23:22];
                   {`MC_BW_32, `MC_MEM_SIZE_256}:       bank_adr <= #1 wb_addr_i[24:23];
                endcase
     end
 
always @(bus_width or mem_size)
        casex({bus_width, mem_size})            // synopsys full_case parallel_case
           {`MC_BW_8, `MC_MEM_SIZE_64}:         page_size = 11'd512;
           {`MC_BW_8, `MC_MEM_SIZE_128}:        page_size = 11'd1024;
           {`MC_BW_8, `MC_MEM_SIZE_256}:        page_size = 11'd1024;
 
           {`MC_BW_16, `MC_MEM_SIZE_64}:        page_size = 11'd256;
           {`MC_BW_16, `MC_MEM_SIZE_128}:       page_size = 11'd512;
           {`MC_BW_16, `MC_MEM_SIZE_256}:       page_size = 11'd512;
 
           {`MC_BW_32, `MC_MEM_SIZE_64}:        page_size = 11'd256;
           {`MC_BW_32, `MC_MEM_SIZE_128}:       page_size = 11'd256;
           {`MC_BW_32, `MC_MEM_SIZE_256}:       page_size = 11'd256;
        endcase
 
endmodule
 

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Memory Controller Address Select Block ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40	16	rudi	`// $Id: mc_adr_sel.v,v 1.3 2001-11-29 02:16:28 rudi Exp $`
41	4	rudi	`//`
42	16	rudi	`// $Date: 2001-11-29 02:16:28 $`
43			`// $Revision: 1.3 $`
44	4	rudi	`// $Author: rudi $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	16	rudi	`// Revision 1.2 2001/08/10 08:16:21 rudi`
51			`//`
52			`// - Changed IO names to be more clear.`
53			`// - Uniquifyed define names to be core specific.`
54			`// - Removed "Refresh Early" configuration`
55			`//`
56	8	rudi	`// Revision 1.1 2001/07/29 07:34:41 rudi`
57			`//`
58			`//`
59			`// 1) Changed Directory Structure`
60			`// 2) Fixed several minor bugs`
61			`//`
62	4	rudi	`// Revision 1.2 2001/06/12 15:19:49 rudi`
63			`//`
64			`//`
65			`// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.`
66			`//`
67			`// Revision 1.1.1.1 2001/05/13 09:39:40 rudi`
68			`// Created Directory Structure`
69			`//`
70			`//`
71			`//`
72			`//`
73
74			`include "mc_defines.v"
75
76	16	rudi	`module mc_adr_sel(clk, csc, tms, wb_ack_o, wb_stb_i, wb_addr_i, wb_we_i,`
77	4	rudi	`wb_write_go, wr_hold, cas_,`
78			`mc_addr, row_adr, bank_adr, rfr_ack,`
79			`cs_le, cmd_a10, row_sel, lmr_sel, next_adr, wr_cycle,`
80			`page_size);`
81
82			`input clk;`
83			`input [31:0] csc;`
84			`input [31:0] tms;`
85			`input wb_ack_o, wb_stb_i;`
86			`input [31:0] wb_addr_i;`
87	16	rudi	`input wb_we_i;`
88	4	rudi	`input wb_write_go;`
89			`input wr_hold;`
90			`input cas_;`
91			`output [23:0] mc_addr;`
92			`output [12:0] row_adr;`
93			`output [1:0] bank_adr;`
94			`input rfr_ack;`
95			`input cs_le;`
96			`input cmd_a10;`
97			`input row_sel;`
98			`input lmr_sel;`
99			`input next_adr;`
100			`input wr_cycle;`
101			`output [10:0] page_size;`
102
103			`////////////////////////////////////////////////////////////////////`
104			`//`
105			`// Local Registers & Wires`
106			`//`
107
108			`reg [23:0] mc_addr_d;`
109			`reg [23:0] acs_addr;`
110			`wire [23:0] acs_addr_pl1;`
111			`reg [23:0] sram_addr;`
112			`wire [14:0] sdram_adr;`
113			`reg [12:0] row_adr;`
114			`reg [9:0] col_adr;`
115			`reg [1:0] bank_adr;`
116			`reg [10:0] page_size;`
117
118			`wire [2:0] mem_type;`
119			`wire [1:0] bus_width;`
120			`wire [1:0] mem_size;`
121			`wire bas;`
122
123			`// Aliases`
124			`assign mem_type = csc[3:1];`
125			`assign bus_width = csc[5:4];`
126			`assign mem_size = csc[7:6];`
127			`assign bas = csc[9];`
128
129			`////////////////////////////////////////////////////////////////////`
130			`//`
131			`// Misc Logic`
132			`//`
133
134			`always @(mem_type or wr_hold or sdram_adr or acs_addr or sram_addr or wb_addr_i)`
135	8	rudi	if(mem_type == `MC_MEM_TYPE_SDRAM) mc_addr_d = {9'h0, sdram_adr};
136	4	rudi	`else`
137	8	rudi	if(mem_type == `MC_MEM_TYPE_ACS) mc_addr_d = acs_addr;
138	4	rudi	`else`
139	8	rudi	if((mem_type == `MC_MEM_TYPE_SRAM) & wr_hold) mc_addr_d = sram_addr;
140	4	rudi	`else mc_addr_d = wb_addr_i[25:2];`
141
142			`assign mc_addr = rfr_ack ? {mc_addr_d[23:11], 1'b1, mc_addr_d[9:0]} : mc_addr_d;`
143
144			`////////////////////////////////////////////////////////////////////`
145			`//`
146			`// Async Devices Address Latch & Counter`
147			`//`
148
149			`mc_incn_r #(24) u0( .clk( clk ),`
150			`.inc_in( acs_addr ),`
151			`.inc_out( acs_addr_pl1 ) );`
152
153			`always @(posedge clk)`
154			`if(wb_stb_i) sram_addr <= #1 wb_addr_i[25:2];`
155
156			`always @(posedge clk)`
157	16	rudi	`if(cs_le \| wb_we_i)`
158	4	rudi	`case(bus_width) // synopsys full_case parallel_case`
159	8	rudi	`MC_BW_8: acs_addr <= #1 wb_addr_i[23:0];
160			`MC_BW_16: acs_addr <= #1 wb_addr_i[24:1];
161			`MC_BW_32: acs_addr <= #1 wb_addr_i[25:2];
162	4	rudi	`endcase`
163			`else`
164			`if(next_adr) acs_addr <= #1 acs_addr_pl1;`
165
166			`////////////////////////////////////////////////////////////////////`
167			`//`
168			`// SDRAM Address Mux`
169			`//`
170
171			`assign sdram_adr[12:0] = (lmr_sel & !cas_) ? tms[12:0] :`
172			`row_sel ? row_adr :`
173			`{2'h0, cmd_a10, col_adr};`
174
175			`assign sdram_adr[14:13] = bank_adr;`
176
177			`always @(posedge clk)`
178			`if(wr_cycle ? wb_ack_o : wb_stb_i)`
179			`casex({bus_width, mem_size}) // synopsys full_case parallel_case`
180	8	rudi	{`MC_BW_8, `MC_MEM_SIZE_64}: col_adr <= #1 {1'h0, wb_addr_i[10:2]};
181			{`MC_BW_8, `MC_MEM_SIZE_128}: col_adr <= #1 wb_addr_i[11:2];
182			{`MC_BW_8, `MC_MEM_SIZE_256}: col_adr <= #1 wb_addr_i[11:2];
183	4	rudi
184	8	rudi	{`MC_BW_16, `MC_MEM_SIZE_64}: col_adr <= #1 {2'h0, wb_addr_i[09:2]};
185			{`MC_BW_16, `MC_MEM_SIZE_128}: col_adr <= #1 {1'h0, wb_addr_i[10:2]};
186			{`MC_BW_16, `MC_MEM_SIZE_256}: col_adr <= #1 {1'h0, wb_addr_i[10:2]};
187	4	rudi
188	8	rudi	{`MC_BW_32, `MC_MEM_SIZE_64}: col_adr <= #1 {2'h0, wb_addr_i[09:2]};
189			{`MC_BW_32, `MC_MEM_SIZE_128}: col_adr <= #1 {2'h0, wb_addr_i[09:2]};
190			{`MC_BW_32, `MC_MEM_SIZE_256}: col_adr <= #1 {2'h0, wb_addr_i[09:2]};
191	4	rudi	`endcase`
192
193			`always @(posedge clk)`
194			`if(cs_le)`
195			`begin`
196			`if(!bas)`
197			`casex({bus_width, mem_size}) // synopsys full_case parallel_case`
198	8	rudi	{`MC_BW_8, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[24:13]};
199			{`MC_BW_8, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[25:14]};
200			{`MC_BW_8, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[26:14];
201	4	rudi
202	8	rudi	{`MC_BW_16, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[23:12]};
203			{`MC_BW_16, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[24:13]};
204			{`MC_BW_16, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[25:13];
205	4	rudi
206	8	rudi	{`MC_BW_32, `MC_MEM_SIZE_64}: row_adr <= #1 {2'h0, wb_addr_i[22:12]};
207			{`MC_BW_32, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[23:12]};
208			{`MC_BW_32, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[24:12];
209	4	rudi	`endcase`
210			`else`
211			`casex({bus_width, mem_size}) // synopsys full_case parallel_case`
212	8	rudi	{`MC_BW_8, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[22:11]};
213			{`MC_BW_8, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[23:12]};
214			{`MC_BW_8, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[24:12];
215	4	rudi
216	8	rudi	{`MC_BW_16, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[21:10]};
217			{`MC_BW_16, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[22:11]};
218			{`MC_BW_16, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[23:11];
219	4	rudi
220	8	rudi	{`MC_BW_32, `MC_MEM_SIZE_64}: row_adr <= #1 {2'h0, wb_addr_i[20:10]};
221			{`MC_BW_32, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[21:10]};
222			{`MC_BW_32, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[22:10];
223	4	rudi	`endcase`
224			`end`
225
226
227			`always @(posedge clk)`
228			`if(cs_le)`
229			`begin`
230			`if(!bas)`
231			`casex({bus_width, mem_size}) // synopsys full_case parallel_case`
232	8	rudi	{`MC_BW_8, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[12:11];
233			{`MC_BW_8, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[13:12];
234			{`MC_BW_8, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[13:12];
235	4	rudi
236	8	rudi	{`MC_BW_16, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[11:10];
237			{`MC_BW_16, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[12:11];
238			{`MC_BW_16, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[12:11];
239	4	rudi
240	8	rudi	{`MC_BW_32, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[11:10];
241			{`MC_BW_32, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[11:10];
242			{`MC_BW_32, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[11:10];
243	4	rudi	`endcase`
244			`else`
245			`casex({bus_width, mem_size}) // synopsys full_case parallel_case`
246	8	rudi	{`MC_BW_8, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[24:23];
247			{`MC_BW_8, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[25:24];
248			{`MC_BW_8, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[26:25];
249	4	rudi
250	8	rudi	{`MC_BW_16, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[23:22];
251			{`MC_BW_16, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[24:23];
252			{`MC_BW_16, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[25:24];
253	4	rudi
254	8	rudi	{`MC_BW_32, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[22:21];
255			{`MC_BW_32, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[23:22];
256			{`MC_BW_32, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[24:23];
257	4	rudi	`endcase`
258			`end`
259
260			`always @(bus_width or mem_size)`
261			`casex({bus_width, mem_size}) // synopsys full_case parallel_case`
262	8	rudi	{`MC_BW_8, `MC_MEM_SIZE_64}: page_size = 11'd512;
263			{`MC_BW_8, `MC_MEM_SIZE_128}: page_size = 11'd1024;
264			{`MC_BW_8, `MC_MEM_SIZE_256}: page_size = 11'd1024;
265	4	rudi
266	8	rudi	{`MC_BW_16, `MC_MEM_SIZE_64}: page_size = 11'd256;
267			{`MC_BW_16, `MC_MEM_SIZE_128}: page_size = 11'd512;
268			{`MC_BW_16, `MC_MEM_SIZE_256}: page_size = 11'd512;
269	4	rudi
270	8	rudi	{`MC_BW_32, `MC_MEM_SIZE_64}: page_size = 11'd256;
271			{`MC_BW_32, `MC_MEM_SIZE_128}: page_size = 11'd256;
272			{`MC_BW_32, `MC_MEM_SIZE_256}: page_size = 11'd256;
273	4	rudi	`endcase`
274
275			`endmodule`
276

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[/] [mem_ctrl/] [trunk/] [rtl/] [verilog/] [mc_adr_sel.v] - Blame information for rev 16