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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Memory Controller Definitions                     ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: mc_defines.v,v 1.6 2001-12-12 06:35:15 rudi Exp $
//
//  $Date: 2001-12-12 06:35:15 $
//  $Revision: 1.6 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.5  2001/12/11 02:47:19  rudi
//
//               - Made some changes not to expect clock during reset ...
//
//               Revision 1.4  2001/11/29 02:16:28  rudi
//
//
//               - More Synthesis cleanup, mostly for speed
//               - Several bug fixes
//               - Changed code to avoid auto-precharge and
//                 burst-terminate combinations (apparently illegal ?)
//                 Now we will do a manual precharge ...
//
//               Revision 1.3  2001/09/10 13:44:17  rudi
//               *** empty log message ***
//
//               Revision 1.2  2001/08/10 08:16:21  rudi
//
//               - Changed IO names to be more clear.
//               - Uniquifyed define names to be core specific.
//               - Removed "Refresh Early" configuration
//
//               Revision 1.1  2001/07/29 07:34:41  rudi
//
//
//               1) Changed Directory Structure
//               2) Fixed several minor bugs
//
//               Revision 1.3  2001/06/12 15:19:49  rudi
//
//
//              Minor changes after running lint, and a small bug
//              fix reading csr and ba_mask registers.
//
//               Revision 1.2  2001/06/03 11:37:17  rudi
//
//
//               1) Fixed Chip Select Mask Register
//                      - Power On Value is now all ones
//                      - Comparison Logic is now correct
//
//               2) All resets are now asynchronous
//
//               3) Converted Power On Delay to an configurable item
//
//               4) Added reset to Chip Select Output Registers
//
//               5) Forcing all outputs to Hi-Z state during reset
//
//               Revision 1.1.1.1  2001/05/13 09:39:38  rudi
//               Created Directory Structure
//
//
//
//
 
`timescale 1ns / 10ps
 
/////////////////////////////////////////////////////////////////////
//
// This define selects how the WISHBONE interface determines if
// the internal register file is selected.
// This should be a simple address decoder. "wb_addr_i" is the
// WISHBONE address bus (32 bits wide).
//`define       MC_REG_SEL              (wb_addr_i[31:29] == 3'h6)
`define MC_REG_SEL              (wb_addr_i[31:29] == 3'b011)
 
// This define selects how the WISHBONE interface determines if
// the memory is selected.
// This should be a simple address decoder. "wb_addr_i" is the
// WISHBONE address bus (32 bits wide).
`define MC_MEM_SEL              (wb_addr_i[31:29] == 3'h0)
 
/////////////////////////////////////////////////////////////////////
//
// This are the default Power-On Reset values for Chip Select
//
 
// This will be defined by the run script for my test bench ...
//`define RUDIS_TB 1
 
// Defines which chip select is used for Power On booting
 
// To run my default testbench default boot CS must be 3 !!!
`ifdef RUDIS_TB
`define MC_DEF_SEL              3'h3
`else
`define MC_DEF_SEL              3'h0
`endif
 
// Defines the default (reset) TMS value for the DEF_SEL chip select
`define MC_DEF_POR_TMS  32'hffff_ffff
 
 
/////////////////////////////////////////////////////////////////////
//
// Define how many Chip Selects to Implement
//
`define MC_HAVE_CS1     1
//`define MC_HAVE_CS2   1
//`define MC_HAVE_CS3   1
//`define MC_HAVE_CS4   1
//`define MC_HAVE_CS5   1
//`define MC_HAVE_CS6   1
//`define MC_HAVE_CS7   1
 
 
// To run my default testbench those need to there !!!
`ifdef RUDIS_TB
`define MC_HAVE_CS2     1
`define MC_HAVE_CS3     1
`define MC_HAVE_CS4     1
`define MC_HAVE_CS5     1
`endif
 
/////////////////////////////////////////////////////////////////////
//
// Init Refresh
//
// Number of Refresh Cycles to perform during SDRAM initialization.
// This varies between SDRAM manufacturer. Typically this value is
// between 2 and 8. This number must be smaller than 16.
`define MC_INIT_RFRC_CNT        2
 
/////////////////////////////////////////////////////////////////////
//
// Power On Delay
//
// Most if SDRAMs require some time to initialize before they can be used
// after power on. If the Memory Controller shall stall after power on to
// allow SDRAMs to finish the initialization process uncomment the below
// define statement
`define MC_POR_DELAY    1
 
// This value defines how many MEM_CLK cycles the Memory Controller should
// stall. Default is 2.5uS. At a 10nS MEM_CLK cycle time, this would 250
// cycles.
`define MC_POR_DELAY_VAL        8'd250
 
 
// ===============================================================
// ===============================================================
// Various internal defines (DO NOT MODIFY !)
// ===============================================================
// ===============================================================
 
// Register settings encodings
`define MC_BW_8                 2'h0
`define MC_BW_16                2'h1
`define MC_BW_32                2'h2
 
`define MC_MEM_TYPE_SDRAM       3'h0
`define MC_MEM_TYPE_SRAM        3'h1
`define MC_MEM_TYPE_ACS         3'h2
`define MC_MEM_TYPE_SCS         3'h3
 
`define MC_MEM_SIZE_64          2'h0
`define MC_MEM_SIZE_128         2'h1
`define MC_MEM_SIZE_256         2'h2
 
// Command Valid, Ras_, Cas_, We_
`define MC_CMD_NOP              4'b0111
`define MC_CMD_PC               4'b1010
`define MC_CMD_ACT              4'b1011
`define MC_CMD_WR               4'b1100
`define MC_CMD_RD               4'b1101
`define MC_CMD_BT               4'b1110
`define MC_CMD_ARFR             4'b1001
`define MC_CMD_LMR              4'b1000
`define MC_CMD_XRD              4'b1111
`define MC_CMD_XWR              4'b1110
 
`define MC_SINGLE_BANK          1'b0
`define MC_ALL_BANKS            1'b1
 

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Memory Controller Definitions ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40	19	rudi	`// $Id: mc_defines.v,v 1.6 2001-12-12 06:35:15 rudi Exp $`
41	4	rudi	`//`
42	19	rudi	`// $Date: 2001-12-12 06:35:15 $`
43			`// $Revision: 1.6 $`
44	4	rudi	`// $Author: rudi $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	19	rudi	`// Revision 1.5 2001/12/11 02:47:19 rudi`
51			`//`
52			`// - Made some changes not to expect clock during reset ...`
53			`//`
54	18	rudi	`// Revision 1.4 2001/11/29 02:16:28 rudi`
55			`//`
56			`//`
57			`// - More Synthesis cleanup, mostly for speed`
58			`// - Several bug fixes`
59			`// - Changed code to avoid auto-precharge and`
60			`// burst-terminate combinations (apparently illegal ?)`
61			`// Now we will do a manual precharge ...`
62			`//`
63	16	rudi	`// Revision 1.3 2001/09/10 13:44:17 rudi`
64			`// * empty log message *`
65			`//`
66	11	rudi	`// Revision 1.2 2001/08/10 08:16:21 rudi`
67			`//`
68			`// - Changed IO names to be more clear.`
69			`// - Uniquifyed define names to be core specific.`
70			`// - Removed "Refresh Early" configuration`
71			`//`
72	8	rudi	`// Revision 1.1 2001/07/29 07:34:41 rudi`
73			`//`
74			`//`
75			`// 1) Changed Directory Structure`
76			`// 2) Fixed several minor bugs`
77			`//`
78	4	rudi	`// Revision 1.3 2001/06/12 15:19:49 rudi`
79			`//`
80			`//`
81	16	rudi	`// Minor changes after running lint, and a small bug`
82			`// fix reading csr and ba_mask registers.`
83	4	rudi	`//`
84			`// Revision 1.2 2001/06/03 11:37:17 rudi`
85			`//`
86			`//`
87			`// 1) Fixed Chip Select Mask Register`
88			`// - Power On Value is now all ones`
89			`// - Comparison Logic is now correct`
90			`//`
91			`// 2) All resets are now asynchronous`
92			`//`
93			`// 3) Converted Power On Delay to an configurable item`
94			`//`
95			`// 4) Added reset to Chip Select Output Registers`
96			`//`
97			`// 5) Forcing all outputs to Hi-Z state during reset`
98			`//`
99			`// Revision 1.1.1.1 2001/05/13 09:39:38 rudi`
100			`// Created Directory Structure`
101			`//`
102			`//`
103			`//`
104			`//`
105
106			`timescale 1ns / 10ps
107
108			`/////////////////////////////////////////////////////////////////////`
109			`//`
110			`// This define selects how the WISHBONE interface determines if`
111			`// the internal register file is selected.`
112			`// This should be a simple address decoder. "wb_addr_i" is the`
113			`// WISHBONE address bus (32 bits wide).`
114	11	rudi	//`define MC_REG_SEL (wb_addr_i[31:29] == 3'h6)
115			`define MC_REG_SEL (wb_addr_i[31:29] == 3'b011)
116	4	rudi
117			`// This define selects how the WISHBONE interface determines if`
118			`// the memory is selected.`
119			`// This should be a simple address decoder. "wb_addr_i" is the`
120			`// WISHBONE address bus (32 bits wide).`
121	8	rudi	`define MC_MEM_SEL (wb_addr_i[31:29] == 3'h0)
122	4	rudi
123			`/////////////////////////////////////////////////////////////////////`
124			`//`
125			`// This are the default Power-On Reset values for Chip Select`
126			`//`
127
128	16	rudi	`// This will be defined by the run script for my test bench ...`
129	19	rudi	//`define RUDIS_TB 1
130	16	rudi
131	4	rudi	`// Defines which chip select is used for Power On booting`
132
133	16	rudi	`// To run my default testbench default boot CS must be 3 !!!`
134			`ifdef RUDIS_TB
135			`define MC_DEF_SEL 3'h3
136			`else
137			`define MC_DEF_SEL 3'h0
138			`endif
139
140	4	rudi	`// Defines the default (reset) TMS value for the DEF_SEL chip select`
141	8	rudi	`define MC_DEF_POR_TMS 32'hffff_ffff
142	4	rudi
143
144			`/////////////////////////////////////////////////////////////////////`
145			`//`
146			`// Define how many Chip Selects to Implement`
147			`//`
148	8	rudi	`define MC_HAVE_CS1 1
149	11	rudi	//`define MC_HAVE_CS2 1
150			//`define MC_HAVE_CS3 1
151			//`define MC_HAVE_CS4 1
152			//`define MC_HAVE_CS5 1
153			//`define MC_HAVE_CS6 1
154			//`define MC_HAVE_CS7 1
155	4	rudi
156
157	16	rudi	`// To run my default testbench those need to there !!!`
158			`ifdef RUDIS_TB
159			`define MC_HAVE_CS2 1
160			`define MC_HAVE_CS3 1
161			`define MC_HAVE_CS4 1
162			`define MC_HAVE_CS5 1
163			`endif
164
165	4	rudi	`/////////////////////////////////////////////////////////////////////`
166			`//`
167			`// Init Refresh`
168			`//`
169			`// Number of Refresh Cycles to perform during SDRAM initialization.`
170			`// This varies between SDRAM manufacturer. Typically this value is`
171			`// between 2 and 8. This number must be smaller than 16.`
172	8	rudi	`define MC_INIT_RFRC_CNT 2
173	4	rudi
174			`/////////////////////////////////////////////////////////////////////`
175			`//`
176			`// Power On Delay`
177			`//`
178			`// Most if SDRAMs require some time to initialize before they can be used`
179			`// after power on. If the Memory Controller shall stall after power on to`
180			`// allow SDRAMs to finish the initialization process uncomment the below`
181			`// define statement`
182	8	rudi	`define MC_POR_DELAY 1
183	4	rudi
184			`// This value defines how many MEM_CLK cycles the Memory Controller should`
185			`// stall. Default is 2.5uS. At a 10nS MEM_CLK cycle time, this would 250`
186			`// cycles.`
187	8	rudi	`define MC_POR_DELAY_VAL 8'd250
188	4	rudi
189
190			`// ===============================================================`
191			`// ===============================================================`
192			`// Various internal defines (DO NOT MODIFY !)`
193			`// ===============================================================`
194			`// ===============================================================`
195
196			`// Register settings encodings`
197	8	rudi	`define MC_BW_8 2'h0
198			`define MC_BW_16 2'h1
199			`define MC_BW_32 2'h2
200	4	rudi
201	8	rudi	`define MC_MEM_TYPE_SDRAM 3'h0
202			`define MC_MEM_TYPE_SRAM 3'h1
203			`define MC_MEM_TYPE_ACS 3'h2
204			`define MC_MEM_TYPE_SCS 3'h3
205	4	rudi
206	8	rudi	`define MC_MEM_SIZE_64 2'h0
207			`define MC_MEM_SIZE_128 2'h1
208			`define MC_MEM_SIZE_256 2'h2
209
210			`// Command Valid, Ras_, Cas_, We_`
211			`define MC_CMD_NOP 4'b0111
212			`define MC_CMD_PC 4'b1010
213			`define MC_CMD_ACT 4'b1011
214			`define MC_CMD_WR 4'b1100
215			`define MC_CMD_RD 4'b1101
216			`define MC_CMD_BT 4'b1110
217			`define MC_CMD_ARFR 4'b1001
218			`define MC_CMD_LMR 4'b1000
219			`define MC_CMD_XRD 4'b1111
220			`define MC_CMD_XWR 4'b1110
221
222			`define MC_SINGLE_BANK 1'b0
223			`define MC_ALL_BANKS 1'b1
224

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[/] [mem_ctrl/] [trunk/] [rtl/] [verilog/] [mc_defines.v] - Blame information for rev 19