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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Memory Controller                                 ////
////  Memory Bus Interface                                       ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: mc_mem_if.v,v 1.3 2001-09-24 00:38:21 rudi Exp $
//
//  $Date: 2001-09-24 00:38:21 $
//  $Revision: 1.3 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.2  2001/09/02 02:28:28  rudi
//
//               Many fixes for minor bugs that showed up in gate level simulations.
//
//               Revision 1.1  2001/07/29 07:34:41  rudi
//
//
//               1) Changed Directory Structure
//               2) Fixed several minor bugs
//
//               Revision 1.3  2001/06/14 01:57:37  rudi
//
//
//               Fixed a potential bug in a corner case situation where the TMS register
//               does not propegate properly during initialisation.
//
//               Revision 1.2  2001/06/03 11:37:17  rudi
//
//
//               1) Fixed Chip Select Mask Register
//                      - Power On Value is now all ones
//                      - Comparison Logic is now correct
//
//               2) All resets are now asynchronous
//
//               3) Converted Power On Delay to an configurable item
//
//               4) Added reset to Chip Select Output Registers
//
//               5) Forcing all outputs to Hi-Z state during reset
//
//               Revision 1.1.1.1  2001/05/13 09:39:48  rudi
//               Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_mem_if(clk, rst, mc_clk, mc_br, mc_bg,
                mc_addr, mc_data_o, mc_dp_o, mc_data_oe,
                mc_dqm, mc_oe_, mc_we_, mc_cas_, mc_ras_, mc_cke_, mc_cs_,
                mc_adsc_, mc_adv_, mc_ack, mc_rp, mc_rp_d,
                mc_br_r, mc_bg_d, mc_data_od, mc_dp_od, mc_addr_d, mc_ack_r, we_,
                ras_, cas_, cke_, mc_adsc_d, mc_adv_d, cs_en, rfr_ack, cs_need_rfr,
                lmr_sel, spec_req_cs, cs, data_oe, susp_sel, mc_c_oe, oe_,
                wb_stb_i, wb_sel_i, wb_cycle, wr_cycle
                );
// Memory Interface
input           clk;
input           rst;
input           mc_clk;
input           mc_br;
output          mc_bg;
output  [23:0]   mc_addr;
output  [31:0]   mc_data_o;
output  [3:0]    mc_dp_o;
output          mc_data_oe;
output  [3:0]    mc_dqm;
output          mc_oe_;
output          mc_we_;
output          mc_cas_;
output          mc_ras_;
output          mc_cke_;
output  [7:0]    mc_cs_;
output          mc_adsc_;
output          mc_adv_;
input           mc_ack;
output          mc_rp;
 
// Internal Interface
output          mc_br_r;
input           mc_bg_d;
input           data_oe;
input           susp_sel;
input           mc_c_oe;
input   [31:0]   mc_data_od;
input   [3:0]    mc_dp_od;
input   [23:0]   mc_addr_d;
output          mc_ack_r;
input           wb_stb_i;
input   [3:0]    wb_sel_i;
input           wb_cycle;
input           wr_cycle;
input           oe_ ;
input           we_;
input           ras_;
input           cas_;
input           cke_;
input           cs_en;
input           rfr_ack;
input   [7:0]    cs_need_rfr;
input           lmr_sel;
input   [7:0]    spec_req_cs;
input   [7:0]    cs;
input           mc_adsc_d;
input           mc_adv_d;
input           mc_rp_d;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg             mc_data_oe;
reg     [31:0]   mc_data_o;
reg     [3:0]    mc_dp_o;
reg     [3:0]    mc_dqm;
reg     [3:0]    mc_dqm_r;
reg     [23:0]   mc_addr;
reg             mc_oe_;
reg             mc_we_;
reg             mc_cas_;
reg             mc_ras_;
wire            mc_cke_;
reg     [7:0]    mc_cs_;
reg             mc_bg;
reg             mc_adsc_;
reg             mc_adv_;
reg             mc_br_r;
reg             mc_ack_r;
reg             mc_rp;
 
//integer       n;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
always @(posedge mc_clk)
        mc_rp <= #1 mc_rp_d;
 
always @(posedge mc_clk)
        mc_br_r <= #1 mc_br;
 
always @(posedge mc_clk)
        mc_ack_r <= #1 mc_ack;
 
always @(posedge mc_clk)
        mc_bg <= #1 mc_bg_d;
 
always @(posedge mc_clk or posedge rst)
        if(rst)         mc_data_oe <= #1 1'b0;
        else            mc_data_oe <= #1 data_oe & !susp_sel & mc_c_oe;
 
always @(posedge mc_clk)
        mc_data_o <= #1 mc_data_od;
 
always @(posedge mc_clk)
        mc_dp_o <= #1 mc_dp_od;
 
always @(posedge mc_clk)
        mc_addr <= #1 mc_addr_d;
 
always @(posedge clk)
        if(wb_stb_i)
                mc_dqm_r <= #1 wb_sel_i;
 
always @(posedge mc_clk)
        mc_dqm <= #1    susp_sel ? 4'hf :
                        data_oe ? ~mc_dqm_r :
                        (wb_cycle & !wr_cycle) ? 4'h0 : 4'hf;
 
always @(posedge mc_clk or posedge rst)
        if(rst)         mc_oe_ <= #1 1'b1;
        else            mc_oe_ <= #1 oe_ | susp_sel;
 
always @(posedge mc_clk)
        mc_we_ <= #1 we_;
 
always @(posedge mc_clk)
        mc_cas_ <= #1 cas_;
 
always @(posedge mc_clk)
        mc_ras_ <= #1 ras_;
 
assign  mc_cke_ = cke_;
 
/*      Apparently Synopsys Can't handle this ....
always @(posedge mc_clk)
        for(n=0;n<8;n=n+1)
           mc_cs_[n] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[n] :
                                lmr_sel ? spec_req_cs[n] :
                                cs[n]
                        ));
*/
 
always @(posedge mc_clk or posedge rst)
        if(rst)         mc_cs_[0] <= #1 1'b1;
        else
        mc_cs_[0] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[0] :
                                lmr_sel ? spec_req_cs[0] :
                                cs[0]
                        ));
 
always @(posedge mc_clk or posedge rst)
        if(rst)         mc_cs_[1] <= #1 1'b1;
        else
           mc_cs_[1] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[1] :
                                lmr_sel ? spec_req_cs[1] :
                                cs[1]
                        ));
 
always @(posedge mc_clk or posedge rst)
        if(rst)         mc_cs_[2] <= #1 1'b1;
        else
           mc_cs_[2] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[2] :
                                lmr_sel ? spec_req_cs[2] :
                                cs[2]
                        ));
 
always @(posedge mc_clk or posedge rst)
        if(rst)         mc_cs_[3] <= #1 1'b1;
        else
           mc_cs_[3] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[3] :
                                lmr_sel ? spec_req_cs[3] :
                                cs[3]
                        ));
 
always @(posedge mc_clk or posedge rst)
        if(rst)         mc_cs_[4] <= #1 1'b1;
        else
           mc_cs_[4] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[4] :
                                lmr_sel ? spec_req_cs[4] :
                                cs[4]
                        ));
 
always @(posedge mc_clk or posedge rst)
        if(rst)         mc_cs_[5] <= #1 1'b1;
        else
           mc_cs_[5] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[5] :
                                lmr_sel ? spec_req_cs[5] :
                                cs[5]
                        ));
 
always @(posedge mc_clk or posedge rst)
        if(rst)         mc_cs_[6] <= #1 1'b1;
        else
           mc_cs_[6] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[6] :
                                lmr_sel ? spec_req_cs[6] :
                                cs[6]
                        ));
 
always @(posedge mc_clk or posedge rst)
        if(rst)         mc_cs_[7] <= #1 1'b1;
        else
           mc_cs_[7] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[7] :
                                lmr_sel ? spec_req_cs[7] :
                                cs[7]
                        ));
 
always @(posedge mc_clk)
        mc_adsc_ <= #1 ~mc_adsc_d;
 
always @(posedge mc_clk)
        mc_adv_  <= #1 ~mc_adv_d;
 
endmodule

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Memory Controller ////`
4			`//// Memory Bus Interface ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2000 Rudolf Usselmann ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41	12	rudi	`// $Id: mc_mem_if.v,v 1.3 2001-09-24 00:38:21 rudi Exp $`
42	4	rudi	`//`
43	12	rudi	`// $Date: 2001-09-24 00:38:21 $`
44			`// $Revision: 1.3 $`
45	4	rudi	`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51	12	rudi	`// Revision 1.2 2001/09/02 02:28:28 rudi`
52			`//`
53			`// Many fixes for minor bugs that showed up in gate level simulations.`
54			`//`
55	9	rudi	`// Revision 1.1 2001/07/29 07:34:41 rudi`
56			`//`
57			`//`
58			`// 1) Changed Directory Structure`
59			`// 2) Fixed several minor bugs`
60			`//`
61	4	rudi	`// Revision 1.3 2001/06/14 01:57:37 rudi`
62			`//`
63			`//`
64			`// Fixed a potential bug in a corner case situation where the TMS register`
65			`// does not propegate properly during initialisation.`
66			`//`
67			`// Revision 1.2 2001/06/03 11:37:17 rudi`
68			`//`
69			`//`
70			`// 1) Fixed Chip Select Mask Register`
71			`// - Power On Value is now all ones`
72			`// - Comparison Logic is now correct`
73			`//`
74			`// 2) All resets are now asynchronous`
75			`//`
76			`// 3) Converted Power On Delay to an configurable item`
77			`//`
78			`// 4) Added reset to Chip Select Output Registers`
79			`//`
80			`// 5) Forcing all outputs to Hi-Z state during reset`
81			`//`
82			`// Revision 1.1.1.1 2001/05/13 09:39:48 rudi`
83			`// Created Directory Structure`
84			`//`
85			`//`
86			`//`
87			`//`
88
89			`include "mc_defines.v"
90
91			`module mc_mem_if(clk, rst, mc_clk, mc_br, mc_bg,`
92			`mc_addr, mc_data_o, mc_dp_o, mc_data_oe,`
93			`mc_dqm, mc_oe_, mc_we_, mc_cas_, mc_ras_, mc_cke_, mc_cs_,`
94	9	rudi	`mc_adsc_, mc_adv_, mc_ack, mc_rp, mc_rp_d,`
95	4	rudi	`mc_br_r, mc_bg_d, mc_data_od, mc_dp_od, mc_addr_d, mc_ack_r, we_,`
96			`ras_, cas_, cke_, mc_adsc_d, mc_adv_d, cs_en, rfr_ack, cs_need_rfr,`
97			`lmr_sel, spec_req_cs, cs, data_oe, susp_sel, mc_c_oe, oe_,`
98			`wb_stb_i, wb_sel_i, wb_cycle, wr_cycle`
99			`);`
100			`// Memory Interface`
101			`input clk;`
102			`input rst;`
103			`input mc_clk;`
104			`input mc_br;`
105			`output mc_bg;`
106			`output [23:0] mc_addr;`
107			`output [31:0] mc_data_o;`
108			`output [3:0] mc_dp_o;`
109			`output mc_data_oe;`
110			`output [3:0] mc_dqm;`
111			`output mc_oe_;`
112			`output mc_we_;`
113			`output mc_cas_;`
114			`output mc_ras_;`
115			`output mc_cke_;`
116			`output [7:0] mc_cs_;`
117			`output mc_adsc_;`
118			`output mc_adv_;`
119			`input mc_ack;`
120	9	rudi	`output mc_rp;`
121	4	rudi
122			`// Internal Interface`
123			`output mc_br_r;`
124			`input mc_bg_d;`
125			`input data_oe;`
126			`input susp_sel;`
127			`input mc_c_oe;`
128			`input [31:0] mc_data_od;`
129			`input [3:0] mc_dp_od;`
130			`input [23:0] mc_addr_d;`
131			`output mc_ack_r;`
132			`input wb_stb_i;`
133			`input [3:0] wb_sel_i;`
134			`input wb_cycle;`
135			`input wr_cycle;`
136			`input oe_ ;`
137			`input we_;`
138			`input ras_;`
139			`input cas_;`
140			`input cke_;`
141			`input cs_en;`
142			`input rfr_ack;`
143			`input [7:0] cs_need_rfr;`
144			`input lmr_sel;`
145			`input [7:0] spec_req_cs;`
146			`input [7:0] cs;`
147			`input mc_adsc_d;`
148			`input mc_adv_d;`
149	9	rudi	`input mc_rp_d;`
150	4	rudi
151			`////////////////////////////////////////////////////////////////////`
152			`//`
153			`// Local Wires`
154			`//`
155
156			`reg mc_data_oe;`
157			`reg [31:0] mc_data_o;`
158			`reg [3:0] mc_dp_o;`
159			`reg [3:0] mc_dqm;`
160			`reg [3:0] mc_dqm_r;`
161			`reg [23:0] mc_addr;`
162			`reg mc_oe_;`
163			`reg mc_we_;`
164			`reg mc_cas_;`
165			`reg mc_ras_;`
166			`wire mc_cke_;`
167			`reg [7:0] mc_cs_;`
168			`reg mc_bg;`
169			`reg mc_adsc_;`
170			`reg mc_adv_;`
171			`reg mc_br_r;`
172			`reg mc_ack_r;`
173	9	rudi	`reg mc_rp;`
174	4	rudi
175			`//integer n;`
176
177			`////////////////////////////////////////////////////////////////////`
178			`//`
179			`// Misc Logic`
180			`//`
181
182			`always @(posedge mc_clk)`
183	9	rudi	`mc_rp <= #1 mc_rp_d;`
184
185			`always @(posedge mc_clk)`
186	4	rudi	`mc_br_r <= #1 mc_br;`
187
188			`always @(posedge mc_clk)`
189			`mc_ack_r <= #1 mc_ack;`
190
191			`always @(posedge mc_clk)`
192			`mc_bg <= #1 mc_bg_d;`
193
194	12	rudi	`always @(posedge mc_clk or posedge rst)`
195			`if(rst) mc_data_oe <= #1 1'b0;`
196			`else mc_data_oe <= #1 data_oe & !susp_sel & mc_c_oe;`
197	4	rudi
198			`always @(posedge mc_clk)`
199			`mc_data_o <= #1 mc_data_od;`
200
201			`always @(posedge mc_clk)`
202			`mc_dp_o <= #1 mc_dp_od;`
203
204			`always @(posedge mc_clk)`
205			`mc_addr <= #1 mc_addr_d;`
206
207			`always @(posedge clk)`
208			`if(wb_stb_i)`
209			`mc_dqm_r <= #1 wb_sel_i;`
210
211			`always @(posedge mc_clk)`
212			`mc_dqm <= #1 susp_sel ? 4'hf :`
213			`data_oe ? ~mc_dqm_r :`
214			`(wb_cycle & !wr_cycle) ? 4'h0 : 4'hf;`
215
216	12	rudi	`always @(posedge mc_clk or posedge rst)`
217			`if(rst) mc_oe_ <= #1 1'b1;`
218	4	rudi	`else mc_oe_ <= #1 oe_ \| susp_sel;`
219
220			`always @(posedge mc_clk)`
221			`mc_we_ <= #1 we_;`
222
223			`always @(posedge mc_clk)`
224			`mc_cas_ <= #1 cas_;`
225
226			`always @(posedge mc_clk)`
227			`mc_ras_ <= #1 ras_;`
228
229			`assign mc_cke_ = cke_;`
230
231			`/* Apparently Synopsys Can't handle this ....`
232			`always @(posedge mc_clk)`
233			`for(n=0;n<8;n=n+1)`
234			`mc_cs_[n] <= #1 ~(cs_en & (`
235			`(rfr_ack \| susp_sel) ? cs_need_rfr[n] :`
236			`lmr_sel ? spec_req_cs[n] :`
237			`cs[n]`
238			`));`
239			`*/`
240
241	12	rudi	`always @(posedge mc_clk or posedge rst)`
242			`if(rst) mc_cs_[0] <= #1 1'b1;`
243	4	rudi	`else`
244			`mc_cs_[0] <= #1 ~(cs_en & (`
245			`(rfr_ack \| susp_sel) ? cs_need_rfr[0] :`
246			`lmr_sel ? spec_req_cs[0] :`
247			`cs[0]`
248			`));`
249
250	12	rudi	`always @(posedge mc_clk or posedge rst)`
251			`if(rst) mc_cs_[1] <= #1 1'b1;`
252	4	rudi	`else`
253			`mc_cs_[1] <= #1 ~(cs_en & (`
254			`(rfr_ack \| susp_sel) ? cs_need_rfr[1] :`
255			`lmr_sel ? spec_req_cs[1] :`
256			`cs[1]`
257			`));`
258
259	12	rudi	`always @(posedge mc_clk or posedge rst)`
260			`if(rst) mc_cs_[2] <= #1 1'b1;`
261	4	rudi	`else`
262			`mc_cs_[2] <= #1 ~(cs_en & (`
263			`(rfr_ack \| susp_sel) ? cs_need_rfr[2] :`
264			`lmr_sel ? spec_req_cs[2] :`
265			`cs[2]`
266			`));`
267
268	12	rudi	`always @(posedge mc_clk or posedge rst)`
269			`if(rst) mc_cs_[3] <= #1 1'b1;`
270	4	rudi	`else`
271			`mc_cs_[3] <= #1 ~(cs_en & (`
272			`(rfr_ack \| susp_sel) ? cs_need_rfr[3] :`
273			`lmr_sel ? spec_req_cs[3] :`
274			`cs[3]`
275			`));`
276
277	12	rudi	`always @(posedge mc_clk or posedge rst)`
278			`if(rst) mc_cs_[4] <= #1 1'b1;`
279	4	rudi	`else`
280			`mc_cs_[4] <= #1 ~(cs_en & (`
281			`(rfr_ack \| susp_sel) ? cs_need_rfr[4] :`
282			`lmr_sel ? spec_req_cs[4] :`
283			`cs[4]`
284			`));`
285
286	12	rudi	`always @(posedge mc_clk or posedge rst)`
287			`if(rst) mc_cs_[5] <= #1 1'b1;`
288	4	rudi	`else`
289			`mc_cs_[5] <= #1 ~(cs_en & (`
290			`(rfr_ack \| susp_sel) ? cs_need_rfr[5] :`
291			`lmr_sel ? spec_req_cs[5] :`
292			`cs[5]`
293			`));`
294
295	12	rudi	`always @(posedge mc_clk or posedge rst)`
296			`if(rst) mc_cs_[6] <= #1 1'b1;`
297	4	rudi	`else`
298			`mc_cs_[6] <= #1 ~(cs_en & (`
299			`(rfr_ack \| susp_sel) ? cs_need_rfr[6] :`
300			`lmr_sel ? spec_req_cs[6] :`
301			`cs[6]`
302			`));`
303
304	12	rudi	`always @(posedge mc_clk or posedge rst)`
305			`if(rst) mc_cs_[7] <= #1 1'b1;`
306	4	rudi	`else`
307			`mc_cs_[7] <= #1 ~(cs_en & (`
308			`(rfr_ack \| susp_sel) ? cs_need_rfr[7] :`
309			`lmr_sel ? spec_req_cs[7] :`
310			`cs[7]`
311			`));`
312
313			`always @(posedge mc_clk)`
314			`mc_adsc_ <= #1 ~mc_adsc_d;`
315
316			`always @(posedge mc_clk)`
317			`mc_adv_ <= #1 ~mc_adv_d;`
318
319			`endmodule`

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[/] [mem_ctrl/] [trunk/] [rtl/] [verilog/] [mc_mem_if.v] - Blame information for rev 12