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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Memory Controller                                 ////
////  Open Bank & Row Tracking Block Top Level                   ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: mc_obct_top.v,v 1.3 2001-12-21 05:09:29 rudi Exp $
//
//  $Date: 2001-12-21 05:09:29 $
//  $Revision: 1.3 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.2  2001/08/10 08:16:21  rudi
//
//               - Changed IO names to be more clear.
//               - Uniquifyed define names to be core specific.
//               - Removed "Refresh Early" configuration
//
//               Revision 1.1  2001/07/29 07:34:41  rudi
//
//
//               1) Changed Directory Structure
//               2) Fixed several minor bugs
//
//               Revision 1.1.1.1  2001/05/13 09:39:47  rudi
//               Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_obct_top(clk, rst, cs, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all,
                bank_open, any_bank_open, row_same, rfr_ack);
input           clk, rst;
input   [7:0]    cs;
input   [12:0]   row_adr;
input   [1:0]    bank_adr;
input           bank_set;
input           bank_clr;
input           bank_clr_all;
output          bank_open;
output          any_bank_open;
output          row_same;
input           rfr_ack;
 
////////////////////////////////////////////////////////////////////
//
// Local Registers & Wires
//
 
reg             bank_open;
reg             row_same;
reg             any_bank_open;
 
wire            bank_set_0;
wire            bank_clr_0;
wire            bank_clr_all_0;
wire            bank_open_0;
wire            row_same_0;
wire            any_bank_open_0;
 
wire            bank_set_1;
wire            bank_clr_1;
wire            bank_clr_all_1;
wire            bank_open_1;
wire            row_same_1;
wire            any_bank_open_1;
 
wire            bank_set_2;
wire            bank_clr_2;
wire            bank_clr_all_2;
wire            bank_open_2;
wire            row_same_2;
wire            any_bank_open_2;
 
wire            bank_set_3;
wire            bank_clr_3;
wire            bank_clr_all_3;
wire            bank_open_3;
wire            row_same_3;
wire            any_bank_open_3;
 
wire            bank_set_4;
wire            bank_clr_4;
wire            bank_clr_all_4;
wire            bank_open_4;
wire            row_same_4;
wire            any_bank_open_4;
 
wire            bank_set_5;
wire            bank_clr_5;
wire            bank_clr_all_5;
wire            bank_open_5;
wire            row_same_5;
wire            any_bank_open_5;
 
wire            bank_set_6;
wire            bank_clr_6;
wire            bank_clr_all_6;
wire            bank_open_6;
wire            row_same_6;
wire            any_bank_open_6;
 
wire            bank_set_7;
wire            bank_clr_7;
wire            bank_clr_all_7;
wire            bank_open_7;
wire            row_same_7;
wire            any_bank_open_7;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign bank_set_0 = cs[0] & bank_set;
assign bank_set_1 = cs[1] & bank_set;
assign bank_set_2 = cs[2] & bank_set;
assign bank_set_3 = cs[3] & bank_set;
assign bank_set_4 = cs[4] & bank_set;
assign bank_set_5 = cs[5] & bank_set;
assign bank_set_6 = cs[6] & bank_set;
assign bank_set_7 = cs[7] & bank_set;
 
assign bank_clr_0 = cs[0] & bank_clr;
assign bank_clr_1 = cs[1] & bank_clr;
assign bank_clr_2 = cs[2] & bank_clr;
assign bank_clr_3 = cs[3] & bank_clr;
assign bank_clr_4 = cs[4] & bank_clr;
assign bank_clr_5 = cs[5] & bank_clr;
assign bank_clr_6 = cs[6] & bank_clr;
assign bank_clr_7 = cs[7] & bank_clr;
 
assign bank_clr_all_0 = (cs[0] & bank_clr_all) | rfr_ack;
assign bank_clr_all_1 = (cs[1] & bank_clr_all) | rfr_ack;
assign bank_clr_all_2 = (cs[2] & bank_clr_all) | rfr_ack;
assign bank_clr_all_3 = (cs[3] & bank_clr_all) | rfr_ack;
assign bank_clr_all_4 = (cs[4] & bank_clr_all) | rfr_ack;
assign bank_clr_all_5 = (cs[5] & bank_clr_all) | rfr_ack;
assign bank_clr_all_6 = (cs[6] & bank_clr_all) | rfr_ack;
assign bank_clr_all_7 = (cs[7] & bank_clr_all) | rfr_ack;
 
always @(posedge clk)
        bank_open <= #1 (cs[0] & bank_open_0) | (cs[1] & bank_open_1) |
                        (cs[2] & bank_open_2) | (cs[3] & bank_open_3) |
                        (cs[4] & bank_open_4) | (cs[5] & bank_open_5) |
                        (cs[6] & bank_open_6) | (cs[7] & bank_open_7);
 
always @(posedge clk)
        row_same <= #1  (cs[0] & row_same_0) | (cs[1] & row_same_1) |
                        (cs[2] & row_same_2) | (cs[3] & row_same_3) |
                        (cs[4] & row_same_4) | (cs[5] & row_same_5) |
                        (cs[6] & row_same_6) | (cs[7] & row_same_7);
 
always @(posedge clk)
        any_bank_open <= #1     (cs[0] & any_bank_open_0) | (cs[1] & any_bank_open_1) |
                                (cs[2] & any_bank_open_2) | (cs[3] & any_bank_open_3) |
                                (cs[4] & any_bank_open_4) | (cs[5] & any_bank_open_5) |
                                (cs[6] & any_bank_open_6) | (cs[7] & any_bank_open_7);
 
 
////////////////////////////////////////////////////////////////////
//
// OBCT Modules for each Chip Select
//
 
mc_obct u0(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_0      ),
                .bank_clr(      bank_clr_0      ),
                .bank_clr_all(  bank_clr_all_0  ),
                .bank_open(     bank_open_0     ),
                .any_bank_open( any_bank_open_0 ),
                .row_same(      row_same_0      )
                );
 
`ifdef MC_HAVE_CS1
mc_obct u1(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_1      ),
                .bank_clr(      bank_clr_1      ),
                .bank_clr_all(  bank_clr_all_1  ),
                .bank_open(     bank_open_1     ),
                .any_bank_open( any_bank_open_1 ),
                .row_same(      row_same_1      )
                );
`else
mc_obct_dummy   u1(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_1      ),
                .bank_clr(      bank_clr_1      ),
                .bank_clr_all(  bank_clr_all_1  ),
                .bank_open(     bank_open_1     ),
                .any_bank_open( any_bank_open_1 ),
                .row_same(      row_same_1      )
                );
`endif
 
`ifdef MC_HAVE_CS2
mc_obct u2(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_2      ),
                .bank_clr(      bank_clr_2      ),
                .bank_clr_all(  bank_clr_all_2  ),
                .bank_open(     bank_open_2     ),
                .any_bank_open( any_bank_open_2 ),
                .row_same(      row_same_2      )
                );
`else
mc_obct_dummy   u2(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_2      ),
                .bank_clr(      bank_clr_2      ),
                .bank_clr_all(  bank_clr_all_2  ),
                .bank_open(     bank_open_2     ),
                .any_bank_open( any_bank_open_2 ),
                .row_same(      row_same_2      )
                );
`endif
 
`ifdef MC_HAVE_CS3
mc_obct u3(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_3      ),
                .bank_clr(      bank_clr_3      ),
                .bank_clr_all(  bank_clr_all_3  ),
                .bank_open(     bank_open_3     ),
                .any_bank_open( any_bank_open_3 ),
                .row_same(      row_same_3      )
                );
`else
mc_obct_dummy   u3(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_3      ),
                .bank_clr(      bank_clr_3      ),
                .bank_clr_all(  bank_clr_all_3  ),
                .bank_open(     bank_open_3     ),
                .any_bank_open( any_bank_open_3 ),
                .row_same(      row_same_3      )
                );
`endif
 
`ifdef MC_HAVE_CS4
mc_obct u4(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_4      ),
                .bank_clr(      bank_clr_4      ),
                .bank_clr_all(  bank_clr_all_4  ),
                .bank_open(     bank_open_4     ),
                .any_bank_open( any_bank_open_4 ),
                .row_same(      row_same_4      )
                );
`else
mc_obct_dummy   u4(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_4      ),
                .bank_clr(      bank_clr_4      ),
                .bank_clr_all(  bank_clr_all_4  ),
                .bank_open(     bank_open_4     ),
                .any_bank_open( any_bank_open_4 ),
                .row_same(      row_same_4      )
                );
`endif
 
`ifdef MC_HAVE_CS5
mc_obct u5(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_5      ),
                .bank_clr(      bank_clr_5      ),
                .bank_clr_all(  bank_clr_all_5  ),
                .bank_open(     bank_open_5     ),
                .any_bank_open( any_bank_open_5 ),
                .row_same(      row_same_5      )
                );
`else
mc_obct_dummy   u5(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_5      ),
                .bank_clr(      bank_clr_5      ),
                .bank_clr_all(  bank_clr_all_5  ),
                .bank_open(     bank_open_5     ),
                .any_bank_open( any_bank_open_5 ),
                .row_same(      row_same_5      )
                );
`endif
 
`ifdef MC_HAVE_CS6
mc_obct u6(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_6      ),
                .bank_clr(      bank_clr_6      ),
                .bank_clr_all(  bank_clr_all_6  ),
                .bank_open(     bank_open_6     ),
                .any_bank_open( any_bank_open_6 ),
                .row_same(      row_same_6      )
                );
`else
mc_obct_dummy   u6(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_6      ),
                .bank_clr(      bank_clr_6      ),
                .bank_clr_all(  bank_clr_all_6  ),
                .bank_open(     bank_open_6     ),
                .any_bank_open( any_bank_open_6 ),
                .row_same(      row_same_6      )
                );
`endif
 
`ifdef MC_HAVE_CS7
mc_obct u7(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_7      ),
                .bank_clr(      bank_clr_7      ),
                .bank_clr_all(  bank_clr_all_7  ),
                .bank_open(     bank_open_7     ),
                .any_bank_open( any_bank_open_7 ),
                .row_same(      row_same_7      )
                );
`else
mc_obct_dummy   u7(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_7      ),
                .bank_clr(      bank_clr_7      ),
                .bank_clr_all(  bank_clr_all_7  ),
                .bank_open(     bank_open_7     ),
                .any_bank_open( any_bank_open_7 ),
                .row_same(      row_same_7      )
                );
`endif
 
endmodule

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Memory Controller ////`
4			`//// Open Bank & Row Tracking Block Top Level ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2000 Rudolf Usselmann ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41	20	rudi	`// $Id: mc_obct_top.v,v 1.3 2001-12-21 05:09:29 rudi Exp $`
42	4	rudi	`//`
43	20	rudi	`// $Date: 2001-12-21 05:09:29 $`
44			`// $Revision: 1.3 $`
45	4	rudi	`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51	20	rudi	`// Revision 1.2 2001/08/10 08:16:21 rudi`
52			`//`
53			`// - Changed IO names to be more clear.`
54			`// - Uniquifyed define names to be core specific.`
55			`// - Removed "Refresh Early" configuration`
56			`//`
57	8	rudi	`// Revision 1.1 2001/07/29 07:34:41 rudi`
58			`//`
59			`//`
60			`// 1) Changed Directory Structure`
61			`// 2) Fixed several minor bugs`
62			`//`
63	4	rudi	`// Revision 1.1.1.1 2001/05/13 09:39:47 rudi`
64			`// Created Directory Structure`
65			`//`
66			`//`
67			`//`
68			`//`
69
70			`include "mc_defines.v"
71
72			`module mc_obct_top(clk, rst, cs, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all,`
73			`bank_open, any_bank_open, row_same, rfr_ack);`
74			`input clk, rst;`
75			`input [7:0] cs;`
76			`input [12:0] row_adr;`
77			`input [1:0] bank_adr;`
78			`input bank_set;`
79			`input bank_clr;`
80			`input bank_clr_all;`
81			`output bank_open;`
82			`output any_bank_open;`
83			`output row_same;`
84			`input rfr_ack;`
85
86			`////////////////////////////////////////////////////////////////////`
87			`//`
88			`// Local Registers & Wires`
89			`//`
90
91			`reg bank_open;`
92			`reg row_same;`
93			`reg any_bank_open;`
94
95			`wire bank_set_0;`
96			`wire bank_clr_0;`
97			`wire bank_clr_all_0;`
98			`wire bank_open_0;`
99			`wire row_same_0;`
100			`wire any_bank_open_0;`
101
102			`wire bank_set_1;`
103			`wire bank_clr_1;`
104			`wire bank_clr_all_1;`
105			`wire bank_open_1;`
106			`wire row_same_1;`
107			`wire any_bank_open_1;`
108
109			`wire bank_set_2;`
110			`wire bank_clr_2;`
111			`wire bank_clr_all_2;`
112			`wire bank_open_2;`
113			`wire row_same_2;`
114			`wire any_bank_open_2;`
115
116			`wire bank_set_3;`
117			`wire bank_clr_3;`
118			`wire bank_clr_all_3;`
119			`wire bank_open_3;`
120			`wire row_same_3;`
121			`wire any_bank_open_3;`
122
123			`wire bank_set_4;`
124			`wire bank_clr_4;`
125			`wire bank_clr_all_4;`
126			`wire bank_open_4;`
127			`wire row_same_4;`
128			`wire any_bank_open_4;`
129
130			`wire bank_set_5;`
131			`wire bank_clr_5;`
132			`wire bank_clr_all_5;`
133			`wire bank_open_5;`
134			`wire row_same_5;`
135			`wire any_bank_open_5;`
136
137			`wire bank_set_6;`
138			`wire bank_clr_6;`
139			`wire bank_clr_all_6;`
140			`wire bank_open_6;`
141			`wire row_same_6;`
142			`wire any_bank_open_6;`
143
144			`wire bank_set_7;`
145			`wire bank_clr_7;`
146			`wire bank_clr_all_7;`
147			`wire bank_open_7;`
148			`wire row_same_7;`
149			`wire any_bank_open_7;`
150
151			`////////////////////////////////////////////////////////////////////`
152			`//`
153			`// Misc Logic`
154			`//`
155
156			`assign bank_set_0 = cs[0] & bank_set;`
157			`assign bank_set_1 = cs[1] & bank_set;`
158			`assign bank_set_2 = cs[2] & bank_set;`
159			`assign bank_set_3 = cs[3] & bank_set;`
160			`assign bank_set_4 = cs[4] & bank_set;`
161			`assign bank_set_5 = cs[5] & bank_set;`
162			`assign bank_set_6 = cs[6] & bank_set;`
163			`assign bank_set_7 = cs[7] & bank_set;`
164
165			`assign bank_clr_0 = cs[0] & bank_clr;`
166			`assign bank_clr_1 = cs[1] & bank_clr;`
167			`assign bank_clr_2 = cs[2] & bank_clr;`
168			`assign bank_clr_3 = cs[3] & bank_clr;`
169			`assign bank_clr_4 = cs[4] & bank_clr;`
170			`assign bank_clr_5 = cs[5] & bank_clr;`
171			`assign bank_clr_6 = cs[6] & bank_clr;`
172			`assign bank_clr_7 = cs[7] & bank_clr;`
173
174			`assign bank_clr_all_0 = (cs[0] & bank_clr_all) \| rfr_ack;`
175			`assign bank_clr_all_1 = (cs[1] & bank_clr_all) \| rfr_ack;`
176			`assign bank_clr_all_2 = (cs[2] & bank_clr_all) \| rfr_ack;`
177			`assign bank_clr_all_3 = (cs[3] & bank_clr_all) \| rfr_ack;`
178			`assign bank_clr_all_4 = (cs[4] & bank_clr_all) \| rfr_ack;`
179			`assign bank_clr_all_5 = (cs[5] & bank_clr_all) \| rfr_ack;`
180			`assign bank_clr_all_6 = (cs[6] & bank_clr_all) \| rfr_ack;`
181			`assign bank_clr_all_7 = (cs[7] & bank_clr_all) \| rfr_ack;`
182
183			`always @(posedge clk)`
184			`bank_open <= #1 (cs[0] & bank_open_0) \| (cs[1] & bank_open_1) \|`
185			`(cs[2] & bank_open_2) \| (cs[3] & bank_open_3) \|`
186			`(cs[4] & bank_open_4) \| (cs[5] & bank_open_5) \|`
187			`(cs[6] & bank_open_6) \| (cs[7] & bank_open_7);`
188
189			`always @(posedge clk)`
190			`row_same <= #1 (cs[0] & row_same_0) \| (cs[1] & row_same_1) \|`
191			`(cs[2] & row_same_2) \| (cs[3] & row_same_3) \|`
192			`(cs[4] & row_same_4) \| (cs[5] & row_same_5) \|`
193			`(cs[6] & row_same_6) \| (cs[7] & row_same_7);`
194
195			`always @(posedge clk)`
196			`any_bank_open <= #1 (cs[0] & any_bank_open_0) \| (cs[1] & any_bank_open_1) \|`
197			`(cs[2] & any_bank_open_2) \| (cs[3] & any_bank_open_3) \|`
198			`(cs[4] & any_bank_open_4) \| (cs[5] & any_bank_open_5) \|`
199			`(cs[6] & any_bank_open_6) \| (cs[7] & any_bank_open_7);`
200
201	20	rudi
202	4	rudi	`////////////////////////////////////////////////////////////////////`
203			`//`
204			`// OBCT Modules for each Chip Select`
205			`//`
206
207			`mc_obct u0(`
208			`.clk( clk ),`
209			`.rst( rst ),`
210			`.row_adr( row_adr ),`
211			`.bank_adr( bank_adr ),`
212			`.bank_set( bank_set_0 ),`
213			`.bank_clr( bank_clr_0 ),`
214			`.bank_clr_all( bank_clr_all_0 ),`
215			`.bank_open( bank_open_0 ),`
216			`.any_bank_open( any_bank_open_0 ),`
217			`.row_same( row_same_0 )`
218			`);`
219
220	8	rudi	`ifdef MC_HAVE_CS1
221	4	rudi	`mc_obct u1(`
222			`.clk( clk ),`
223			`.rst( rst ),`
224			`.row_adr( row_adr ),`
225			`.bank_adr( bank_adr ),`
226			`.bank_set( bank_set_1 ),`
227			`.bank_clr( bank_clr_1 ),`
228			`.bank_clr_all( bank_clr_all_1 ),`
229			`.bank_open( bank_open_1 ),`
230			`.any_bank_open( any_bank_open_1 ),`
231			`.row_same( row_same_1 )`
232			`);`
233			`else
234			`mc_obct_dummy u1(`
235			`.clk( clk ),`
236			`.rst( rst ),`
237			`.row_adr( row_adr ),`
238			`.bank_adr( bank_adr ),`
239			`.bank_set( bank_set_1 ),`
240			`.bank_clr( bank_clr_1 ),`
241			`.bank_clr_all( bank_clr_all_1 ),`
242			`.bank_open( bank_open_1 ),`
243			`.any_bank_open( any_bank_open_1 ),`
244			`.row_same( row_same_1 )`
245			`);`
246			`endif
247
248	8	rudi	`ifdef MC_HAVE_CS2
249	4	rudi	`mc_obct u2(`
250			`.clk( clk ),`
251			`.rst( rst ),`
252			`.row_adr( row_adr ),`
253			`.bank_adr( bank_adr ),`
254			`.bank_set( bank_set_2 ),`
255			`.bank_clr( bank_clr_2 ),`
256			`.bank_clr_all( bank_clr_all_2 ),`
257			`.bank_open( bank_open_2 ),`
258			`.any_bank_open( any_bank_open_2 ),`
259			`.row_same( row_same_2 )`
260			`);`
261			`else
262			`mc_obct_dummy u2(`
263			`.clk( clk ),`
264			`.rst( rst ),`
265			`.row_adr( row_adr ),`
266			`.bank_adr( bank_adr ),`
267			`.bank_set( bank_set_2 ),`
268			`.bank_clr( bank_clr_2 ),`
269			`.bank_clr_all( bank_clr_all_2 ),`
270			`.bank_open( bank_open_2 ),`
271			`.any_bank_open( any_bank_open_2 ),`
272			`.row_same( row_same_2 )`
273			`);`
274			`endif
275
276	8	rudi	`ifdef MC_HAVE_CS3
277	4	rudi	`mc_obct u3(`
278			`.clk( clk ),`
279			`.rst( rst ),`
280			`.row_adr( row_adr ),`
281			`.bank_adr( bank_adr ),`
282			`.bank_set( bank_set_3 ),`
283			`.bank_clr( bank_clr_3 ),`
284			`.bank_clr_all( bank_clr_all_3 ),`
285			`.bank_open( bank_open_3 ),`
286			`.any_bank_open( any_bank_open_3 ),`
287			`.row_same( row_same_3 )`
288			`);`
289			`else
290			`mc_obct_dummy u3(`
291			`.clk( clk ),`
292			`.rst( rst ),`
293			`.row_adr( row_adr ),`
294			`.bank_adr( bank_adr ),`
295			`.bank_set( bank_set_3 ),`
296			`.bank_clr( bank_clr_3 ),`
297			`.bank_clr_all( bank_clr_all_3 ),`
298			`.bank_open( bank_open_3 ),`
299			`.any_bank_open( any_bank_open_3 ),`
300			`.row_same( row_same_3 )`
301			`);`
302			`endif
303
304	8	rudi	`ifdef MC_HAVE_CS4
305	4	rudi	`mc_obct u4(`
306			`.clk( clk ),`
307			`.rst( rst ),`
308			`.row_adr( row_adr ),`
309			`.bank_adr( bank_adr ),`
310			`.bank_set( bank_set_4 ),`
311			`.bank_clr( bank_clr_4 ),`
312			`.bank_clr_all( bank_clr_all_4 ),`
313			`.bank_open( bank_open_4 ),`
314			`.any_bank_open( any_bank_open_4 ),`
315			`.row_same( row_same_4 )`
316			`);`
317			`else
318			`mc_obct_dummy u4(`
319			`.clk( clk ),`
320			`.rst( rst ),`
321			`.row_adr( row_adr ),`
322			`.bank_adr( bank_adr ),`
323			`.bank_set( bank_set_4 ),`
324			`.bank_clr( bank_clr_4 ),`
325			`.bank_clr_all( bank_clr_all_4 ),`
326			`.bank_open( bank_open_4 ),`
327			`.any_bank_open( any_bank_open_4 ),`
328			`.row_same( row_same_4 )`
329			`);`
330			`endif
331
332	8	rudi	`ifdef MC_HAVE_CS5
333	4	rudi	`mc_obct u5(`
334			`.clk( clk ),`
335			`.rst( rst ),`
336			`.row_adr( row_adr ),`
337			`.bank_adr( bank_adr ),`
338			`.bank_set( bank_set_5 ),`
339			`.bank_clr( bank_clr_5 ),`
340			`.bank_clr_all( bank_clr_all_5 ),`
341			`.bank_open( bank_open_5 ),`
342			`.any_bank_open( any_bank_open_5 ),`
343			`.row_same( row_same_5 )`
344			`);`
345			`else
346			`mc_obct_dummy u5(`
347			`.clk( clk ),`
348			`.rst( rst ),`
349			`.row_adr( row_adr ),`
350			`.bank_adr( bank_adr ),`
351			`.bank_set( bank_set_5 ),`
352			`.bank_clr( bank_clr_5 ),`
353			`.bank_clr_all( bank_clr_all_5 ),`
354			`.bank_open( bank_open_5 ),`
355			`.any_bank_open( any_bank_open_5 ),`
356			`.row_same( row_same_5 )`
357			`);`
358			`endif
359
360	8	rudi	`ifdef MC_HAVE_CS6
361	4	rudi	`mc_obct u6(`
362			`.clk( clk ),`
363			`.rst( rst ),`
364			`.row_adr( row_adr ),`
365			`.bank_adr( bank_adr ),`
366			`.bank_set( bank_set_6 ),`
367			`.bank_clr( bank_clr_6 ),`
368			`.bank_clr_all( bank_clr_all_6 ),`
369			`.bank_open( bank_open_6 ),`
370			`.any_bank_open( any_bank_open_6 ),`
371			`.row_same( row_same_6 )`
372			`);`
373			`else
374			`mc_obct_dummy u6(`
375			`.clk( clk ),`
376			`.rst( rst ),`
377			`.row_adr( row_adr ),`
378			`.bank_adr( bank_adr ),`
379			`.bank_set( bank_set_6 ),`
380			`.bank_clr( bank_clr_6 ),`
381			`.bank_clr_all( bank_clr_all_6 ),`
382			`.bank_open( bank_open_6 ),`
383			`.any_bank_open( any_bank_open_6 ),`
384			`.row_same( row_same_6 )`
385			`);`
386			`endif
387
388	8	rudi	`ifdef MC_HAVE_CS7
389	4	rudi	`mc_obct u7(`
390			`.clk( clk ),`
391			`.rst( rst ),`
392			`.row_adr( row_adr ),`
393			`.bank_adr( bank_adr ),`
394			`.bank_set( bank_set_7 ),`
395			`.bank_clr( bank_clr_7 ),`
396			`.bank_clr_all( bank_clr_all_7 ),`
397			`.bank_open( bank_open_7 ),`
398			`.any_bank_open( any_bank_open_7 ),`
399			`.row_same( row_same_7 )`
400			`);`
401			`else
402			`mc_obct_dummy u7(`
403			`.clk( clk ),`
404			`.rst( rst ),`
405			`.row_adr( row_adr ),`
406			`.bank_adr( bank_adr ),`
407			`.bank_set( bank_set_7 ),`
408			`.bank_clr( bank_clr_7 ),`
409			`.bank_clr_all( bank_clr_all_7 ),`
410			`.bank_open( bank_open_7 ),`
411			`.any_bank_open( any_bank_open_7 ),`
412			`.row_same( row_same_7 )`
413			`);`
414			`endif
415
416			`endmodule`

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