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[/] [mem_ctrl/] [trunk/] [rtl/] [verilog/] [mc_rd_fifo.v] - Blame information for rev 18

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Memory Controller                                 ////
////  Read FIFO                                                  ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: mc_rd_fifo.v,v 1.3 2001-12-11 02:47:19 rudi Exp $
//
//  $Date: 2001-12-11 02:47:19 $
//  $Revision: 1.3 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.2  2001/11/29 02:16:28  rudi
//
//
//               - More Synthesis cleanup, mostly for speed
//               - Several bug fixes
//               - Changed code to avoid auto-precharge and
//                 burst-terminate combinations (apparently illegal ?)
//                 Now we will do a manual precharge ...
//
//               Revision 1.1  2001/07/29 07:34:41  rudi
//
//
//               1) Changed Directory Structure
//               2) Fixed several minor bugs
//
//               Revision 1.1.1.1  2001/05/13 09:39:44  rudi
//               Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_rd_fifo(clk, rst, clr, din, we, dout, re);
 
input           clk, rst, clr;
input   [35:0]   din;
input           we;
output  [35:0]   dout;
input           re;
 
reg     [3:0]    rd_adr, wr_adr;
reg     [35:0]   r0, r1, r2, r3;
reg     [35:0]   dout;
 
always @(posedge clk or posedge rst)
        if(rst)         rd_adr <= #1 4'h1;
        else
        if(clr)         rd_adr <= #1 4'h1;
        else
        if(re)          rd_adr <= #1 {rd_adr[2:0], rd_adr[3]};
 
always @(posedge clk or posedge rst)
        if(rst)         wr_adr <= #1 4'h1;
        else
        if(clr)         wr_adr <= #1 4'h1;
        else
        if(we)          wr_adr <= #1 {wr_adr[2:0], wr_adr[3]};
 
always @(posedge clk)
        if(we & wr_adr[0])       r0 <= #1 din;
 
always @(posedge clk)
        if(we & wr_adr[1])      r1 <= #1 din;
 
always @(posedge clk)
        if(we & wr_adr[2])      r2 <= #1 din;
 
always @(posedge clk)
        if(we & wr_adr[3])      r3 <= #1 din;
 
always @(rd_adr or r0 or r1 or r2 or r3 or re or we or din)
        case(rd_adr)            // synopsys full_case parallel_case
           4'h1:        dout = r0;
           4'h2:        dout = r1;
           4'h4:        dout = r2;
           4'h8:        dout = r3;
        endcase
 
endmodule

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Memory Controller ////`
4			`//// Read FIFO ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2000 Rudolf Usselmann ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41	18	rudi	`// $Id: mc_rd_fifo.v,v 1.3 2001-12-11 02:47:19 rudi Exp $`
42	4	rudi	`//`
43	18	rudi	`// $Date: 2001-12-11 02:47:19 $`
44			`// $Revision: 1.3 $`
45	4	rudi	`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51	18	rudi	`// Revision 1.2 2001/11/29 02:16:28 rudi`
52			`//`
53			`//`
54			`// - More Synthesis cleanup, mostly for speed`
55			`// - Several bug fixes`
56			`// - Changed code to avoid auto-precharge and`
57			`// burst-terminate combinations (apparently illegal ?)`
58			`// Now we will do a manual precharge ...`
59			`//`
60	16	rudi	`// Revision 1.1 2001/07/29 07:34:41 rudi`
61			`//`
62			`//`
63			`// 1) Changed Directory Structure`
64			`// 2) Fixed several minor bugs`
65			`//`
66	4	rudi	`// Revision 1.1.1.1 2001/05/13 09:39:44 rudi`
67			`// Created Directory Structure`
68			`//`
69			`//`
70			`//`
71			`//`
72
73			`include "mc_defines.v"
74
75	18	rudi	`module mc_rd_fifo(clk, rst, clr, din, we, dout, re);`
76	4	rudi
77	18	rudi	`input clk, rst, clr;`
78	4	rudi	`input [35:0] din;`
79			`input we;`
80			`output [35:0] dout;`
81			`input re;`
82
83			`reg [3:0] rd_adr, wr_adr;`
84			`reg [35:0] r0, r1, r2, r3;`
85			`reg [35:0] dout;`
86
87	18	rudi	`always @(posedge clk or posedge rst)`
88			`if(rst) rd_adr <= #1 4'h1;`
89	4	rudi	`else`
90	18	rudi	`if(clr) rd_adr <= #1 4'h1;`
91			`else`
92	4	rudi	`if(re) rd_adr <= #1 {rd_adr[2:0], rd_adr[3]};`
93
94	18	rudi	`always @(posedge clk or posedge rst)`
95			`if(rst) wr_adr <= #1 4'h1;`
96	4	rudi	`else`
97	18	rudi	`if(clr) wr_adr <= #1 4'h1;`
98			`else`
99	4	rudi	`if(we) wr_adr <= #1 {wr_adr[2:0], wr_adr[3]};`
100
101			`always @(posedge clk)`
102			`if(we & wr_adr[0]) r0 <= #1 din;`
103
104			`always @(posedge clk)`
105			`if(we & wr_adr[1]) r1 <= #1 din;`
106
107			`always @(posedge clk)`
108			`if(we & wr_adr[2]) r2 <= #1 din;`
109
110			`always @(posedge clk)`
111			`if(we & wr_adr[3]) r3 <= #1 din;`
112
113			`always @(rd_adr or r0 or r1 or r2 or r3 or re or we or din)`
114			`case(rd_adr) // synopsys full_case parallel_case`
115			`4'h1: dout = r0;`
116			`4'h2: dout = r1;`
117			`4'h4: dout = r2;`
118			`4'h8: dout = r3;`
119			`endcase`
120
121			`endmodule`

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[/] [mem_ctrl/] [trunk/] [rtl/] [verilog/] [mc_rd_fifo.v] - Blame information for rev 18