| 1 |
4 |
rudi |
/////////////////////////////////////////////////////////////////////
|
| 2 |
|
|
//// ////
|
| 3 |
|
|
//// WISHBONE Memory Controller ////
|
| 4 |
|
|
//// Read FIFO ////
|
| 5 |
|
|
//// ////
|
| 6 |
|
|
//// ////
|
| 7 |
|
|
//// Author: Rudolf Usselmann ////
|
| 8 |
|
|
//// rudi@asics.ws ////
|
| 9 |
|
|
//// ////
|
| 10 |
|
|
//// ////
|
| 11 |
|
|
//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
|
| 12 |
|
|
//// ////
|
| 13 |
|
|
/////////////////////////////////////////////////////////////////////
|
| 14 |
|
|
//// ////
|
| 15 |
|
|
//// Copyright (C) 2000 Rudolf Usselmann ////
|
| 16 |
|
|
//// rudi@asics.ws ////
|
| 17 |
|
|
//// ////
|
| 18 |
|
|
//// This source file may be used and distributed without ////
|
| 19 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 20 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 21 |
|
|
//// the original copyright notice and the associated disclaimer.////
|
| 22 |
|
|
//// ////
|
| 23 |
|
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
| 24 |
|
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
| 25 |
|
|
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
| 26 |
|
|
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
| 27 |
|
|
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
| 28 |
|
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
| 29 |
|
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
| 30 |
|
|
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
| 31 |
|
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
| 32 |
|
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
| 33 |
|
|
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
| 34 |
|
|
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
| 35 |
|
|
//// POSSIBILITY OF SUCH DAMAGE. ////
|
| 36 |
|
|
//// ////
|
| 37 |
|
|
/////////////////////////////////////////////////////////////////////
|
| 38 |
|
|
|
| 39 |
|
|
// CVS Log
|
| 40 |
|
|
//
|
| 41 |
|
|
// $Id: mc_rd_fifo.v,v 1.1 2001-07-29 07:34:41 rudi Exp $
|
| 42 |
|
|
//
|
| 43 |
|
|
// $Date: 2001-07-29 07:34:41 $
|
| 44 |
|
|
// $Revision: 1.1 $
|
| 45 |
|
|
// $Author: rudi $
|
| 46 |
|
|
// $Locker: $
|
| 47 |
|
|
// $State: Exp $
|
| 48 |
|
|
//
|
| 49 |
|
|
// Change History:
|
| 50 |
|
|
// $Log: not supported by cvs2svn $
|
| 51 |
|
|
// Revision 1.1.1.1 2001/05/13 09:39:44 rudi
|
| 52 |
|
|
// Created Directory Structure
|
| 53 |
|
|
//
|
| 54 |
|
|
//
|
| 55 |
|
|
//
|
| 56 |
|
|
//
|
| 57 |
|
|
|
| 58 |
|
|
`include "mc_defines.v"
|
| 59 |
|
|
|
| 60 |
|
|
module mc_rd_fifo(clk, rst, din, we, dout, re);
|
| 61 |
|
|
|
| 62 |
|
|
input clk, rst;
|
| 63 |
|
|
input [35:0] din;
|
| 64 |
|
|
input we;
|
| 65 |
|
|
output [35:0] dout;
|
| 66 |
|
|
input re;
|
| 67 |
|
|
|
| 68 |
|
|
reg [3:0] rd_adr, wr_adr;
|
| 69 |
|
|
reg [35:0] r0, r1, r2, r3;
|
| 70 |
|
|
reg [35:0] dout;
|
| 71 |
|
|
|
| 72 |
|
|
always @(posedge clk)
|
| 73 |
|
|
if(!rst) rd_adr <= #1 4'h1;
|
| 74 |
|
|
else
|
| 75 |
|
|
if(re) rd_adr <= #1 {rd_adr[2:0], rd_adr[3]};
|
| 76 |
|
|
|
| 77 |
|
|
always @(posedge clk)
|
| 78 |
|
|
if(!rst) wr_adr <= #1 4'h1;
|
| 79 |
|
|
else
|
| 80 |
|
|
if(we) wr_adr <= #1 {wr_adr[2:0], wr_adr[3]};
|
| 81 |
|
|
|
| 82 |
|
|
always @(posedge clk)
|
| 83 |
|
|
if(we & wr_adr[0]) r0 <= #1 din;
|
| 84 |
|
|
|
| 85 |
|
|
always @(posedge clk)
|
| 86 |
|
|
if(we & wr_adr[1]) r1 <= #1 din;
|
| 87 |
|
|
|
| 88 |
|
|
always @(posedge clk)
|
| 89 |
|
|
if(we & wr_adr[2]) r2 <= #1 din;
|
| 90 |
|
|
|
| 91 |
|
|
always @(posedge clk)
|
| 92 |
|
|
if(we & wr_adr[3]) r3 <= #1 din;
|
| 93 |
|
|
|
| 94 |
|
|
always @(rd_adr or r0 or r1 or r2 or r3 or re or we or din)
|
| 95 |
|
|
if(re & we) dout = din;
|
| 96 |
|
|
else
|
| 97 |
|
|
case(rd_adr) // synopsys full_case parallel_case
|
| 98 |
|
|
4'h1: dout = r0;
|
| 99 |
|
|
4'h2: dout = r1;
|
| 100 |
|
|
4'h4: dout = r2;
|
| 101 |
|
|
4'h8: dout = r3;
|
| 102 |
|
|
endcase
|
| 103 |
|
|
|
| 104 |
|
|
endmodule
|
