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[/] [mem_ctrl/] [trunk/] [rtl/] [verilog/] [mc_refresh.v] - Blame information for rev 18

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Memory Controller                                 ////
////  Refresh Module                                             ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: mc_refresh.v,v 1.3 2001-12-11 02:47:19 rudi Exp $
//
//  $Date: 2001-12-11 02:47:19 $
//  $Revision: 1.3 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.2  2001/09/24 00:38:21  rudi
//
//               Changed Reset to be active high and async.
//
//               Revision 1.1  2001/07/29 07:34:41  rudi
//
//
//               1) Changed Directory Structure
//               2) Fixed several minor bugs
//
//               Revision 1.3  2001/06/12 15:19:49  rudi
//
//
//               Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
//
//               Revision 1.2  2001/06/03 11:37:17  rudi
//
//
//               1) Fixed Chip Select Mask Register
//                      - Power On Value is now all ones
//                      - Comparison Logic is now correct
//
//               2) All resets are now asynchronous
//
//               3) Converted Power On Delay to an configurable item
//
//               4) Added reset to Chip Select Output Registers
//
//               5) Forcing all outputs to Hi-Z state during reset
//
//               Revision 1.1.1.1  2001/05/13 09:39:47  rudi
//               Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_refresh(clk, rst,
                cs_need_rfr, ref_int, rfr_req, rfr_ack,
                rfr_ps_val
                );
 
input           clk, rst;
input   [7:0]    cs_need_rfr;
input   [2:0]    ref_int;
output          rfr_req;
input           rfr_ack;
input   [7:0]    rfr_ps_val;
 
////////////////////////////////////////////////////////////////////
//
// Local Registers & Wires
//
 
reg             rfr_en;
reg     [7:0]    ps_cnt;
wire            ps_cnt_clr;
reg             rfr_ce;
reg     [7:0]    rfr_cnt;
reg             rfr_clr;
reg             rfr_req;
reg             rfr_early;
 
/*
Refresh generation
 
The prescaler generates a 0.48828 uS clock enable
 
The refresh counter generates the following refresh rates:
(Actual values are about 0.63% below the desired values).
This is for a 200 Mhz WISHBONE Bus.
0.970 uS,
1.940
3.880
7.760
15.520
32.040
62.080
124.160 uS
 
(desired values)
0.976 uS
1.953
3.906
7.812
15.625
31.250
62.500
125.000 uS
*/
 
////////////////////////////////////////////////////////////////////
//
// Prescaler
//
 
always @(posedge clk or posedge rst)
        if(rst)         rfr_en <= #1 1'b0;
        else            rfr_en <= #1 |cs_need_rfr;
 
always @(posedge clk or posedge rst)
        if(rst)                         ps_cnt <= #1 8'h0;
        else
        if(ps_cnt_clr)                  ps_cnt <= #1 8'h0;
        else
        if(rfr_en)                      ps_cnt <= #1 ps_cnt + 8'h1;
 
assign ps_cnt_clr = (ps_cnt == rfr_ps_val) & (rfr_ps_val != 8'h0);
 
always @(posedge clk or posedge rst)
        if(rst)         rfr_early <= #1 1'b0;
        else            rfr_early <= #1 (ps_cnt == rfr_ps_val);
 
////////////////////////////////////////////////////////////////////
//
// Refresh Counter
//
 
always @(posedge clk or posedge rst)
        if(rst)         rfr_ce <= #1 1'b0;
        else            rfr_ce <= #1 ps_cnt_clr;
 
always @(posedge clk or posedge rst)
        if(rst)                 rfr_cnt <= #1 8'h0;
        else
        if(rfr_ack)             rfr_cnt <= #1 8'h0;
        else
        if(rfr_ce)              rfr_cnt <= #1 rfr_cnt + 8'h1;
 
always @(posedge clk)
        case(ref_int)           // synopsys full_case parallel_case
           3'h0: rfr_clr <= #1  rfr_cnt[0]   & rfr_early;
           3'h1: rfr_clr <= #1 &rfr_cnt[1:0] & rfr_early;
           3'h2: rfr_clr <= #1 &rfr_cnt[2:0] & rfr_early;
           3'h3: rfr_clr <= #1 &rfr_cnt[3:0] & rfr_early;
           3'h4: rfr_clr <= #1 &rfr_cnt[4:0] & rfr_early;
           3'h5: rfr_clr <= #1 &rfr_cnt[5:0] & rfr_early;
           3'h6: rfr_clr <= #1 &rfr_cnt[6:0] & rfr_early;
           3'h7: rfr_clr <= #1 &rfr_cnt[7:0] & rfr_early;
        endcase
 
always @(posedge clk or posedge rst)
        if(rst)                 rfr_req <= #1 1'b0;
        else
        if(rfr_ack)             rfr_req <= #1 1'b0;
        else
        if(rfr_clr)             rfr_req <= #1 1'b1;
 
endmodule

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Memory Controller ////`
4			`//// Refresh Module ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2000 Rudolf Usselmann ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41	18	rudi	`// $Id: mc_refresh.v,v 1.3 2001-12-11 02:47:19 rudi Exp $`
42	4	rudi	`//`
43	18	rudi	`// $Date: 2001-12-11 02:47:19 $`
44			`// $Revision: 1.3 $`
45	4	rudi	`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51	18	rudi	`// Revision 1.2 2001/09/24 00:38:21 rudi`
52			`//`
53			`// Changed Reset to be active high and async.`
54			`//`
55	12	rudi	`// Revision 1.1 2001/07/29 07:34:41 rudi`
56			`//`
57			`//`
58			`// 1) Changed Directory Structure`
59			`// 2) Fixed several minor bugs`
60			`//`
61	4	rudi	`// Revision 1.3 2001/06/12 15:19:49 rudi`
62			`//`
63			`//`
64			`// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.`
65			`//`
66			`// Revision 1.2 2001/06/03 11:37:17 rudi`
67			`//`
68			`//`
69			`// 1) Fixed Chip Select Mask Register`
70			`// - Power On Value is now all ones`
71			`// - Comparison Logic is now correct`
72			`//`
73			`// 2) All resets are now asynchronous`
74			`//`
75			`// 3) Converted Power On Delay to an configurable item`
76			`//`
77			`// 4) Added reset to Chip Select Output Registers`
78			`//`
79			`// 5) Forcing all outputs to Hi-Z state during reset`
80			`//`
81			`// Revision 1.1.1.1 2001/05/13 09:39:47 rudi`
82			`// Created Directory Structure`
83			`//`
84			`//`
85			`//`
86			`//`
87
88			`include "mc_defines.v"
89
90			`module mc_refresh(clk, rst,`
91			`cs_need_rfr, ref_int, rfr_req, rfr_ack,`
92			`rfr_ps_val`
93			`);`
94
95			`input clk, rst;`
96			`input [7:0] cs_need_rfr;`
97			`input [2:0] ref_int;`
98			`output rfr_req;`
99			`input rfr_ack;`
100			`input [7:0] rfr_ps_val;`
101
102			`////////////////////////////////////////////////////////////////////`
103			`//`
104			`// Local Registers & Wires`
105			`//`
106
107			`reg rfr_en;`
108			`reg [7:0] ps_cnt;`
109			`wire ps_cnt_clr;`
110			`reg rfr_ce;`
111			`reg [7:0] rfr_cnt;`
112			`reg rfr_clr;`
113			`reg rfr_req;`
114			`reg rfr_early;`
115
116			`/*`
117			`Refresh generation`
118
119			`The prescaler generates a 0.48828 uS clock enable`
120
121			`The refresh counter generates the following refresh rates:`
122			`(Actual values are about 0.63% below the desired values).`
123			`This is for a 200 Mhz WISHBONE Bus.`
124			`0.970 uS,`
125			`1.940`
126			`3.880`
127			`7.760`
128			`15.520`
129			`32.040`
130			`62.080`
131			`124.160 uS`
132
133			`(desired values)`
134			`0.976 uS`
135			`1.953`
136			`3.906`
137			`7.812`
138			`15.625`
139			`31.250`
140			`62.500`
141			`125.000 uS`
142			`*/`
143
144			`////////////////////////////////////////////////////////////////////`
145			`//`
146			`// Prescaler`
147			`//`
148
149	18	rudi	`always @(posedge clk or posedge rst)`
150			`if(rst) rfr_en <= #1 1'b0;`
151			`else rfr_en <= #1 \|cs_need_rfr;`
152	4	rudi
153	12	rudi	`always @(posedge clk or posedge rst)`
154			`if(rst) ps_cnt <= #1 8'h0;`
155	4	rudi	`else`
156			`if(ps_cnt_clr) ps_cnt <= #1 8'h0;`
157			`else`
158			`if(rfr_en) ps_cnt <= #1 ps_cnt + 8'h1;`
159
160			`assign ps_cnt_clr = (ps_cnt == rfr_ps_val) & (rfr_ps_val != 8'h0);`
161
162	18	rudi	`always @(posedge clk or posedge rst)`
163			`if(rst) rfr_early <= #1 1'b0;`
164			`else rfr_early <= #1 (ps_cnt == rfr_ps_val);`
165	4	rudi
166			`////////////////////////////////////////////////////////////////////`
167			`//`
168			`// Refresh Counter`
169			`//`
170
171	18	rudi	`always @(posedge clk or posedge rst)`
172			`if(rst) rfr_ce <= #1 1'b0;`
173			`else rfr_ce <= #1 ps_cnt_clr;`
174	4	rudi
175	12	rudi	`always @(posedge clk or posedge rst)`
176			`if(rst) rfr_cnt <= #1 8'h0;`
177	4	rudi	`else`
178			`if(rfr_ack) rfr_cnt <= #1 8'h0;`
179			`else`
180			`if(rfr_ce) rfr_cnt <= #1 rfr_cnt + 8'h1;`
181
182			`always @(posedge clk)`
183			`case(ref_int) // synopsys full_case parallel_case`
184			`3'h0: rfr_clr <= #1 rfr_cnt[0] & rfr_early;`
185			`3'h1: rfr_clr <= #1 &rfr_cnt[1:0] & rfr_early;`
186			`3'h2: rfr_clr <= #1 &rfr_cnt[2:0] & rfr_early;`
187			`3'h3: rfr_clr <= #1 &rfr_cnt[3:0] & rfr_early;`
188			`3'h4: rfr_clr <= #1 &rfr_cnt[4:0] & rfr_early;`
189			`3'h5: rfr_clr <= #1 &rfr_cnt[5:0] & rfr_early;`
190			`3'h6: rfr_clr <= #1 &rfr_cnt[6:0] & rfr_early;`
191			`3'h7: rfr_clr <= #1 &rfr_cnt[7:0] & rfr_early;`
192			`endcase`
193
194	12	rudi	`always @(posedge clk or posedge rst)`
195			`if(rst) rfr_req <= #1 1'b0;`
196	4	rudi	`else`
197			`if(rfr_ack) rfr_req <= #1 1'b0;`
198			`else`
199			`if(rfr_clr) rfr_req <= #1 1'b1;`
200
201			`endmodule`

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[/] [mem_ctrl/] [trunk/] [rtl/] [verilog/] [mc_refresh.v] - Blame information for rev 18