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/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE Memory Controller Top Level ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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rudi |
// $Id: mc_top.v,v 1.2 2001-08-10 08:16:21 rudi Exp $
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//
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// $Date: 2001-08-10 08:16:21 $
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// $Revision: 1.2 $
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// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/07/29 07:34:41 rudi
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//
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//
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// 1) Changed Directory Structure
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// 2) Fixed several minor bugs
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//
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// Revision 1.3 2001/06/12 15:19:49 rudi
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//
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//
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// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
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//
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// Revision 1.2 2001/06/03 11:37:17 rudi
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//
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//
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// 1) Fixed Chip Select Mask Register
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// - Power On Value is now all ones
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// - Comparison Logic is now correct
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//
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// 2) All resets are now asynchronous
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//
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// 3) Converted Power On Delay to an configurable item
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//
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// 4) Added reset to Chip Select Output Registers
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//
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// 5) Forcing all outputs to Hi-Z state during reset
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//
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// Revision 1.1.1.1 2001/05/13 09:39:39 rudi
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// Created Directory Structure
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//
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//
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//
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//
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`include "mc_defines.v"
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module mc_top(clk_i, rst_i,
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wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
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wb_stb_i, wb_ack_o, wb_err_o,
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susp_req_i, resume_req_i, suspended_o, poc_o,
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mc_clk_i, mc_br_pad_i, mc_bg_pad_o, mc_ack_pad_i,
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mc_addr_pad_o, mc_data_pad_i, mc_data_pad_o, mc_dp_pad_i,
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mc_dp_pad_o, mc_doe_pad_doe_o, mc_dqm_pad_o, mc_oe_pad_o_,
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mc_we_pad_o_, mc_cas_pad_o_, mc_ras_pad_o_, mc_cke_pad_o_,
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mc_cs_pad_o_, mc_sts_pad_i, mc_rp_pad_o_, mc_vpen_pad_o,
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mc_adsc_pad_o_, mc_adv_pad_o_, mc_zz_pad_o, mc_coe_pad_coe_o
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);
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input clk_i, rst_i;
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// --------------------------------------
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// WISHBONE SLAVE INTERFACE
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input [31:0] wb_data_i;
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output [31:0] wb_data_o;
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input [31:0] wb_addr_i;
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input [3:0] wb_sel_i;
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input wb_we_i;
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input wb_cyc_i;
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input wb_stb_i;
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output wb_ack_o;
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output wb_err_o;
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// --------------------------------------
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// Suspend Resume Interface
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input susp_req_i;
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input resume_req_i;
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output suspended_o;
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// POC
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output [31:0] poc_o;
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// --------------------------------------
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// Memory Bus Signals
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input mc_clk_i;
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input mc_br_pad_i;
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output mc_bg_pad_o;
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input mc_ack_pad_i;
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output [23:0] mc_addr_pad_o;
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input [31:0] mc_data_pad_i;
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output [31:0] mc_data_pad_o;
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input [3:0] mc_dp_pad_i;
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output [3:0] mc_dp_pad_o;
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output mc_doe_pad_doe_o;
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output [3:0] mc_dqm_pad_o;
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output mc_oe_pad_o_;
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output mc_we_pad_o_;
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output mc_cas_pad_o_;
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output mc_ras_pad_o_;
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output mc_cke_pad_o_;
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output [7:0] mc_cs_pad_o_;
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input mc_sts_pad_i;
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output mc_rp_pad_o_;
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output mc_vpen_pad_o;
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output mc_adsc_pad_o_;
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output mc_adv_pad_o_;
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output mc_zz_pad_o;
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output mc_coe_pad_coe_o;
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rudi |
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////////////////////////////////////////////////////////////////////
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//
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// Local Wires
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//
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// WISHBONE Interface Interconnects
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wire wb_read_go;
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wire wb_write_go;
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wire wb_first;
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wire wb_wait;
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wire mem_ack;
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wire mem_wb_ack_o, rf_wb_ack_o;
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// --------------------------------------
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// Suspend Resume Interface
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//wire susp_req;
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//wire resume_req;
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wire susp_sel;
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reg mc_zz_pad_o;
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// Register File Interconnects
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wire [31:0] rf_dout;
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wire [31:0] csc;
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wire [31:0] tms;
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wire [31:0] sp_csc;
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wire [31:0] sp_tms;
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wire [7:0] cs;
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wire fs;
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wire cs_le;
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wire [7:0] cs_need_rfr;
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wire [2:0] ref_int;
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wire [31:0] mem_dout;
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wire rf_wb_err_o;
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wire wp_err;
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// Address Select Signals
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wire [12:0] row_adr;
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wire [1:0] bank_adr;
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wire cmd_a10;
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wire row_sel;
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wire next_adr;
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wire [10:0] page_size;
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wire lmr_sel;
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wire wr_hold;
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// OBCT Signals
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wire bank_set;
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wire bank_clr;
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wire bank_clr_all;
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wire bank_open;
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wire row_same;
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wire [7:0] obct_cs;
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wire any_bank_open;
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// Data path Controller Signals
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wire dv;
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wire pack_le0, pack_le1, pack_le2; // Pack Latch Enable
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wire par_err;
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wire [31:0] mc_data_od;
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wire [3:0] mc_dp_od;
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wire [23:0] mc_addr_d;
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// Refresh Counter Signals
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wire rfr_req;
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wire rfr_ack;
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wire [7:0] rfr_ps_val;
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// Memory Timing Block Signals
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wire data_oe;
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wire oe_;
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wire we_;
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wire cas_;
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wire ras_;
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wire cke_;
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wire lmr_req;
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wire lmr_ack;
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wire init_req;
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wire init_ack;
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wire [7:0] spec_req_cs;
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wire cs_en;
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wire wb_cycle, wr_cycle;
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wire [31:0] tms_s;
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wire [31:0] csc_s;
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wire mc_br_r;
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wire mc_bg_d;
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wire mc_adsc_d;
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wire mc_adv_d;
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wire mc_ack_r;
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wire err;
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/*
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// synopsys translate_off
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initial // FOR RICHARD TEST BENCH ONLY ... FIX_ME
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begin
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$shm_open("waves");
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$shm_probe("AS",mc_top,"AS");
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$display("INFO: Signal dump enabled ...\n\n");
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repeat(4000) @(posedge clk_i);
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$finish;
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end
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// synopsys translate_on
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*/
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////////////////////////////////////////////////////////////////////
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//
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// Misc Logic
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//
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assign mc_rp_pad_o_ = !suspended_o & !fs;
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always @(posedge mc_clk_i)
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mc_zz_pad_o <= #1 suspended_o;
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assign wb_err_o = wb_cyc_i & wb_stb_i &
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(`MC_MEM_SEL ? ((par_err & !wb_we_i) | err | wp_err) : rf_wb_err_o);
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assign wb_data_o = `MC_MEM_SEL ? mem_dout : rf_dout;
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assign wb_ack_o = `MC_MEM_SEL ? mem_wb_ack_o : rf_wb_ack_o;
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4 |
rudi |
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assign obct_cs = (rfr_ack | susp_sel) ? cs_need_rfr :
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(lmr_ack | init_ack) ? spec_req_cs : cs;
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assign lmr_sel = lmr_ack | init_ack;
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assign tms_s = lmr_sel ? sp_tms : tms;
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assign csc_s = lmr_sel ? sp_csc : csc;
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////////////////////////////////////////////////////////////////////
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//
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// Modules
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//
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mc_rf u0(
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8 |
rudi |
.clk( clk_i ),
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.rst( rst_i ),
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4 |
rudi |
.wb_data_i( wb_data_i ),
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.rf_dout( rf_dout ),
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.wb_addr_i( wb_addr_i ),
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.wb_we_i( wb_we_i ),
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.wb_cyc_i( wb_cyc_i ),
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.wb_stb_i( wb_stb_i ),
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.wb_ack_o( rf_wb_ack_o ),
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.wb_err_o( rf_wb_err_o ),
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.wp_err( wp_err ),
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.csc( csc ),
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.tms( tms ),
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8 |
rudi |
.poc( poc_o ),
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4 |
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.sp_csc( sp_csc ),
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.sp_tms( sp_tms ),
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.cs( cs ),
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8 |
rudi |
.mc_data_i( mc_data_pad_i ),
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.mc_sts( mc_sts_pad_i ),
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.mc_vpen( mc_vpen_pad_o ),
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4 |
rudi |
.fs( fs ),
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.cs_le( cs_le ),
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.cs_need_rfr( cs_need_rfr ),
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.ref_int( ref_int ),
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.rfr_ps_val( rfr_ps_val ),
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.spec_req_cs( spec_req_cs ),
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.init_req( init_req ),
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.init_ack( init_ack ),
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.lmr_req( lmr_req ),
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.lmr_ack( lmr_ack )
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);
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| 312 |
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mc_adr_sel u1(
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| 314 |
8 |
rudi |
.clk( clk_i ),
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| 315 |
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.csc( csc_s ),
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| 316 |
4 |
rudi |
.tms( tms_s ),
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.wb_stb_i( wb_stb_i ),
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.wb_ack_o( mem_wb_ack_o ),
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.wb_addr_i( wb_addr_i ),
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.wb_write_go( wb_write_go ),
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.wr_hold( wr_hold ),
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.cas_( cas_ ),
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.mc_addr( mc_addr_d ),
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.row_adr( row_adr ),
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.bank_adr( bank_adr ),
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.rfr_ack( rfr_ack ),
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.cs_le( cs_le ),
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|
|
.cmd_a10( cmd_a10 ),
|
| 329 |
|
|
.row_sel( row_sel ),
|
| 330 |
|
|
.lmr_sel( lmr_sel ),
|
| 331 |
|
|
.next_adr( next_adr ),
|
| 332 |
|
|
.wr_cycle( wr_cycle ),
|
| 333 |
|
|
.page_size( page_size )
|
| 334 |
|
|
);
|
| 335 |
|
|
|
| 336 |
|
|
mc_obct_top u2(
|
| 337 |
8 |
rudi |
.clk( clk_i ),
|
| 338 |
|
|
.rst( rst_i ),
|
| 339 |
4 |
rudi |
.cs( obct_cs ),
|
| 340 |
|
|
.row_adr( row_adr ),
|
| 341 |
|
|
.bank_adr( bank_adr ),
|
| 342 |
|
|
.bank_set( bank_set ),
|
| 343 |
|
|
.bank_clr( bank_clr ),
|
| 344 |
|
|
.bank_clr_all( bank_clr_all ),
|
| 345 |
|
|
.bank_open( bank_open ),
|
| 346 |
|
|
.any_bank_open( any_bank_open ),
|
| 347 |
|
|
.row_same( row_same ),
|
| 348 |
|
|
.rfr_ack( rfr_ack )
|
| 349 |
|
|
);
|
| 350 |
|
|
|
| 351 |
|
|
mc_dp u3(
|
| 352 |
8 |
rudi |
.clk( clk_i ),
|
| 353 |
|
|
.rst( rst_i ),
|
| 354 |
4 |
rudi |
.csc( csc ),
|
| 355 |
|
|
.wb_cyc_i( wb_cyc_i ),
|
| 356 |
|
|
.mem_wb_ack_o( mem_wb_ack_o ),
|
| 357 |
|
|
.wb_data_i( wb_data_i ),
|
| 358 |
|
|
.wb_data_o( mem_dout ),
|
| 359 |
|
|
.wb_read_go( wb_read_go ),
|
| 360 |
8 |
rudi |
.mc_data_i( mc_data_pad_i ),
|
| 361 |
|
|
.mc_dp_i( mc_dp_pad_i ),
|
| 362 |
4 |
rudi |
.mc_data_o( mc_data_od ),
|
| 363 |
|
|
.mc_dp_o( mc_dp_od ),
|
| 364 |
|
|
.dv( dv ),
|
| 365 |
|
|
.pack_le0( pack_le0 ),
|
| 366 |
|
|
.pack_le1( pack_le1 ),
|
| 367 |
|
|
.pack_le2( pack_le2 ),
|
| 368 |
|
|
.byte_en( wb_sel_i ),
|
| 369 |
|
|
.par_err( par_err )
|
| 370 |
|
|
);
|
| 371 |
|
|
|
| 372 |
|
|
mc_refresh u4(
|
| 373 |
8 |
rudi |
.clk( clk_i ),
|
| 374 |
|
|
.rst( rst_i ),
|
| 375 |
4 |
rudi |
.cs_need_rfr( cs_need_rfr ),
|
| 376 |
|
|
.ref_int( ref_int ),
|
| 377 |
|
|
.rfr_req( rfr_req ),
|
| 378 |
|
|
.rfr_ack( rfr_ack ),
|
| 379 |
|
|
.rfr_ps_val( rfr_ps_val )
|
| 380 |
|
|
);
|
| 381 |
|
|
|
| 382 |
|
|
mc_timing u5(
|
| 383 |
8 |
rudi |
.clk( clk_i ),
|
| 384 |
|
|
.rst( rst_i ),
|
| 385 |
4 |
rudi |
.wb_cyc_i( wb_cyc_i ),
|
| 386 |
|
|
.wb_we_i( wb_we_i ),
|
| 387 |
|
|
.wb_read_go( wb_read_go ),
|
| 388 |
|
|
.wb_write_go( wb_write_go ),
|
| 389 |
|
|
.wb_first( wb_first ),
|
| 390 |
|
|
.wb_wait( wb_wait ),
|
| 391 |
|
|
.mem_ack( mem_ack ),
|
| 392 |
|
|
.err( err ),
|
| 393 |
8 |
rudi |
.susp_req( susp_req_i ),
|
| 394 |
|
|
.resume_req( resume_req_i ),
|
| 395 |
|
|
.suspended( suspended_o ),
|
| 396 |
4 |
rudi |
.susp_sel( susp_sel ),
|
| 397 |
|
|
.mc_br( mc_br_r ),
|
| 398 |
|
|
.mc_bg( mc_bg_d ),
|
| 399 |
|
|
.mc_ack( mc_ack_r ),
|
| 400 |
|
|
.data_oe( data_oe ),
|
| 401 |
|
|
.oe_( oe_ ),
|
| 402 |
|
|
.we_( we_ ),
|
| 403 |
|
|
.cas_( cas_ ),
|
| 404 |
|
|
.ras_( ras_ ),
|
| 405 |
|
|
.cke_( cke_ ),
|
| 406 |
|
|
.cs_en( cs_en ),
|
| 407 |
|
|
.mc_adsc( mc_adsc_d ),
|
| 408 |
|
|
.mc_adv( mc_adv_d ),
|
| 409 |
8 |
rudi |
.mc_c_oe( mc_coe_pad_coe_o),
|
| 410 |
4 |
rudi |
.wb_cycle( wb_cycle ),
|
| 411 |
|
|
.wr_cycle( wr_cycle ),
|
| 412 |
|
|
.csc( csc_s ),
|
| 413 |
|
|
.tms( tms_s ),
|
| 414 |
|
|
.cs( cs ),
|
| 415 |
|
|
.lmr_req( lmr_req ),
|
| 416 |
|
|
.lmr_ack( lmr_ack ),
|
| 417 |
|
|
.cs_le( cs_le ),
|
| 418 |
|
|
.cmd_a10( cmd_a10 ),
|
| 419 |
|
|
.row_sel( row_sel ),
|
| 420 |
|
|
.next_adr( next_adr ),
|
| 421 |
|
|
.page_size( page_size ),
|
| 422 |
|
|
.bank_set( bank_set ),
|
| 423 |
|
|
.bank_clr( bank_clr ),
|
| 424 |
|
|
.bank_clr_all( bank_clr_all ),
|
| 425 |
|
|
.bank_open( bank_open ),
|
| 426 |
|
|
.any_bank_open( any_bank_open ),
|
| 427 |
|
|
.row_same( row_same ),
|
| 428 |
|
|
.dv( dv ),
|
| 429 |
|
|
.pack_le0( pack_le0 ),
|
| 430 |
|
|
.pack_le1( pack_le1 ),
|
| 431 |
|
|
.pack_le2( pack_le2 ),
|
| 432 |
|
|
.par_err( par_err ),
|
| 433 |
|
|
.rfr_req( rfr_req ),
|
| 434 |
|
|
.rfr_ack( rfr_ack ),
|
| 435 |
|
|
.init_req( init_req ),
|
| 436 |
|
|
.init_ack( init_ack )
|
| 437 |
|
|
);
|
| 438 |
|
|
|
| 439 |
|
|
mc_wb_if u6(
|
| 440 |
8 |
rudi |
.clk( clk_i ),
|
| 441 |
|
|
.rst( rst_i ),
|
| 442 |
4 |
rudi |
.wb_addr_i( wb_addr_i ),
|
| 443 |
|
|
.wb_cyc_i( wb_cyc_i ),
|
| 444 |
|
|
.wb_stb_i( wb_stb_i ),
|
| 445 |
|
|
.wb_we_i( wb_we_i ),
|
| 446 |
|
|
.wb_ack_o( mem_wb_ack_o ),
|
| 447 |
|
|
.wb_err( wb_err_o ),
|
| 448 |
|
|
.wb_read_go( wb_read_go ),
|
| 449 |
|
|
.wb_write_go( wb_write_go ),
|
| 450 |
|
|
.wb_first( wb_first ),
|
| 451 |
|
|
.wb_wait( wb_wait ),
|
| 452 |
|
|
.mem_ack( mem_ack ),
|
| 453 |
|
|
.wr_hold( wr_hold )
|
| 454 |
|
|
);
|
| 455 |
|
|
|
| 456 |
|
|
mc_mem_if u7(
|
| 457 |
8 |
rudi |
.clk( clk_i ),
|
| 458 |
|
|
.rst( rst_i ),
|
| 459 |
|
|
.mc_clk( mc_clk_i ),
|
| 460 |
|
|
.mc_br( mc_br_pad_i ),
|
| 461 |
|
|
.mc_bg( mc_bg_pad_o ),
|
| 462 |
|
|
.mc_addr( mc_addr_pad_o ),
|
| 463 |
|
|
.mc_data_o( mc_data_pad_o ),
|
| 464 |
|
|
.mc_dp_o( mc_dp_pad_o ),
|
| 465 |
|
|
.mc_data_oe( mc_doe_pad_doe_o),
|
| 466 |
|
|
.mc_dqm( mc_dqm_pad_o ),
|
| 467 |
|
|
.mc_oe_( mc_oe_pad_o_ ),
|
| 468 |
|
|
.mc_we_( mc_we_pad_o_ ),
|
| 469 |
|
|
.mc_cas_( mc_cas_pad_o_ ),
|
| 470 |
|
|
.mc_ras_( mc_ras_pad_o_ ),
|
| 471 |
|
|
.mc_cke_( mc_cke_pad_o_ ),
|
| 472 |
|
|
.mc_cs_( mc_cs_pad_o_ ),
|
| 473 |
|
|
.mc_adsc_( mc_adsc_pad_o_ ),
|
| 474 |
|
|
.mc_adv_( mc_adv_pad_o_ ),
|
| 475 |
4 |
rudi |
.mc_br_r( mc_br_r ),
|
| 476 |
|
|
.mc_bg_d( mc_bg_d ),
|
| 477 |
|
|
.mc_data_od( mc_data_od ),
|
| 478 |
|
|
.mc_dp_od( mc_dp_od ),
|
| 479 |
|
|
.mc_addr_d( mc_addr_d ),
|
| 480 |
8 |
rudi |
.mc_ack( mc_ack_pad_i ),
|
| 481 |
4 |
rudi |
.we_( we_ ),
|
| 482 |
|
|
.ras_( ras_ ),
|
| 483 |
|
|
.cas_( cas_ ),
|
| 484 |
|
|
.cke_( cke_ ),
|
| 485 |
|
|
.mc_adsc_d( mc_adsc_d ),
|
| 486 |
|
|
.mc_adv_d( mc_adv_d ),
|
| 487 |
|
|
.cs_en( cs_en ),
|
| 488 |
|
|
.rfr_ack( rfr_ack ),
|
| 489 |
|
|
.cs_need_rfr( cs_need_rfr ),
|
| 490 |
|
|
.lmr_sel( lmr_sel ),
|
| 491 |
|
|
.spec_req_cs( spec_req_cs ),
|
| 492 |
|
|
.cs( cs ),
|
| 493 |
|
|
.data_oe( data_oe ),
|
| 494 |
|
|
.susp_sel( susp_sel ),
|
| 495 |
8 |
rudi |
.mc_c_oe( mc_coe_pad_coe_o),
|
| 496 |
4 |
rudi |
.mc_ack_r( mc_ack_r ),
|
| 497 |
|
|
.oe_( oe_ ),
|
| 498 |
|
|
.wb_stb_i( wb_stb_i ),
|
| 499 |
|
|
.wb_sel_i( wb_sel_i ),
|
| 500 |
|
|
.wb_cycle( wb_cycle ),
|
| 501 |
|
|
.wr_cycle( wr_cycle )
|
| 502 |
|
|
);
|
| 503 |
|
|
|
| 504 |
|
|
endmodule
|
