URL https://opencores.org/ocsvn/mem_ctrl/mem_ctrl/trunk

Subversion Repositories mem_ctrl

[/] [mem_ctrl/] [trunk/] [rtl/] [verilog/] [mc_wb_if.v] - Blame information for rev 18

Go to most recent revision | Details | Compare with Previous | View Log


/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Memory Controller                                 ////
////  WISHBONE Interface                                         ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: mc_wb_if.v,v 1.5 2001-12-11 02:47:19 rudi Exp $
//
//  $Date: 2001-12-11 02:47:19 $
//  $Revision: 1.5 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.4  2001/11/29 02:16:28  rudi
//
//
//               - More Synthesis cleanup, mostly for speed
//               - Several bug fixes
//               - Changed code to avoid auto-precharge and
//                 burst-terminate combinations (apparently illegal ?)
//                 Now we will do a manual precharge ...
//
//               Revision 1.3  2001/09/24 00:38:21  rudi
//
//               Changed Reset to be active high and async.
//
//               Revision 1.2  2001/08/10 08:16:21  rudi
//
//               - Changed IO names to be more clear.
//               - Uniquifyed define names to be core specific.
//               - Removed "Refresh Early" configuration
//
//               Revision 1.1  2001/07/29 07:34:41  rudi
//
//
//               1) Changed Directory Structure
//               2) Fixed several minor bugs
//
//               Revision 1.3  2001/06/12 15:19:49  rudi
//
//
//              Minor changes after running lint, and a small bug
//              fix reading csr and ba_mask registers.
//
//               Revision 1.2  2001/06/03 11:37:17  rudi
//
//
//               1) Fixed Chip Select Mask Register
//                      - Power On Value is now all ones
//                      - Comparison Logic is now correct
//
//               2) All resets are now asynchronous
//
//               3) Converted Power On Delay to an configurable item
//
//               4) Added reset to Chip Select Output Registers
//
//               5) Forcing all outputs to Hi-Z state during reset
//
//               Revision 1.1.1.1  2001/05/13 09:39:47  rudi
//               Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_wb_if(clk, rst,
                wb_addr_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_err, wb_ack_o,
                wb_read_go, wb_write_go,
                wb_first, wb_wait, mem_ack, wr_hold,
                err, par_err, wp_err,
                wb_data_o, mem_dout, rf_dout);
 
input           clk, rst;
input   [31:0]   wb_addr_i;
input           wb_cyc_i;
input           wb_stb_i;
input           wb_we_i;
output          wb_err;
output          wb_ack_o;
output          wb_read_go;
output          wb_write_go;
output          wb_first;
output          wb_wait;
input           mem_ack;
output          wr_hold;
input           err, par_err, wp_err;
output  [31:0]   wb_data_o;
input   [31:0]   mem_dout, rf_dout;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
 
wire            mem_sel;
reg             read_go_r;
reg             read_go_r1;
reg             write_go_r;
reg             write_go_r1;
reg             wb_first_r;
wire            wb_first_set;
reg             wr_hold;
wire            rmw;
reg             rmw_r;
reg             rmw_en;
reg             wb_ack_o;
reg             wb_err;
reg     [31:0]   wb_data_o;
 
////////////////////////////////////////////////////////////////////
//
// Memory Go Logic
//
 
assign mem_sel = `MC_MEM_SEL;
 
always @(posedge clk or posedge rst)
        if(rst)                 rmw_en <= #1 1'b0;
        else
        if(wb_ack_o)            rmw_en <= #1 1'b1;
        else
        if(!wb_cyc_i)           rmw_en <= #1 1'b0;
 
always @(posedge clk or posedge rst)
        if(rst) rmw_r <= #1 1'b0;
        else    rmw_r <= #1 !wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en;
 
assign rmw = rmw_r | (!wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en);
 
always @(posedge clk or posedge rst)
        if(rst) read_go_r1 <= #1 1'b0;
        else    read_go_r1 <= #1 !rmw & wb_cyc_i &
                                ((wb_stb_i & mem_sel & !wb_we_i) | read_go_r);
 
always @(posedge clk or posedge rst)
        if(rst) read_go_r <= #1 1'b0;
        else    read_go_r <= #1 read_go_r1 & wb_cyc_i;
 
assign  wb_read_go = !rmw & read_go_r1 & wb_cyc_i;
 
always @(posedge clk or posedge rst)
        if(rst) write_go_r1 <= #1 1'b0;
        else    write_go_r1 <= #1 wb_cyc_i &
                                ((wb_stb_i & mem_sel & wb_we_i) | write_go_r);
 
always @(posedge clk or posedge rst)
        if(rst)         write_go_r <= #1 1'b0;
        else            write_go_r <= #1 write_go_r1 & wb_cyc_i &
                                        ((wb_we_i & wb_stb_i) | !wb_stb_i);
 
assign wb_write_go =    !rmw & write_go_r1 & wb_cyc_i &
                        ((wb_we_i & wb_stb_i) | !wb_stb_i);
 
assign wb_first_set = mem_sel & wb_cyc_i & wb_stb_i & !(read_go_r | write_go_r);
assign wb_first = wb_first_set | (wb_first_r & !wb_ack_o & !wb_err);
 
always @(posedge clk or posedge rst)
        if(rst)                 wb_first_r <= #1 1'b0;
        else
        if(wb_first_set)        wb_first_r <= #1 1'b1;
        else
        if(wb_ack_o | wb_err)   wb_first_r <= #1 1'b0;
 
always @(posedge clk or posedge rst)
        if(rst)                 wr_hold <= #1 1'b0;
        else
        if(wb_cyc_i & wb_stb_i) wr_hold <= #1 wb_we_i;
 
////////////////////////////////////////////////////////////////////
//
// WB Ack
//
 
always @(posedge clk or posedge rst)
        if(rst) wb_ack_o <= #1 1'b0;
        else    wb_ack_o <= #1 `MC_MEM_SEL ? mem_ack :
                                `MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o;
 
always @(posedge clk or posedge rst)
        if(rst) wb_err <= #1 1'b0;
        else    wb_err <= #1 wb_cyc_i & wb_stb_i & `MC_MEM_SEL &
                                (par_err | err | wp_err) & !wb_err;
 
////////////////////////////////////////////////////////////////////
//
// Memory Wait Logic
//
 
assign wb_wait = wb_cyc_i & !wb_stb_i & (wb_write_go | wb_read_go);
 
////////////////////////////////////////////////////////////////////
//
// WISHBONE Data Output
//
 
always @(posedge clk)
        wb_data_o <= #1 `MC_MEM_SEL ? mem_dout : rf_dout;
 
endmodule

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Memory Controller ////`
4			`//// WISHBONE Interface ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2000 Rudolf Usselmann ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41	18	rudi	`// $Id: mc_wb_if.v,v 1.5 2001-12-11 02:47:19 rudi Exp $`
42	4	rudi	`//`
43	18	rudi	`// $Date: 2001-12-11 02:47:19 $`
44			`// $Revision: 1.5 $`
45	4	rudi	`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51	18	rudi	`// Revision 1.4 2001/11/29 02:16:28 rudi`
52			`//`
53			`//`
54			`// - More Synthesis cleanup, mostly for speed`
55			`// - Several bug fixes`
56			`// - Changed code to avoid auto-precharge and`
57			`// burst-terminate combinations (apparently illegal ?)`
58			`// Now we will do a manual precharge ...`
59			`//`
60	16	rudi	`// Revision 1.3 2001/09/24 00:38:21 rudi`
61			`//`
62			`// Changed Reset to be active high and async.`
63			`//`
64	12	rudi	`// Revision 1.2 2001/08/10 08:16:21 rudi`
65			`//`
66			`// - Changed IO names to be more clear.`
67			`// - Uniquifyed define names to be core specific.`
68			`// - Removed "Refresh Early" configuration`
69			`//`
70	8	rudi	`// Revision 1.1 2001/07/29 07:34:41 rudi`
71			`//`
72			`//`
73			`// 1) Changed Directory Structure`
74			`// 2) Fixed several minor bugs`
75			`//`
76	4	rudi	`// Revision 1.3 2001/06/12 15:19:49 rudi`
77			`//`
78			`//`
79	16	rudi	`// Minor changes after running lint, and a small bug`
80			`// fix reading csr and ba_mask registers.`
81	4	rudi	`//`
82			`// Revision 1.2 2001/06/03 11:37:17 rudi`
83			`//`
84			`//`
85			`// 1) Fixed Chip Select Mask Register`
86			`// - Power On Value is now all ones`
87			`// - Comparison Logic is now correct`
88			`//`
89			`// 2) All resets are now asynchronous`
90			`//`
91			`// 3) Converted Power On Delay to an configurable item`
92			`//`
93			`// 4) Added reset to Chip Select Output Registers`
94			`//`
95			`// 5) Forcing all outputs to Hi-Z state during reset`
96			`//`
97			`// Revision 1.1.1.1 2001/05/13 09:39:47 rudi`
98			`// Created Directory Structure`
99			`//`
100			`//`
101			`//`
102			`//`
103
104			`include "mc_defines.v"
105
106			`module mc_wb_if(clk, rst,`
107			`wb_addr_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_err, wb_ack_o,`
108			`wb_read_go, wb_write_go,`
109	16	rudi	`wb_first, wb_wait, mem_ack, wr_hold,`
110			`err, par_err, wp_err,`
111			`wb_data_o, mem_dout, rf_dout);`
112	4	rudi
113			`input clk, rst;`
114			`input [31:0] wb_addr_i;`
115			`input wb_cyc_i;`
116			`input wb_stb_i;`
117			`input wb_we_i;`
118	16	rudi	`output wb_err;`
119	4	rudi	`output wb_ack_o;`
120			`output wb_read_go;`
121			`output wb_write_go;`
122			`output wb_first;`
123			`output wb_wait;`
124			`input mem_ack;`
125			`output wr_hold;`
126	16	rudi	`input err, par_err, wp_err;`
127			`output [31:0] wb_data_o;`
128			`input [31:0] mem_dout, rf_dout;`
129	4	rudi
130			`////////////////////////////////////////////////////////////////////`
131			`//`
132			`// Local Wires and Registers`
133			`//`
134
135			`wire mem_sel;`
136			`reg read_go_r;`
137			`reg read_go_r1;`
138			`reg write_go_r;`
139			`reg write_go_r1;`
140			`reg wb_first_r;`
141			`wire wb_first_set;`
142			`reg wr_hold;`
143			`wire rmw;`
144			`reg rmw_r;`
145			`reg rmw_en;`
146	16	rudi	`reg wb_ack_o;`
147			`reg wb_err;`
148			`reg [31:0] wb_data_o;`
149	4	rudi
150			`////////////////////////////////////////////////////////////////////`
151			`//`
152			`// Memory Go Logic`
153			`//`
154
155	8	rudi	assign mem_sel = `MC_MEM_SEL;
156	4	rudi
157	12	rudi	`always @(posedge clk or posedge rst)`
158			`if(rst) rmw_en <= #1 1'b0;`
159	4	rudi	`else`
160	16	rudi	`if(wb_ack_o) rmw_en <= #1 1'b1;`
161	4	rudi	`else`
162			`if(!wb_cyc_i) rmw_en <= #1 1'b0;`
163
164	18	rudi	`always @(posedge clk or posedge rst)`
165			`if(rst) rmw_r <= #1 1'b0;`
166			`else rmw_r <= #1 !wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en;`
167	4	rudi
168			`assign rmw = rmw_r \| (!wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en);`
169
170	18	rudi	`always @(posedge clk or posedge rst)`
171			`if(rst) read_go_r1 <= #1 1'b0;`
172			`else read_go_r1 <= #1 !rmw & wb_cyc_i &`
173			`((wb_stb_i & mem_sel & !wb_we_i) \| read_go_r);`
174	4	rudi
175	18	rudi	`always @(posedge clk or posedge rst)`
176			`if(rst) read_go_r <= #1 1'b0;`
177			`else read_go_r <= #1 read_go_r1 & wb_cyc_i;`
178	4	rudi
179	16	rudi	`assign wb_read_go = !rmw & read_go_r1 & wb_cyc_i;`
180	4	rudi
181	18	rudi	`always @(posedge clk or posedge rst)`
182			`if(rst) write_go_r1 <= #1 1'b0;`
183			`else write_go_r1 <= #1 wb_cyc_i &`
184			`((wb_stb_i & mem_sel & wb_we_i) \| write_go_r);`
185	4	rudi
186	18	rudi	`always @(posedge clk or posedge rst)`
187			`if(rst) write_go_r <= #1 1'b0;`
188			`else write_go_r <= #1 write_go_r1 & wb_cyc_i &`
189			`((wb_we_i & wb_stb_i) \| !wb_stb_i);`
190	4	rudi
191	16	rudi	`assign wb_write_go = !rmw & write_go_r1 & wb_cyc_i &`
192	4	rudi	`((wb_we_i & wb_stb_i) \| !wb_stb_i);`
193
194			`assign wb_first_set = mem_sel & wb_cyc_i & wb_stb_i & !(read_go_r \| write_go_r);`
195	16	rudi	`assign wb_first = wb_first_set \| (wb_first_r & !wb_ack_o & !wb_err);`
196	4	rudi
197	12	rudi	`always @(posedge clk or posedge rst)`
198			`if(rst) wb_first_r <= #1 1'b0;`
199	4	rudi	`else`
200			`if(wb_first_set) wb_first_r <= #1 1'b1;`
201			`else`
202	16	rudi	`if(wb_ack_o \| wb_err) wb_first_r <= #1 1'b0;`
203	4	rudi
204	18	rudi	`always @(posedge clk or posedge rst)`
205			`if(rst) wr_hold <= #1 1'b0;`
206			`else`
207	4	rudi	`if(wb_cyc_i & wb_stb_i) wr_hold <= #1 wb_we_i;`
208
209			`////////////////////////////////////////////////////////////////////`
210			`//`
211			`// WB Ack`
212			`//`
213
214	18	rudi	`always @(posedge clk or posedge rst)`
215			`if(rst) wb_ack_o <= #1 1'b0;`
216			else wb_ack_o <= #1 `MC_MEM_SEL ? mem_ack :
217			`MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o;
218	4	rudi
219	18	rudi	`always @(posedge clk or posedge rst)`
220			`if(rst) wb_err <= #1 1'b0;`
221			else wb_err <= #1 wb_cyc_i & wb_stb_i & `MC_MEM_SEL &
222			`(par_err \| err \| wp_err) & !wb_err;`
223	16	rudi
224	4	rudi	`////////////////////////////////////////////////////////////////////`
225			`//`
226			`// Memory Wait Logic`
227			`//`
228
229			`assign wb_wait = wb_cyc_i & !wb_stb_i & (wb_write_go \| wb_read_go);`
230
231	16	rudi	`////////////////////////////////////////////////////////////////////`
232			`//`
233			`// WISHBONE Data Output`
234			`//`
235
236			`always @(posedge clk)`
237			wb_data_o <= #1 `MC_MEM_SEL ? mem_dout : rf_dout;
238
239	4	rudi	`endmodule`

Browse

Tools

Subversion Repositories mem_ctrl

[/] [mem_ctrl/] [trunk/] [rtl/] [verilog/] [mc_wb_if.v] - Blame information for rev 18