OpenCores
URL https://opencores.org/ocsvn/mem_ctrl/mem_ctrl/trunk

Subversion Repositories mem_ctrl

[/] [mem_ctrl/] [trunk/] [rtl/] [verilog/] [mc_wb_if.v] - Blame information for rev 28

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 rudi
/////////////////////////////////////////////////////////////////////
2
////                                                             ////
3
////  WISHBONE Memory Controller                                 ////
4
////  WISHBONE Interface                                         ////
5
////                                                             ////
6
////                                                             ////
7
////  Author: Rudolf Usselmann                                   ////
8
////          rudi@asics.ws                                      ////
9
////                                                             ////
10
////                                                             ////
11
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
12
////                                                             ////
13
/////////////////////////////////////////////////////////////////////
14
////                                                             ////
15 22 rudi
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
16
////                         www.asics.ws                        ////
17
////                         rudi@asics.ws                       ////
18 4 rudi
////                                                             ////
19
//// This source file may be used and distributed without        ////
20
//// restriction provided that this copyright statement is not   ////
21
//// removed from the file and that any derivative work contains ////
22
//// the original copyright notice and the associated disclaimer.////
23
////                                                             ////
24
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
25
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
26
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
27
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
28
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
29
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
30
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
31
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
32
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
33
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
34
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
35
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
36
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
37
////                                                             ////
38
/////////////////////////////////////////////////////////////////////
39
 
40
//  CVS Log
41
//
42 22 rudi
//  $Id: mc_wb_if.v,v 1.6 2002-01-21 13:08:52 rudi Exp $
43 4 rudi
//
44 22 rudi
//  $Date: 2002-01-21 13:08:52 $
45
//  $Revision: 1.6 $
46 4 rudi
//  $Author: rudi $
47
//  $Locker:  $
48
//  $State: Exp $
49
//
50
// Change History:
51
//               $Log: not supported by cvs2svn $
52 22 rudi
//               Revision 1.5  2001/12/11 02:47:19  rudi
53
//
54
//               - Made some changes not to expect clock during reset ...
55
//
56 18 rudi
//               Revision 1.4  2001/11/29 02:16:28  rudi
57
//
58
//
59
//               - More Synthesis cleanup, mostly for speed
60
//               - Several bug fixes
61
//               - Changed code to avoid auto-precharge and
62
//                 burst-terminate combinations (apparently illegal ?)
63
//                 Now we will do a manual precharge ...
64
//
65 16 rudi
//               Revision 1.3  2001/09/24 00:38:21  rudi
66
//
67
//               Changed Reset to be active high and async.
68
//
69 12 rudi
//               Revision 1.2  2001/08/10 08:16:21  rudi
70
//
71
//               - Changed IO names to be more clear.
72
//               - Uniquifyed define names to be core specific.
73
//               - Removed "Refresh Early" configuration
74
//
75 8 rudi
//               Revision 1.1  2001/07/29 07:34:41  rudi
76
//
77
//
78
//               1) Changed Directory Structure
79
//               2) Fixed several minor bugs
80
//
81 4 rudi
//               Revision 1.3  2001/06/12 15:19:49  rudi
82
//
83
//
84 16 rudi
//              Minor changes after running lint, and a small bug
85
//              fix reading csr and ba_mask registers.
86 4 rudi
//
87
//               Revision 1.2  2001/06/03 11:37:17  rudi
88
//
89
//
90
//               1) Fixed Chip Select Mask Register
91
//                      - Power On Value is now all ones
92
//                      - Comparison Logic is now correct
93
//
94
//               2) All resets are now asynchronous
95
//
96
//               3) Converted Power On Delay to an configurable item
97
//
98
//               4) Added reset to Chip Select Output Registers
99
//
100
//               5) Forcing all outputs to Hi-Z state during reset
101
//
102
//               Revision 1.1.1.1  2001/05/13 09:39:47  rudi
103
//               Created Directory Structure
104
//
105
//
106
//
107
//
108
 
109
`include "mc_defines.v"
110
 
111
module mc_wb_if(clk, rst,
112
                wb_addr_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_err, wb_ack_o,
113
                wb_read_go, wb_write_go,
114 16 rudi
                wb_first, wb_wait, mem_ack, wr_hold,
115
                err, par_err, wp_err,
116
                wb_data_o, mem_dout, rf_dout);
117 4 rudi
 
118
input           clk, rst;
119
input   [31:0]   wb_addr_i;
120
input           wb_cyc_i;
121
input           wb_stb_i;
122
input           wb_we_i;
123 16 rudi
output          wb_err;
124 4 rudi
output          wb_ack_o;
125
output          wb_read_go;
126
output          wb_write_go;
127
output          wb_first;
128
output          wb_wait;
129
input           mem_ack;
130
output          wr_hold;
131 16 rudi
input           err, par_err, wp_err;
132
output  [31:0]   wb_data_o;
133
input   [31:0]   mem_dout, rf_dout;
134 4 rudi
 
135
////////////////////////////////////////////////////////////////////
136
//
137
// Local Wires and Registers
138
//
139
 
140
wire            mem_sel;
141
reg             read_go_r;
142
reg             read_go_r1;
143
reg             write_go_r;
144
reg             write_go_r1;
145
reg             wb_first_r;
146
wire            wb_first_set;
147
reg             wr_hold;
148
wire            rmw;
149
reg             rmw_r;
150
reg             rmw_en;
151 16 rudi
reg             wb_ack_o;
152
reg             wb_err;
153
reg     [31:0]   wb_data_o;
154 4 rudi
 
155
////////////////////////////////////////////////////////////////////
156
//
157
// Memory Go Logic
158
//
159
 
160 8 rudi
assign mem_sel = `MC_MEM_SEL;
161 4 rudi
 
162 12 rudi
always @(posedge clk or posedge rst)
163
        if(rst)                 rmw_en <= #1 1'b0;
164 4 rudi
        else
165 16 rudi
        if(wb_ack_o)            rmw_en <= #1 1'b1;
166 4 rudi
        else
167
        if(!wb_cyc_i)           rmw_en <= #1 1'b0;
168
 
169 18 rudi
always @(posedge clk or posedge rst)
170
        if(rst) rmw_r <= #1 1'b0;
171
        else    rmw_r <= #1 !wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en;
172 4 rudi
 
173
assign rmw = rmw_r | (!wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en);
174
 
175 18 rudi
always @(posedge clk or posedge rst)
176
        if(rst) read_go_r1 <= #1 1'b0;
177
        else    read_go_r1 <= #1 !rmw & wb_cyc_i &
178
                                ((wb_stb_i & mem_sel & !wb_we_i) | read_go_r);
179 4 rudi
 
180 18 rudi
always @(posedge clk or posedge rst)
181
        if(rst) read_go_r <= #1 1'b0;
182
        else    read_go_r <= #1 read_go_r1 & wb_cyc_i;
183 4 rudi
 
184 16 rudi
assign  wb_read_go = !rmw & read_go_r1 & wb_cyc_i;
185 4 rudi
 
186 18 rudi
always @(posedge clk or posedge rst)
187
        if(rst) write_go_r1 <= #1 1'b0;
188
        else    write_go_r1 <= #1 wb_cyc_i &
189
                                ((wb_stb_i & mem_sel & wb_we_i) | write_go_r);
190 4 rudi
 
191 18 rudi
always @(posedge clk or posedge rst)
192
        if(rst)         write_go_r <= #1 1'b0;
193
        else            write_go_r <= #1 write_go_r1 & wb_cyc_i &
194
                                        ((wb_we_i & wb_stb_i) | !wb_stb_i);
195 4 rudi
 
196 16 rudi
assign wb_write_go =    !rmw & write_go_r1 & wb_cyc_i &
197 4 rudi
                        ((wb_we_i & wb_stb_i) | !wb_stb_i);
198
 
199
assign wb_first_set = mem_sel & wb_cyc_i & wb_stb_i & !(read_go_r | write_go_r);
200 16 rudi
assign wb_first = wb_first_set | (wb_first_r & !wb_ack_o & !wb_err);
201 4 rudi
 
202 12 rudi
always @(posedge clk or posedge rst)
203
        if(rst)                 wb_first_r <= #1 1'b0;
204 4 rudi
        else
205
        if(wb_first_set)        wb_first_r <= #1 1'b1;
206
        else
207 16 rudi
        if(wb_ack_o | wb_err)   wb_first_r <= #1 1'b0;
208 4 rudi
 
209 18 rudi
always @(posedge clk or posedge rst)
210
        if(rst)                 wr_hold <= #1 1'b0;
211
        else
212 4 rudi
        if(wb_cyc_i & wb_stb_i) wr_hold <= #1 wb_we_i;
213
 
214
////////////////////////////////////////////////////////////////////
215
//
216
// WB Ack
217
//
218
 
219 22 rudi
wire    wb_err_d;
220
 
221
// Ack no longer asserted when wb_err is asserted
222 18 rudi
always @(posedge clk or posedge rst)
223
        if(rst) wb_ack_o <= #1 1'b0;
224 22 rudi
        else    wb_ack_o <= #1 `MC_MEM_SEL ? mem_ack & !wb_err_d :
225 18 rudi
                                `MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o;
226 4 rudi
 
227 22 rudi
assign wb_err_d = wb_cyc_i & wb_stb_i & (par_err | err | wp_err);
228
 
229 18 rudi
always @(posedge clk or posedge rst)
230
        if(rst) wb_err <= #1 1'b0;
231 22 rudi
        else    wb_err <= #1 `MC_MEM_SEL & wb_err_d & !wb_err;
232 16 rudi
 
233 4 rudi
////////////////////////////////////////////////////////////////////
234
//
235
// Memory Wait Logic
236
//
237
 
238
assign wb_wait = wb_cyc_i & !wb_stb_i & (wb_write_go | wb_read_go);
239
 
240 16 rudi
////////////////////////////////////////////////////////////////////
241
//
242
// WISHBONE Data Output
243
//
244
 
245
always @(posedge clk)
246
        wb_data_o <= #1 `MC_MEM_SEL ? mem_dout : rf_dout;
247
 
248 4 rudi
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.