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[/] [mem_ctrl/] [trunk/] [rtl/] [verilog/] [mc_wb_if.v] - Blame information for rev 4

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Memory Controller                                 ////
////  WISHBONE Interface                                         ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: mc_wb_if.v,v 1.1 2001-07-29 07:34:41 rudi Exp $
//
//  $Date: 2001-07-29 07:34:41 $
//  $Revision: 1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.3  2001/06/12 15:19:49  rudi
//
//
//               Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
//
//               Revision 1.2  2001/06/03 11:37:17  rudi
//
//
//               1) Fixed Chip Select Mask Register
//                      - Power On Value is now all ones
//                      - Comparison Logic is now correct
//
//               2) All resets are now asynchronous
//
//               3) Converted Power On Delay to an configurable item
//
//               4) Added reset to Chip Select Output Registers
//
//               5) Forcing all outputs to Hi-Z state during reset
//
//               Revision 1.1.1.1  2001/05/13 09:39:47  rudi
//               Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_wb_if(clk, rst,
                wb_addr_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_err, wb_ack_o,
                wb_read_go, wb_write_go,
                wb_first, wb_wait, mem_ack, wr_hold);
 
input           clk, rst;
input   [31:0]   wb_addr_i;
input           wb_cyc_i;
input           wb_stb_i;
input           wb_we_i;
input           wb_err;
output          wb_ack_o;
output          wb_read_go;
output          wb_write_go;
output          wb_first;
output          wb_wait;
input           mem_ack;
output          wr_hold;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
 
wire            mem_sel;
reg             read_go_r;
reg             read_go_r1;
reg             write_go_r;
reg             write_go_r1;
reg             wb_first_r;
wire            wb_first_set;
reg             wr_hold;
wire            rmw;
reg             rmw_r;
reg             rmw_en;
 
////////////////////////////////////////////////////////////////////
//
// Memory Go Logic
//
 
assign mem_sel = `MEM_SEL;
 
always @(posedge clk or negedge rst)
        if(!rst)                rmw_en <= #1 1'b0;
        else
        if(mem_ack)             rmw_en <= #1 1'b1;
        else
        if(!wb_cyc_i)           rmw_en <= #1 1'b0;
 
always @(posedge clk)
        rmw_r <= #1 !wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en;
 
assign rmw = rmw_r | (!wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en);
 
 
always @(posedge clk)
        read_go_r1 <= #1 !rmw & wb_cyc_i & ((wb_stb_i & mem_sel & !wb_we_i) | read_go_r);
 
always @(posedge clk)
        read_go_r <= #1 read_go_r1 & wb_cyc_i;
 
assign  wb_read_go   =  !rmw & read_go_r1 & wb_cyc_i;
 
always @(posedge clk)
        write_go_r1 <= #1 wb_cyc_i & ((wb_stb_i & mem_sel & wb_we_i) | write_go_r);
 
always @(posedge clk)
        //write_go_r <= #1 write_go_r1 & wb_cyc_i;
        write_go_r <= #1 write_go_r1 & wb_cyc_i &
                        ((wb_we_i & wb_stb_i) | !wb_stb_i);
 
assign wb_write_go   = !rmw & write_go_r1 & wb_cyc_i &
                        ((wb_we_i & wb_stb_i) | !wb_stb_i);
 
assign wb_first_set = mem_sel & wb_cyc_i & wb_stb_i & !(read_go_r | write_go_r);
assign wb_first = wb_first_set | (wb_first_r & !mem_ack & !wb_err);
 
always @(posedge clk or negedge rst)
        if(!rst)                wb_first_r <= #1 1'b0;
        else
        if(wb_first_set)        wb_first_r <= #1 1'b1;
        else
        if(mem_ack | wb_err)    wb_first_r <= #1 1'b0;
 
always @(posedge clk)
        if(wb_cyc_i & wb_stb_i) wr_hold <= #1 wb_we_i;
 
////////////////////////////////////////////////////////////////////
//
// WB Ack
//
 
assign wb_ack_o = mem_ack;
 
////////////////////////////////////////////////////////////////////
//
// Memory Wait Logic
//
 
assign wb_wait = wb_cyc_i & !wb_stb_i & (wb_write_go | wb_read_go);
 
endmodule

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Memory Controller ////`
4			`//// WISHBONE Interface ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2000 Rudolf Usselmann ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41			`// $Id: mc_wb_if.v,v 1.1 2001-07-29 07:34:41 rudi Exp $`
42			`//`
43			`// $Date: 2001-07-29 07:34:41 $`
44			`// $Revision: 1.1 $`
45			`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51			`// Revision 1.3 2001/06/12 15:19:49 rudi`
52			`//`
53			`//`
54			`// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.`
55			`//`
56			`// Revision 1.2 2001/06/03 11:37:17 rudi`
57			`//`
58			`//`
59			`// 1) Fixed Chip Select Mask Register`
60			`// - Power On Value is now all ones`
61			`// - Comparison Logic is now correct`
62			`//`
63			`// 2) All resets are now asynchronous`
64			`//`
65			`// 3) Converted Power On Delay to an configurable item`
66			`//`
67			`// 4) Added reset to Chip Select Output Registers`
68			`//`
69			`// 5) Forcing all outputs to Hi-Z state during reset`
70			`//`
71			`// Revision 1.1.1.1 2001/05/13 09:39:47 rudi`
72			`// Created Directory Structure`
73			`//`
74			`//`
75			`//`
76			`//`
77
78			`include "mc_defines.v"
79
80			`module mc_wb_if(clk, rst,`
81			`wb_addr_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_err, wb_ack_o,`
82			`wb_read_go, wb_write_go,`
83			`wb_first, wb_wait, mem_ack, wr_hold);`
84
85			`input clk, rst;`
86			`input [31:0] wb_addr_i;`
87			`input wb_cyc_i;`
88			`input wb_stb_i;`
89			`input wb_we_i;`
90			`input wb_err;`
91			`output wb_ack_o;`
92			`output wb_read_go;`
93			`output wb_write_go;`
94			`output wb_first;`
95			`output wb_wait;`
96			`input mem_ack;`
97			`output wr_hold;`
98
99			`////////////////////////////////////////////////////////////////////`
100			`//`
101			`// Local Wires and Registers`
102			`//`
103
104			`wire mem_sel;`
105			`reg read_go_r;`
106			`reg read_go_r1;`
107			`reg write_go_r;`
108			`reg write_go_r1;`
109			`reg wb_first_r;`
110			`wire wb_first_set;`
111			`reg wr_hold;`
112			`wire rmw;`
113			`reg rmw_r;`
114			`reg rmw_en;`
115
116			`////////////////////////////////////////////////////////////////////`
117			`//`
118			`// Memory Go Logic`
119			`//`
120
121			assign mem_sel = `MEM_SEL;
122
123			`always @(posedge clk or negedge rst)`
124			`if(!rst) rmw_en <= #1 1'b0;`
125			`else`
126			`if(mem_ack) rmw_en <= #1 1'b1;`
127			`else`
128			`if(!wb_cyc_i) rmw_en <= #1 1'b0;`
129
130			`always @(posedge clk)`
131			`rmw_r <= #1 !wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en;`
132
133			`assign rmw = rmw_r \| (!wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en);`
134
135
136			`always @(posedge clk)`
137			`read_go_r1 <= #1 !rmw & wb_cyc_i & ((wb_stb_i & mem_sel & !wb_we_i) \| read_go_r);`
138
139			`always @(posedge clk)`
140			`read_go_r <= #1 read_go_r1 & wb_cyc_i;`
141
142			`assign wb_read_go = !rmw & read_go_r1 & wb_cyc_i;`
143
144			`always @(posedge clk)`
145			`write_go_r1 <= #1 wb_cyc_i & ((wb_stb_i & mem_sel & wb_we_i) \| write_go_r);`
146
147			`always @(posedge clk)`
148			`//write_go_r <= #1 write_go_r1 & wb_cyc_i;`
149			`write_go_r <= #1 write_go_r1 & wb_cyc_i &`
150			`((wb_we_i & wb_stb_i) \| !wb_stb_i);`
151
152			`assign wb_write_go = !rmw & write_go_r1 & wb_cyc_i &`
153			`((wb_we_i & wb_stb_i) \| !wb_stb_i);`
154
155			`assign wb_first_set = mem_sel & wb_cyc_i & wb_stb_i & !(read_go_r \| write_go_r);`
156			`assign wb_first = wb_first_set \| (wb_first_r & !mem_ack & !wb_err);`
157
158			`always @(posedge clk or negedge rst)`
159			`if(!rst) wb_first_r <= #1 1'b0;`
160			`else`
161			`if(wb_first_set) wb_first_r <= #1 1'b1;`
162			`else`
163			`if(mem_ack \| wb_err) wb_first_r <= #1 1'b0;`
164
165			`always @(posedge clk)`
166			`if(wb_cyc_i & wb_stb_i) wr_hold <= #1 wb_we_i;`
167
168			`////////////////////////////////////////////////////////////////////`
169			`//`
170			`// WB Ack`
171			`//`
172
173			`assign wb_ack_o = mem_ack;`
174
175			`////////////////////////////////////////////////////////////////////`
176			`//`
177			`// Memory Wait Logic`
178			`//`
179
180			`assign wb_wait = wb_cyc_i & !wb_stb_i & (wb_write_go \| wb_read_go);`
181
182			`endmodule`

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[/] [mem_ctrl/] [trunk/] [rtl/] [verilog/] [mc_wb_if.v] - Blame information for rev 4