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[/] [memory_cores/] [trunk/] [FIFO/] [FIFO_TB.vhd] - Blame information for rev 25

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-------------------------------------------------------------------------------
-- Title      : FIFO Test Bench
-- Project    : Memory Cores/FIFO
-------------------------------------------------------------------------------
-- File        : FIFO_TB.VHD
-- Author      : Jamil Khatib  <khatib@ieee.org>
-- Organization: OpenIPCore Project
-- Created     : 2000/02/29
-- Last update : 2000/02/29
-- Platform    : 
-- Simulators  : Modelsim 5.2EE / Windows98
-- Synthesizers: 
-- Target      :
-- Dependency  : It uses VHDL 93 file syntax
-------------------------------------------------------------------------------
-- Description: FIFO Test bench
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
-- 
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it under the terms of the Openip General Public
-- License as it is going to be published by the OpenIPCore Organization and
-- any coming versions of this license.
-- You can check the draft license at
-- http://www.openip.org/oc/license.html
 
-------------------------------------------------------------------------------
-- Revisions  :
-- Revision Number : 1
-- Version              :   0.1
-- Date             :   24th Feb 2000
-- Modifier     :   Jamil Khatib (khatib@ieee.org)
-- Desccription :       Created
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.STD_LOGIC_UNSIGNED.all;
 
use std.textio.all;
 
 
entity fifo_tb is
        -- Generic declarations of the tested unit
        generic(
                WIDTH : INTEGER := 8;
                ADD_WIDTH : INTEGER := 4 );
end fifo_tb;
 
architecture TB_ARCHITECTURE of fifo_tb is
 
        constant MAX_STATES : integer := 16;
 
        type TEST_VECTORS is record
                WE : std_logic;    -- Write signal
                RE : std_logic;    -- Read  signal
        end record;
 
        type TABLE_typ is array (0 to MAX_STATES - 1 ) of TEST_VECTORS;
 
        signal TABLE : TABLE_typ;
 
        file l_file: TEXT open write_mode is "fifo.log";
 
        --INITs the table
        procedure init_table(signal L_TABLE: INOUT TABLE_typ
        ) is
        begin
                L_TABLE <= (
                                        ('0','0'), --nn
                                        ('1','0'), --wn
                                        ('1','0'), --wn
                                        ('1','1'), --wr
                                        ('1','1'), --wr
                                        ('0','1'), --nr
                                        ('0','1'), --nr
                                        ('0','1'), --nr
                                        ('1','0'), --wn
                                        ('1','1'), --wr
                                        ('1','0'), --wn
                                        ('0','1'), --nr
                                        ('0','1'), --nr
                                        ('0','1'), --nr
                                        ('1','1'), --wr
                                        ('0','0')  --nn
                                   );
 
        end;
 
        -- Component declaration of the tested unit
        component FIFO
        generic(
                WIDTH : INTEGER := 8;
                ADD_WIDTH : INTEGER := 4 );
        port(
                Data_In : in std_logic_vector((WIDTH-1) downto 0);
                Data_Out : out std_logic_vector((WIDTH-1) downto 0);
                clk : in std_logic;
                reset : in std_logic;
                RE : in std_logic;
                WE : in std_logic;
                Full : out std_logic;
                Half_full : out std_logic;
                Empty : out std_logic );
end component;
 
        -- Stimulus signals - signals mapped to the input and inout ports of tested entity
        signal Data_In : std_logic_vector((WIDTH-1) downto 0);
        signal clk : std_logic :='0';
        signal reset : std_logic;
        signal RE : std_logic;
        signal WE : std_logic;
        -- Observed signals - signals mapped to the output ports of tested entity
        signal Data_Out : std_logic_vector((WIDTH-1) downto 0);
        signal Full : std_logic;
        signal Half_full : std_logic;
        signal Empty : std_logic;
 
 
 
begin
 
 
        -- Unit Under Test port map
        UUT : FIFO
                port map
                        (Data_In => Data_In,
                        Data_Out => Data_Out,
                        clk => clk,
                        reset => reset,
                        RE => RE,
                        WE => WE,
                        Full => Full,
                        Half_full => Half_full,
                        Empty => Empty );
 
-- Clock generation
        clk <= not clk after 40 ns;
 
-- Reset generation
        reset <= transport '0',
                 '1' after 20 ns;
 
-- WE signal stimuls generation
        write_proc: process(clk,reset)
        variable count  : integer;
    variable l : line;
 
        begin
                if reset = '0' then
 
                count := 0;
                data_in <= (others => '0');
 
                init_table(TABLE);
 
                write(l,' ');
                writeline(l_file,l);
 
                write(l,'=');--"=======RESET========",right,20);
                write(l,'=');
                write(l,'R');
                write(l,'S');
                write(l,'T');
                write(l,'=');
                write(l,'=');
                write(l,'@');
                write(l,now);
 
                writeline(l_file,l);
 
                we <= '0';
 
                elsif clk = '0' then
 
                        count := count +1;
                        if count > (MAX_STATES-1) or count < 0 then
                                count := 0;
 
                        end if;
                        data_in <= data_in + 1;
 
                        we <= TABLE(count).WE;
 
                        write(l,'W');write(l,'E');
                        write(l,'=');write(l,conv_integer(we));
                        write(l,' ');
                        write(l,conv_integer(data_in));
                        write(l,'@');
                        write(l,now);
 
                        writeline(l_file,l);
                end if;
        end process write_proc;
 
 
-- RE signal stimuls generation
        read_proc: process(clk,reset)
                variable l : line;
                variable count  : integer;
        begin
                if reset = '0' then
 
                        count := 0;
 
                        re <= '0';
 
                elsif clk = '0' then
 
                        count := count +1;
                        if count > (MAX_STATES-1)  or count < 0 then
                                count := 0;
 
                        end if;
 
                        re <= TABLE(count).RE;
 
                        write(l,'R');write(l,'E');
                        write(l,'=');write(l,conv_integer(re));
                        write(l,' ');
                        write(l,conv_integer(data_out));
                        write(l,'@');
                        write(l,now);
 
                        writeline(l_file,l);
 
 
                end if;
        end process read_proc;
 
-- diff pointer
        ptr_proc: process(WE,RE,reset)
                variable diff_ptr : integer;
                variable l : line;
        begin
 
        if reset = '0' then
 
                diff_ptr := 0;
 
        end if;
 
        if WE = '1' then
                diff_ptr := diff_ptr + 1;
        end if;
 
        if RE = '1' then
                diff_ptr := diff_ptr - 1;
        end if;
 
        write(l,'d');write(l,'f');write(l,'f');
        write(l,'=');write(l,conv_integer(diff_ptr));
        write(l,'@');write(l,now);
        writeline(l_file,l);
 
        end process ptr_proc;
 
-- clock monitor process
        clk_proc: process(clk)
                variable l : line;
        begin
                if clk = '1' then
 
                        write(l,' ');
                        writeline(l_file,l);
 
                        write(l,'*');write(l,'*');write(l,'*');
                        write(l,'c');write(l,'l');write(l,'k');
                        write(l,'@');
                        write(l,now);
 
                        writeline(l_file,l);
 
                end if;
 
        end process     clk_proc;
 
 
-- flags monitor process
        flags_proc: process(full,half_full,empty)
                variable l : line;
        begin
 
                if full = '1'  then
                        write(l,'!');
                        write(l,'F');write(l,'U');write(l,'L');
                        write(l,'@');
                        write(l,now);
 
                        writeline(l_file,l);
 
                end if;
 
                if half_full = '1'  then
 
                        write(l,'H');write(l,'L');write(l,'F');
                        write(l,'@');
                        write(l,now);
 
                        writeline(l_file,l);
                end if;
 
                if empty = '1' then
                        write(l,'!');
                        write(l,'E');write(l,'M');write(l,'P');
                        write(l,'@');
                        write(l,now);
 
                        writeline(l_file,l);
 
                end if;
 
        end process     flags_proc;
 
 
end TB_ARCHITECTURE;
 
configuration TESTBENCH_FOR_FIFO of fifo_tb is
        for TB_ARCHITECTURE
                for UUT : FIFO
                        use entity work.FIFO(FIFO_v7);
                end for;
        end for;
end TESTBENCH_FOR_FIFO;
 
 
 

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[/] [memory_cores/] [trunk/] [FIFO/] [FIFO_TB.vhd] - Blame information for rev 25

Line No.	Rev	Author	Line
1	13	khatib	`-------------------------------------------------------------------------------`
2			`-- Title : FIFO Test Bench`
3			`-- Project : Memory Cores/FIFO`
4			`-------------------------------------------------------------------------------`
5			`-- File : FIFO_TB.VHD`
6			`-- Author : Jamil Khatib <khatib@ieee.org>`
7			`-- Organization: OpenIPCore Project`
8			`-- Created : 2000/02/29`
9			`-- Last update : 2000/02/29`
10			`-- Platform :`
11			`-- Simulators : Modelsim 5.2EE / Windows98`
12			`-- Synthesizers:`
13			`-- Target :`
14			`-- Dependency : It uses VHDL 93 file syntax`
15			`-------------------------------------------------------------------------------`
16			`-- Description: FIFO Test bench`
17			`-------------------------------------------------------------------------------`
18			`-- Copyright (c) 2000 Jamil Khatib`
19			`--`
20			`-- This VHDL design file is an open design; you can redistribute it and/or`
21			`-- modify it and/or implement it under the terms of the Openip General Public`
22			`-- License as it is going to be published by the OpenIPCore Organization and`
23			`-- any coming versions of this license.`
24			`-- You can check the draft license at`
25			`-- http://www.openip.org/oc/license.html`
26
27			`-------------------------------------------------------------------------------`
28			`-- Revisions :`
29			`-- Revision Number : 1`
30			`-- Version : 0.1`
31			`-- Date : 24th Feb 2000`
32			`-- Modifier : Jamil Khatib (khatib@ieee.org)`
33			`-- Desccription : Created`
34			`--`
35			`-------------------------------------------------------------------------------`
36
37			`library ieee;`
38			`use ieee.std_logic_arith.all;`
39			`use ieee.std_logic_1164.all;`
40			`use ieee.STD_LOGIC_UNSIGNED.all;`
41
42			`use std.textio.all;`
43
44
45			`entity fifo_tb is`
46			`-- Generic declarations of the tested unit`
47			`generic(`
48			`WIDTH : INTEGER := 8;`
49			`ADD_WIDTH : INTEGER := 4 );`
50			`end fifo_tb;`
51
52			`architecture TB_ARCHITECTURE of fifo_tb is`
53
54			`constant MAX_STATES : integer := 16;`
55
56			`type TEST_VECTORS is record`
57			`WE : std_logic; -- Write signal`
58			`RE : std_logic; -- Read signal`
59			`end record;`
60
61			`type TABLE_typ is array (0 to MAX_STATES - 1 ) of TEST_VECTORS;`
62
63			`signal TABLE : TABLE_typ;`
64
65			`file l_file: TEXT open write_mode is "fifo.log";`
66
67			`--INITs the table`
68			`procedure init_table(signal L_TABLE: INOUT TABLE_typ`
69			`) is`
70			`begin`
71			`L_TABLE <= (`
72			`('0','0'), --nn`
73			`('1','0'), --wn`
74			`('1','0'), --wn`
75			`('1','1'), --wr`
76			`('1','1'), --wr`
77			`('0','1'), --nr`
78			`('0','1'), --nr`
79			`('0','1'), --nr`
80			`('1','0'), --wn`
81			`('1','1'), --wr`
82			`('1','0'), --wn`
83			`('0','1'), --nr`
84			`('0','1'), --nr`
85			`('0','1'), --nr`
86			`('1','1'), --wr`
87			`('0','0') --nn`
88			`);`
89
90			`end;`
91
92			`-- Component declaration of the tested unit`
93			`component FIFO`
94			`generic(`
95			`WIDTH : INTEGER := 8;`
96			`ADD_WIDTH : INTEGER := 4 );`
97			`port(`
98			`Data_In : in std_logic_vector((WIDTH-1) downto 0);`
99			`Data_Out : out std_logic_vector((WIDTH-1) downto 0);`
100			`clk : in std_logic;`
101			`reset : in std_logic;`
102			`RE : in std_logic;`
103			`WE : in std_logic;`
104			`Full : out std_logic;`
105			`Half_full : out std_logic;`
106			`Empty : out std_logic );`
107			`end component;`
108
109			`-- Stimulus signals - signals mapped to the input and inout ports of tested entity`
110			`signal Data_In : std_logic_vector((WIDTH-1) downto 0);`
111			`signal clk : std_logic :='0';`
112			`signal reset : std_logic;`
113			`signal RE : std_logic;`
114			`signal WE : std_logic;`
115			`-- Observed signals - signals mapped to the output ports of tested entity`
116			`signal Data_Out : std_logic_vector((WIDTH-1) downto 0);`
117			`signal Full : std_logic;`
118			`signal Half_full : std_logic;`
119			`signal Empty : std_logic;`
120
121
122
123			`begin`
124
125
126			`-- Unit Under Test port map`
127			`UUT : FIFO`
128			`port map`
129			`(Data_In => Data_In,`
130			`Data_Out => Data_Out,`
131			`clk => clk,`
132			`reset => reset,`
133			`RE => RE,`
134			`WE => WE,`
135			`Full => Full,`
136			`Half_full => Half_full,`
137			`Empty => Empty );`
138
139			`-- Clock generation`
140			`clk <= not clk after 40 ns;`
141
142			`-- Reset generation`
143			`reset <= transport '0',`
144			`'1' after 20 ns;`
145
146			`-- WE signal stimuls generation`
147			`write_proc: process(clk,reset)`
148			`variable count : integer;`
149			`variable l : line;`
150
151			`begin`
152			`if reset = '0' then`
153
154			`count := 0;`
155			`data_in <= (others => '0');`
156
157			`init_table(TABLE);`
158
159			`write(l,' ');`
160			`writeline(l_file,l);`
161
162			`write(l,'=');--"=======RESET========",right,20);`
163			`write(l,'=');`
164			`write(l,'R');`
165			`write(l,'S');`
166			`write(l,'T');`
167			`write(l,'=');`
168			`write(l,'=');`
169			`write(l,'@');`
170			`write(l,now);`
171
172			`writeline(l_file,l);`
173
174			`we <= '0';`
175
176			`elsif clk = '0' then`
177
178			`count := count +1;`
179			`if count > (MAX_STATES-1) or count < 0 then`
180			`count := 0;`
181
182			`end if;`
183			`data_in <= data_in + 1;`
184
185			`we <= TABLE(count).WE;`
186
187			`write(l,'W');write(l,'E');`
188			`write(l,'=');write(l,conv_integer(we));`
189			`write(l,' ');`
190			`write(l,conv_integer(data_in));`
191			`write(l,'@');`
192			`write(l,now);`
193
194			`writeline(l_file,l);`
195			`end if;`
196			`end process write_proc;`
197
198
199			`-- RE signal stimuls generation`
200			`read_proc: process(clk,reset)`
201			`variable l : line;`
202			`variable count : integer;`
203			`begin`
204			`if reset = '0' then`
205
206			`count := 0;`
207
208			`re <= '0';`
209
210			`elsif clk = '0' then`
211
212			`count := count +1;`
213			`if count > (MAX_STATES-1) or count < 0 then`
214			`count := 0;`
215
216			`end if;`
217
218			`re <= TABLE(count).RE;`
219
220			`write(l,'R');write(l,'E');`
221			`write(l,'=');write(l,conv_integer(re));`
222			`write(l,' ');`
223			`write(l,conv_integer(data_out));`
224			`write(l,'@');`
225			`write(l,now);`
226
227			`writeline(l_file,l);`
228
229
230			`end if;`
231			`end process read_proc;`
232
233			`-- diff pointer`
234			`ptr_proc: process(WE,RE,reset)`
235			`variable diff_ptr : integer;`
236			`variable l : line;`
237			`begin`
238
239			`if reset = '0' then`
240
241			`diff_ptr := 0;`
242
243			`end if;`
244
245			`if WE = '1' then`
246			`diff_ptr := diff_ptr + 1;`
247			`end if;`
248
249			`if RE = '1' then`
250			`diff_ptr := diff_ptr - 1;`
251			`end if;`
252
253			`write(l,'d');write(l,'f');write(l,'f');`
254			`write(l,'=');write(l,conv_integer(diff_ptr));`
255			`write(l,'@');write(l,now);`
256			`writeline(l_file,l);`
257
258			`end process ptr_proc;`
259
260			`-- clock monitor process`
261			`clk_proc: process(clk)`
262			`variable l : line;`
263			`begin`
264			`if clk = '1' then`
265
266			`write(l,' ');`
267			`writeline(l_file,l);`
268
269			`write(l,'');write(l,'');write(l,'*');`
270			`write(l,'c');write(l,'l');write(l,'k');`
271			`write(l,'@');`
272			`write(l,now);`
273
274			`writeline(l_file,l);`
275
276			`end if;`
277
278			`end process clk_proc;`
279
280
281			`-- flags monitor process`
282			`flags_proc: process(full,half_full,empty)`
283			`variable l : line;`
284			`begin`
285
286			`if full = '1' then`
287			`write(l,'!');`
288			`write(l,'F');write(l,'U');write(l,'L');`
289			`write(l,'@');`
290			`write(l,now);`
291
292			`writeline(l_file,l);`
293
294			`end if;`
295
296			`if half_full = '1' then`
297
298			`write(l,'H');write(l,'L');write(l,'F');`
299			`write(l,'@');`
300			`write(l,now);`
301
302			`writeline(l_file,l);`
303			`end if;`
304
305			`if empty = '1' then`
306			`write(l,'!');`
307			`write(l,'E');write(l,'M');write(l,'P');`
308			`write(l,'@');`
309			`write(l,now);`
310
311			`writeline(l_file,l);`
312
313			`end if;`
314
315			`end process flags_proc;`
316
317
318			`end TB_ARCHITECTURE;`
319
320			`configuration TESTBENCH_FOR_FIFO of fifo_tb is`
321			`for TB_ARCHITECTURE`
322			`for UUT : FIFO`
323			`use entity work.FIFO(FIFO_v7);`
324			`end for;`
325			`end for;`
326			`end TESTBENCH_FOR_FIFO;`
327
328
329