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[/] [memory_cores/] [trunk/] [FIFO/] [fifo.vhdl] - Blame information for rev 25

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1 8 khatib 
-------------------------------------------------------------------------------
2 
--
3 
-- Copyright Jamil Khatib 1999
4 
--
5 
--
6 
-- This VHDL design file is an open design; you can redistribute it and/or
7 
-- modify it and/or implement it under the terms of the Openip General Public
8 
-- License as it is going to be published by the OpenIP Organization and any
9 
-- coming versions of this license.
10 
-- You can check the draft license at
11 
-- http://www.openip.org/oc/license.html
12 
--
13 
--
14 
-- Creator : Jamil Khatib
15 
-- Date 10/10/99
16 
--
17 
-- version 0.19991226
18 
--
19 
-- This file was tested on the ModelSim 5.2EE
20 
-- The test vecors for model sim is included in vectors.do file
21 
-- This VHDL design file is proved through simulation but not verified on Silicon
22 
--
23 
--
24 
-------------------------------------------------------------------------------
25 
-------------------------------------------------------------------------------
26 
 
27 
 
28 
LIBRARY ieee;
29 
USE ieee.std_logic_1164.ALL;
30 
 
31 14 khatib 
USE ieee.std_logic_unsigned.ALL;
32 8 khatib 
 
33 
 
34 
 
35 
-- Dual port Memory core
36 
 
37 
 
38 
 
39 
ENTITY dpmem IS
40 
generic ( ADD_WIDTH: integer := 8 ;
41 
                 WIDTH : integer := 8);
42 
  PORT (
43 
    clk      : IN  std_logic;                                -- write clock
44 
    reset    : IN  std_logic;                                -- System Reset
45 
    W_add    : IN  std_logic_vector(add_width -1 downto 0);  -- Write Address
46 
    R_add    : IN  std_logic_vector(add_width -1 downto 0);  -- Read Address
47 
    Data_In  : IN  std_logic_vector(WIDTH - 1  DOWNTO 0);    -- input data
48 
    Data_Out : OUT std_logic_vector(WIDTH -1   DOWNTO 0);    -- output Data
49 
    WR       : IN  std_logic;                                -- Write Enable
50 
    RE       : IN  std_logic);                               -- Read Enable
51 
END dpmem;
52 
 
53 
-------------------------------------------------------------------------------
54 
-------------------------------------------------------------------------------
55 
 
56 
ARCHITECTURE dpmem_v3 OF dpmem IS
57 
 
58 
 
59 
  TYPE data_array IS ARRAY (integer range <>) OF std_logic_vector(WIDTH -1  DOWNTO 0);
60 
                                        -- Memory Type
61 
  SIGNAL data : data_array(0 to (2** add_width) );  -- Local data
62 
 
63 
 
64 
 
65 
  procedure init_mem(signal memory_cell : inout data_array ) is
66 
  begin
67 
 
68 
    for i in 0 to (2** add_width) loop
69 
      memory_cell(i) <= (others => '0');
70 
    end loop;
71 
 
72 
  end init_mem;
73 
 
74 
 
75 
BEGIN  -- dpmem_v3
76 
 
77 
  PROCESS (clk, reset)
78 
 
79 
  BEGIN  -- PROCESS
80 
 
81 
 
82 
    -- activities triggered by asynchronous reset (active low)
83 
    IF reset = '0' THEN
84 
      data_out <= (OTHERS => '1');
85 
      init_mem ( data);
86 
 
87 
      -- activities triggered by rising edge of clock
88 
    ELSIF clk'event AND clk = '1' THEN
89 
      IF RE = '1' THEN
90 
        data_out <= data(conv_integer(R_add));
91 
      else
92 
        data_out <= (OTHERS => '1');    -- Defualt value
93 
      END IF;
94 
 
95 
      IF WR = '1' THEN
96 
        data(conv_integeR(W_add)) <= Data_In;
97 
      END IF;
98 
    END IF;
99 
 
100 
 
101 
 
102 
  END PROCESS;
103 
 
104 
 
105 
END dpmem_v3;
106 
 
107 
 
108 
-------------------------------------------------------------------------------
109 
-------------------------------------------------------------------------------
110 
 
111 
library ieee;
112 
use ieee.std_logic_1164.all;
113 
USE ieee.std_logic_signed.ALL;
114 
USE ieee.std_logic_arith.ALL;
115 
 
116 
 
117 
entity FIFO is
118 
 
119 
    generic (WIDTH : integer := 8;      -- FIFO word width
120 
             ADD_WIDTH : integer := 8); -- Address Width
121 
 
122 
    port (Data_in : in std_logic_vector(WIDTH - 1 downto 0);  -- Input data
123 
          Data_out : out std_logic_vector(WIDTH - 1 downto 0);  -- Out put data
124 
          clk : in std_logic;           -- System Clock
125 
          Reset : in std_logic;         -- System global Reset
126 
          RE : in std_logic;            -- Read Enable
127 
          WE : in std_logic;            -- Write Enable
128 
          Full : buffer std_logic;      -- Full Flag
129 
          Half_full : out std_logic;    -- Half Full Flag
130 
          Empty : buffer std_logic);    -- Empty Flag
131 
 
132 
end FIFO;
133 
 
134 
-------------------------------------------------------------------------------
135 
-------------------------------------------------------------------------------
136 
 
137 
-- Input data _is_ latched
138 
 
139 
library ieee;
140 
use ieee.std_logic_1164.all;
141 
use ieee.numeric_std.all;
142 
--USE ieee.std_logic_signed.ALL;
143 
--USE ieee.std_logic_arith.ALL;
144 
 
145 
-------------------------------------------------------------------------------
146 
-- purpose: FIFO Architecture
147 
architecture FIFO_v1 of FIFO is
148 
 
149 
-- constant values
150 
        constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
151 
        constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
152 17 khatib 
        constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
153 
 
154 8 khatib 
 
155 
        signal Data_in_del : std_logic_vector(WIDTH - 1 downto 0);  -- delayed Data in
156 
 
157 
 
158 
    signal R_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Read Address
159 
    signal W_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Write Address
160 
        signal D_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Diff Address
161 
 
162 
    signal REN_INT : std_logic;                 -- Internal Read Enable
163 
    signal WEN_INT : std_logic;                 -- Internal Write Enable
164 
 
165 
        component dpmem
166 
            generic (ADD_WIDTH : integer := 8;
167 
                                 WIDTH : integer := 8 );
168 
 
169 
        port (clk : in std_logic;
170 
            reset : in std_logic;
171 
                w_add : in std_logic_vector(ADD_WIDTH -1  downto 0 );
172 
            r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
173 
            data_in : in std_logic_vector(WIDTH - 1 downto 0);
174 
            data_out : out std_logic_vector(WIDTH - 1 downto 0 );
175 
            WR  : in std_logic;
176 
            RE  : in std_logic);
177 
        end component;
178 
 
179 
 
180 
 
181 
begin  -- FIFO_v1
182 
-------------------------------------------------------------------------------
183 
 
184 
memcore: dpmem
185 
generic map (WIDTH => 8,
186 
                                ADD_WIDTH =>8)
187 
        port map (clk => clk,
188 
                         reset => reset,
189 
                         w_add => w_add,
190 
                         r_add => r_add,
191 
                         Data_in => data_in_del,
192 
                         data_out => data_out,
193 
                         wr => wen_int,
194 
                         re => ren_int);
195 
 
196 
-------------------------------------------------------------------------------
197 
 
198 
Sync_data: process(clk,reset)
199 
        begin -- process Sync_data
200 
                if reset ='0' then
201 
                        data_in_del <= (others =>'0');
202 
 
203 
                elsif clk'event and clk = '1'  then
204 
                        data_in_del <= data_in;
205 
                else
206 
                        data_in_del <= data_in_del;
207 
                end if;
208 
 
209 
 
210 
        end process Sync_data;
211 
 
212 
-------------------------------------------------------------------------------
213 
 
214 
wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0';
215 
 
216 
ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0';
217 
 
218 
--w_r_gen: process(we,re,FULL,EMPTY)
219 
 
220 
--begin
221 
 
222 
--      if WE = '1' and (FULL = '0') then
223 
--                      wen_int <= '1';
224 
--        else
225 
--                      wen_int <= '0';
226 
 
227 
--    end if;
228 
 
229 
--      if RE = '1' and ( EMPTY = '0') then
230 
--              ren_int <= '1';
231 
--     else
232 
--              ren_int <= '0';
233 
--    end if;
234 
 
235 
--end process w_r_gen;
236 
 
237 
-------------------------------------------------------------------------------
238 
 
239 
 
240 
Add_gen: process(clk,reset)
241 
        variable q1 : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Counter state
242 
        variable q2 : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Counter state
243 
        variable q3 : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Counter state
244 
 
245 
   begin  -- process ADD_gen
246 
 
247 
       -- activities triggered by asynchronous reset (active low)
248 
       if reset = '0' then
249 
                        q1 := (others =>'0');
250 
                        q2 := (others =>'0');
251 
                        q3 := (others =>'0');
252 
--                      wen_int <= '0';
253 
--                      ren_int <= '0';
254 
       -- activities triggered by rising edge of clock
255 
       elsif clk'event and clk = '1'  then
256 
 
257 
                if WE = '1' and ( FULL = '0') then
258 
                        q1 := q1 + 1;
259 
                        q3 := q3 +1;
260 
                   --   wen_int <= '1';
261 
        else
262 
                        q1 := q1;
263 
                        q3 := q3;
264 
                        --wen_int <= '0';
265 
 
266 
            end if;
267 
 
268 
                if RE = '1' and ( EMPTY = '0') then
269 
                        q2 := q2 + 1;
270 
                        q3 := q3 -1;
271 
                        --ren_int <= '1';
272 
        else
273 
                        q2 := q2;
274 
                        q3 := q3;
275 
                        --ren_int <= '0';
276 
            end if;
277 
 
278 
       end if;
279 
 
280 
            R_ADD  <= q2;
281 
                W_ADD  <= q1;
282 
                D_ADD  <= q3;
283 
 
284 
   end process ADD_gen;
285 
 
286 
-------------------------------------------------------------------------------
287 
 
288 
        FULL      <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
289 
        EMPTY     <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) =  MIN_ADDR) else '0';
290 
        HALF_FULL <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) >  HALF_ADDR) else '0';
291 
 
292 
 
293 
-------------------------------------------------------------------------------
294 
 
295 
 
296 
 
297 
end FIFO_v1;
298 
 
299 
-------------------------------------------------------------------------------
300 
-------------------------------------------------------------------------------
301 
-- Ren_int & Wen_int are synchronized with the clock
302 
 
303 
library ieee;
304 
use ieee.std_logic_1164.all;
305 
use ieee.numeric_std.all;
306 
--USE ieee.std_logic_signed.ALL;
307 
--USE ieee.std_logic_arith.ALL;
308 
 
309 
-------------------------------------------------------------------------------
310 
-- purpose: FIFO Architecture
311 
architecture FIFO_v2 of FIFO is
312 
 
313 
-- constant values
314 
        constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
315 
        constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
316 17 khatib 
constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
317 
 
318 8 khatib 
 
319 
    signal R_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Read Address
320 
    signal W_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Write Address
321 
        signal D_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Diff Address
322 
 
323 
    signal REN_INT : std_logic;                 -- Internal Read Enable
324 
    signal WEN_INT : std_logic;                 -- Internal Write Enable
325 
 
326 
        component dpmem
327 
            generic (ADD_WIDTH : integer := 8;
328 
                                 WIDTH : integer := 8 );
329 
 
330 
        port (clk : in std_logic;
331 
            reset : in std_logic;
332 
                w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
333 
            r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
334 
            data_in : in std_logic_vector(WIDTH - 1 downto 0);
335 
            data_out : out std_logic_vector(WIDTH - 1 downto 0 );
336 
            WR  : in std_logic;
337 
            RE  : in std_logic);
338 
        end component;
339 
 
340 
 
341 
 
342 
begin  -- FIFO_v2
343 
 
344 
-------------------------------------------------------------------------------
345 
 
346 
memcore: dpmem
347 
        generic map (WIDTH => 8,
348 
                                ADD_WIDTH =>8)
349 
 
350 
        port map (clk => clk,
351 
                         reset => reset,
352 
                         w_add => w_add,
353 
                         r_add => r_add,
354 
                         Data_in => data_in,
355 
                         data_out => data_out,
356 
                         wr => wen_int,
357 
                         re => ren_int);
358 
 
359 
-------------------------------------------------------------------------------
360 
 
361 
cont_gen: process(clk,reset)
362 
   begin  -- process cont_gen
363 
 
364 
       -- activities triggered by asynchronous reset (active low)
365 
       if reset = '0' then
366 
                        wen_int <= '0';
367 
                        ren_int <= '0';
368 
       -- activities triggered by rising edge of clock
369 
       elsif clk'event and clk = '1'  then
370 
 
371 
                if WE = '1' and (not FULL = '1') then
372 
                        wen_int <= '1';
373 
        else
374 
                        wen_int <= '0';
375 
 
376 
            end if;
377 
 
378 
                if RE = '1' and (not EMPTY = '1') then
379 
                        ren_int <= '1';
380 
        else
381 
                        ren_int <= '0';
382 
            end if;
383 
 
384 
       end if;
385 
 
386 
   end process cont_gen;
387 
 
388 
 
389 
-------------------------------------------------------------------------------
390 
 
391 
Add_gen: process(clk,reset)
392 
        variable q1 : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Counter state
393 
        variable q2 : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Counter state
394 
        variable q3 : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Counter state
395 
 
396 
   begin  -- process ADD_gen
397 
 
398 
       -- activities triggered by asynchronous reset (active low)
399 
       if reset = '0' then
400 
                        q1 := (others =>'0');
401 
                        q2 := (others =>'0');
402 
                        q3 := (others =>'0');
403 
        -- activities triggered by rising edge of clock
404 
       elsif clk'event and clk = '1'  then
405 
 
406 
                if WE = '1' and ( FULL = '0') then
407 
                        q1 := q1 + 1;
408 
                        q3 := q3 +1;
409 
         else
410 
                        q1 := q1;
411 
                        q3 := q3;
412 
 
413 
            end if;
414 
 
415 
                if RE = '1' and ( EMPTY = '0') then
416 
                        q2 := q2 + 1;
417 
                        q3 := q3 -1;
418 
        else
419 
                        q2 := q2;
420 
                        q3 := q3;
421 
            end if;
422 
 
423 
       end if;
424 
 
425 
            R_ADD  <= q2;
426 
                W_ADD  <= q1;
427 
                D_ADD  <= q3;
428 
 
429 
   end process ADD_gen;
430 
 
431 
-------------------------------------------------------------------------------
432 
 
433 
        FULL      <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) =  MAX_ADDR) else '0';
434 
        EMPTY     <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) =  MIN_ADDR) else '0';
435 
        HALF_FULL <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) >  HALF_ADDR) else '0';
436 
 
437 
-------------------------------------------------------------------------------
438 
 
439 
end FIFO_v2;
440 
 
441 
-------------------------------------------------------------------------------
442 
-------------------------------------------------------------------------------
443 
 
444 
-- Input data is _NOT_ latched
445 
 
446 
library ieee;
447 
use ieee.std_logic_1164.all;
448 
use ieee.numeric_std.all;
449 
--USE ieee.std_logic_signed.ALL;
450 
--USE ieee.std_logic_arith.ALL;
451 
 
452 
-------------------------------------------------------------------------------
453 
-- purpose: FIFO Architecture
454 
architecture FIFO_v3 of FIFO is
455 
 
456 
-- constant values
457 
        constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
458 
        constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
459 17 khatib 
        constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
460 8 khatib 
 
461 17 khatib 
 
462 
 
463 8 khatib 
    signal R_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Read Address
464 
    signal W_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Write Address
465 
        signal D_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Diff Address
466 
 
467 
    signal REN_INT : std_logic;                 -- Internal Read Enable
468 
    signal WEN_INT : std_logic;                 -- Internal Write Enable
469 
 
470 
        component dpmem
471 
            generic (ADD_WIDTH : integer := 8;
472 
                                 WIDTH : integer := 8 );
473 
 
474 
        port (clk : in std_logic;
475 
            reset : in std_logic;
476 
                w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
477 
            r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
478 
            data_in : in std_logic_vector(WIDTH - 1 downto 0);
479 
            data_out : out std_logic_vector(WIDTH - 1 downto 0 );
480 
            WR  : in std_logic;
481 
            RE  : in std_logic);
482 
        end component;
483 
 
484 
 
485 
 
486 
begin  -- FIFO_v3
487 
 
488 
-------------------------------------------------------------------------------
489 
 
490 
memcore: dpmem
491 
generic map (WIDTH => 8,
492 
                                ADD_WIDTH =>8)
493 
        port map (clk => clk,
494 
                         reset => reset,
495 
                         w_add => w_add,
496 
                         r_add => r_add,
497 
                         Data_in => data_in,
498 
                         data_out => data_out,
499 
                         wr => wen_int,
500 
                         re => ren_int);
501 
 
502 
-------------------------------------------------------------------------------
503 
 
504 
wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0';
505 
 
506 
ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0';
507 
 
508 
 
509 
-------------------------------------------------------------------------------
510 
 
511 
Add_gen: process(clk,reset)
512 
        variable q1 : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Counter state
513 
        variable q2 : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Counter state
514 
        variable q3 : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Counter state
515 
 
516 
   begin  -- process ADD_gen
517 
 
518 
       -- activities triggered by asynchronous reset (active low)
519 
       if reset = '0' then
520 
                        q1 := (others =>'0');
521 
                        q2 := (others =>'0');
522 
                        q3 := (others =>'0');
523 
       -- activities triggered by rising edge of clock
524 
       elsif clk'event and clk = '1'  then
525 
 
526 
                if WE = '1' and ( FULL = '0') then
527 
                        q1 := q1 + 1;
528 
                        q3 := q3 +1;
529 
        else
530 
                        q1 := q1;
531 
                        q3 := q3;
532 
 
533 
            end if;
534 
 
535 
                if RE = '1' and ( EMPTY = '0') then
536 
                        q2 := q2 + 1;
537 
                        q3 := q3 -1;
538 
        else
539 
                        q2 := q2;
540 
                        q3 := q3;
541 
            end if;
542 
 
543 
       end if;
544 
 
545 
            R_ADD  <= q2;
546 
                W_ADD  <= q1;
547 
                D_ADD  <= q3;
548 
 
549 
   end process ADD_gen;
550 
 
551 
-------------------------------------------------------------------------------
552 
 
553 
        FULL      <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
554 
        EMPTY     <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) =  MIN_ADDR) else '0';
555 
        HALF_FULL <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) >  HALF_ADDR) else '0';
556 
 
557 
 
558 
-------------------------------------------------------------------------------
559 
 
560 
 
561 
end FIFO_v3;
562 
 
563 
 
564 
-------------------------------------------------------------------------------
565 
-------------------------------------------------------------------------------
566 
 
567 
-- This arch was synthesized by webfitter
568 
-- It is the same as fifo_v1 but
569 
-- 1. address variables was changed to signals
570 
-- 2. else statement was removed from process sync_data
571 
-- 3. address-width was changed to 3 instead of 8
572 
-- Input data _is_ latched
573 
 
574 
library ieee;
575 
-- numeric package genertes compile error by webfitter compiler
576 
use ieee.std_logic_1164.all;
577 
USE ieee.std_logic_signed.ALL;
578 
USE ieee.std_logic_arith.ALL;
579 
 
580 
-------------------------------------------------------------------------------
581 
-- purpose: FIFO Architecture
582 
architecture FIFO_v4 of FIFO is
583 
 
584 
-- constant values
585 
        constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
586 
        constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
587 17 khatib 
        constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
588 8 khatib 
 
589 17 khatib 
        constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
590 
 
591 
 
592 8 khatib 
        signal Data_in_del : std_logic_vector(WIDTH - 1 downto 0);  -- delayed Data in
593 
 
594 
 
595 
    signal R_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Read Address
596 
    signal W_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Write Address
597 
        signal D_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Diff Address
598 
 
599 
    signal REN_INT : std_logic;                 -- Internal Read Enable
600 
    signal WEN_INT : std_logic;                 -- Internal Write Enable
601 
 
602 
        component dpmem
603 
            generic (ADD_WIDTH : integer := 8;
604 
                                 WIDTH : integer := 8 );
605 
 
606 
        port (clk : in std_logic;
607 
            reset : in std_logic;
608 
                w_add : in std_logic_vector(ADD_WIDTH -1  downto 0 );
609 
            r_add : in std_logic_vector(ADD_WIDTH -1  downto 0 );
610 
            data_in : in std_logic_vector(WIDTH - 1 downto 0);
611 
            data_out : out std_logic_vector(WIDTH - 1 downto 0 );
612 
            WR  : in std_logic;
613 
            RE  : in std_logic);
614 
        end component;
615 
 
616 
 
617 
 
618 
begin  -- FIFO_v4
619 
-------------------------------------------------------------------------------
620 
 
621 
memcore: dpmem
622 
generic map (WIDTH => 8,
623 
                                ADD_WIDTH =>8)
624 
        port map (clk => clk,
625 
                         reset => reset,
626 
                         w_add => w_add,
627 
                         r_add => r_add,
628 
                         Data_in => data_in_del,
629 
                         data_out => data_out,
630 
                         wr => wen_int,
631 
                         re => ren_int);
632 
 
633 
-------------------------------------------------------------------------------
634 
 
635 
Sync_data: process(clk,reset)
636 
        begin -- process Sync_data
637 
                if reset ='0' then
638 
                        data_in_del <= (others =>'0');
639 
 
640 
                elsif clk'event and clk = '1'  then
641 
                        data_in_del <= data_in;
642 
 
643 
-- else statemnet was removed due to error (hdl
644 
--
645 
                end if;
646 
 
647 
 
648 
        end process Sync_data;
649 
 
650 
-------------------------------------------------------------------------------
651 
 
652 
wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0';
653 
 
654 
ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0';
655 
 
656 
-------------------------------------------------------------------------------
657 
 
658 
 
659 
Add_gen: process(clk,reset)
660 
-- The variables was replaced by add signals
661 
 
662 
   begin  -- process ADD_gen
663 
 
664 
       -- activities triggered by asynchronous reset (active low)
665 
       if reset = '0' then
666 
                        W_ADD <= (others =>'0');
667 
                        R_ADD <= (others =>'0');
668 
                        D_ADD <= (others =>'0');
669 
       -- activities triggered by rising edge of clock
670 
       elsif clk'event and clk = '1'  then
671 
 
672 
                if WE = '1' and ( FULL = '0') then
673 
                        W_ADD <= W_ADD + 1;
674 
                        D_ADD <= D_ADD +1;
675 
--        else
676 
--                      W_ADD <= W_ADD;
677 
--                      D_ADD <= D_ADD;
678 
 
679 
            end if;
680 
 
681 
                if RE = '1' and ( EMPTY = '0') then
682 
                        R_ADD <= R_ADD + 1;
683 
                        D_ADD <= D_ADD -1;
684 
--        else
685 
--                      R_ADD <= R_ADD;
686 
--                      D_ADD <= D_ADD;
687 
            end if;
688 
 
689 
       end if;
690 
 
691 
 
692 
   end process ADD_gen;
693 
 
694 
-------------------------------------------------------------------------------
695 
 
696 
        FULL      <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
697 
        EMPTY     <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) =  MIN_ADDR) else '0';
698 
        HALF_FULL <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) >  HALF_ADDR) else '0';
699 
 
700 
 
701 
-------------------------------------------------------------------------------
702 
 
703 
 
704 
 
705 
end FIFO_v4;
706 
 
707 
-------------------------------------------------------------------------------
708 
 
709 
-------------------------------------------------------------------------------
710 
-------------------------------------------------------------------------------
711 
 
712 
-- synthesized using webfitter
713 
-- Input data is _NOT_ latched
714 
-- The same as fifo_v3 but without the use of the variables in add_gen process
715 
-- else case in add_gen "RE and WE" was removed
716 
 
717 
library ieee;
718 
use ieee.std_logic_1164.all;
719 
--use ieee.numeric_std.all;
720 
USE ieee.std_logic_signed.ALL;
721 
USE ieee.std_logic_arith.ALL;
722 
 
723 
-------------------------------------------------------------------------------
724 
-- purpose: FIFO Architecture
725 
architecture FIFO_v5 of FIFO is
726 
 
727 
-- constant values
728 
        constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
729 
        constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
730 17 khatib 
        constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
731 
 
732 8 khatib 
 
733 
    signal R_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Read Address
734 
    signal W_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Write Address
735 
        signal D_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Diff Address
736 
 
737 
    signal REN_INT : std_logic;                 -- Internal Read Enable
738 
    signal WEN_INT : std_logic;                 -- Internal Write Enable
739 
 
740 
        component dpmem
741 
            generic (ADD_WIDTH : integer := 8;
742 
                                 WIDTH : integer := 8 );
743 
 
744 
        port (clk : in std_logic;
745 
            reset : in std_logic;
746 
                w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
747 
            r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
748 
            data_in : in std_logic_vector(WIDTH - 1 downto 0);
749 
            data_out : out std_logic_vector(WIDTH - 1 downto 0 );
750 
            WR  : in std_logic;
751 
            RE  : in std_logic);
752 
        end component;
753 
 
754 
 
755 
 
756 
begin  -- FIFO_v5
757 
 
758 
-------------------------------------------------------------------------------
759 
 
760 
memcore: dpmem
761 
generic map (WIDTH => 8,
762 
                                ADD_WIDTH =>8)
763 
        port map (clk => clk,
764 
                         reset => reset,
765 
                         w_add => w_add,
766 
                         r_add => r_add,
767 
                         Data_in => data_in,
768 
                         data_out => data_out,
769 
                         wr => wen_int,
770 
                         re => ren_int);
771 
 
772 
-------------------------------------------------------------------------------
773 
 
774 
wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0';
775 
 
776 
ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0';
777 
 
778 
 
779 
-------------------------------------------------------------------------------
780 
 
781 
Add_gen: process(clk,reset)
782 
 
783 
   begin  -- process ADD_gen
784 
 
785 
       -- activities triggered by asynchronous reset (active low)
786 
       if reset = '0' then
787 
                        W_ADD <= (others =>'0');
788 
                        R_ADD <= (others =>'0');
789 
                        D_ADD <= (others =>'0');
790 
       -- activities triggered by rising edge of clock
791 
       elsif clk'event and clk = '1'  then
792 
 
793 
                if WE = '1' and ( FULL = '0') then
794 
                        W_ADD <= W_ADD + 1;
795 
                        D_ADD <= D_ADD +1;
796 
--        else
797 
--                      W_ADD <= W_ADD;
798 
--                      D_ADD <= D_ADD;
799 
 
800 
            end if;
801 
 
802 
                if RE = '1' and ( EMPTY = '0') then
803 
                        R_ADD <= R_ADD + 1;
804 
                        D_ADD <= D_ADD -1;
805 
--        else
806 
--                      R_ADD <= R_ADD;
807 
--                      D_ADD <= D_ADD;
808 
            end if;
809 
 
810 
       end if;
811 
 
812 
--          R_ADD  <= q2;
813 
--              W_ADD  <= q1;
814 
--              D_ADD  <= q3;
815 
 
816 
   end process ADD_gen;
817 
 
818 
-------------------------------------------------------------------------------
819 
 
820 
        FULL      <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
821 
        EMPTY     <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) =  MIN_ADDR) else '0';
822 
        HALF_FULL <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) >  HALF_ADDR) else '0';
823 
 
824 
 
825 
-------------------------------------------------------------------------------
826 
 
827 
 
828 
end FIFO_v5;
829 
 
830 
-------------------------------------------------------------------------------
831 
-------------------------------------------------------------------------------
832 
 
833 9 khatib 
-------------------------------------------------------------------------------
834 
-------------------------------------------------------------------------------
835 
 
836 
-- Exactly teh same as FIFO_v5 but ieee.numeric_std.all is used
837 
 
838 
library ieee;
839 
use ieee.std_logic_1164.all;
840 
use ieee.numeric_std.all;
841 
--USE ieee.std_logic_signed.ALL;
842 
--USE ieee.std_logic_arith.ALL;
843 
 
844 
-------------------------------------------------------------------------------
845 
-- purpose: FIFO Architecture
846 
architecture FIFO_v6 of FIFO is
847 
 
848 
-- constant values
849 
        constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
850 
        constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
851 17 khatib 
        constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
852 9 khatib 
 
853 
    signal R_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Read Address
854 
    signal W_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Write Address
855 
        signal D_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Diff Address
856 
 
857 
    signal REN_INT : std_logic;                 -- Internal Read Enable
858 
    signal WEN_INT : std_logic;                 -- Internal Write Enable
859 
 
860 
        component dpmem
861 
            generic (ADD_WIDTH : integer := 8;
862 
                                 WIDTH : integer := 8 );
863 
 
864 
        port (clk : in std_logic;
865 
            reset : in std_logic;
866 
                w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
867 
            r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
868 
            data_in : in std_logic_vector(WIDTH - 1 downto 0);
869 
            data_out : out std_logic_vector(WIDTH - 1 downto 0 );
870 
            WR  : in std_logic;
871 
            RE  : in std_logic);
872 
        end component;
873 
 
874 
 
875 
 
876 
begin  -- FIFO_v6
877 
 
878 
-------------------------------------------------------------------------------
879 
 
880 
memcore: dpmem
881 
generic map (WIDTH => 8,
882 
                                ADD_WIDTH =>8)
883 
        port map (clk => clk,
884 
                         reset => reset,
885 
                         w_add => w_add,
886 
                         r_add => r_add,
887 
                         Data_in => data_in,
888 
                         data_out => data_out,
889 
                         wr => wen_int,
890 
                         re => ren_int);
891 
 
892 
-------------------------------------------------------------------------------
893 
 
894 
wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0';
895 
 
896 
ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0';
897 
 
898 
 
899 
-------------------------------------------------------------------------------
900 
 
901 
Add_gen: process(clk,reset)
902 
 
903 
   begin  -- process ADD_gen
904 
 
905 
       -- activities triggered by asynchronous reset (active low)
906 
       if reset = '0' then
907 
                        W_ADD <= (others =>'0');
908 
                        R_ADD <= (others =>'0');
909 
                        D_ADD <= (others =>'0');
910 
       -- activities triggered by rising edge of clock
911 
       elsif clk'event and clk = '1'  then
912 
 
913 
                if WE = '1' and ( FULL = '0') then
914 
                        W_ADD <= W_ADD + 1;
915 
                        D_ADD <= D_ADD +1;
916 
--        else
917 
--                      W_ADD <= W_ADD;
918 
--                      D_ADD <= D_ADD;
919 
 
920 
            end if;
921 
 
922 
                if RE = '1' and ( EMPTY = '0') then
923 
                        R_ADD <= R_ADD + 1;
924 
                        D_ADD <= D_ADD -1;
925 
--        else
926 
--                      R_ADD <= R_ADD;
927 
--                      D_ADD <= D_ADD;
928 
            end if;
929 
 
930 
       end if;
931 
 
932 
--          R_ADD  <= q2;
933 
--              W_ADD  <= q1;
934 
--              D_ADD  <= q3;
935 
 
936 
   end process ADD_gen;
937 
 
938 
-------------------------------------------------------------------------------
939 
 
940 
        FULL      <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
941 
        EMPTY     <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) =  MIN_ADDR) else '0';
942 
        HALF_FULL <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) >  HALF_ADDR) else '0';
943 
 
944 
 
945 
-------------------------------------------------------------------------------
946 
 
947 
 
948 
end FIFO_v6;
949 
 
950 
-------------------------------------------------------------------------------
951 
-------------------------------------------------------------------------------
952 14 khatib 
-------------------------------------------------------------------------------
953 
-------------------------------------------------------------------------------
954 9 khatib 
 
955 14 khatib 
-- 1- Synchronous FIFO
956 
-- 2- Read & write are synchronized to the same clock
957 
-- 3- Input data should be stable one clock after Wr
958 
-- 4-
959 
 
960 
 
961 
library ieee;
962 
use ieee.std_logic_1164.all;
963 
use ieee.std_logic_unsigned.all;
964 
-------------------------------------------------------------------------------
965 
-- purpose: FIFO Architecture
966 
architecture FIFO_v7 of FIFO is
967 
 
968 
-- constant values
969 
        constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
970 
        constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
971 17 khatib 
        constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
972 
 
973 14 khatib 
 
974 
-- Internal signals
975 
    signal R_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Read Address
976 
    signal W_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Write Address
977 
 
978 
    signal REN_INT : std_logic;                 -- Internal Read Enable
979 
    signal WEN_INT : std_logic;                 -- Internal Write Enable
980 
 
981 
--      signal int_full : std_logic;
982 
--      signal int_empty : std_logic;
983 
 
984 
        signal datainREG : std_logic_vector(WIDTH - 1 downto 0); -- Data in regiester
985 
        signal dataoutREG : std_logic_vector(WIDTH - 1 downto 0);        -- Data out regiester
986 
 
987 
 
988 
        component dpmem
989 
            generic (ADD_WIDTH : integer := 4;
990 
                                 WIDTH : integer := 8 );
991 
 
992 
        port (clk : in std_logic;
993 
            reset : in std_logic;
994 
                w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
995 
            r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
996 
            data_in : in std_logic_vector(WIDTH - 1 downto 0);
997 
            data_out : out std_logic_vector(WIDTH - 1 downto 0 );
998 
            WR  : in std_logic;
999 
            RE  : in std_logic);
1000 
        end component;
1001 
 
1002 
 
1003 
 
1004 
begin  -- FIFO_v7
1005 
 
1006 
-------------------------------------------------------------------------------
1007 
 
1008 
memcore: dpmem
1009 
generic map (WIDTH => 8,
1010 
                                ADD_WIDTH =>4)
1011 
        port map (clk => clk,
1012 
                         reset => reset,
1013 
                         w_add => w_add,
1014 
                         r_add => r_add,
1015 
                         Data_in => datainREG,
1016 
                         data_out => dataoutREG,
1017 
                         wr => wen_int,
1018 
                         re => re);
1019 
 
1020 
-------------------------------------------------------------------------------
1021 
 
1022 
Add_gen: process(clk,reset)
1023 
 
1024 
        variable full_var : std_logic;
1025 
        variable empty_var : std_logic;
1026 
        variable half_full_var : std_logic;
1027 
 
1028 
        variable W_ADD_old :  std_logic_vector(ADD_WIDTH -1 downto 0);
1029 
 
1030 
 
1031 
        variable D_ADD : std_logic_vector(add_width -1 downto 0);
1032 
 
1033 
 
1034 
   begin  -- process ADD_gen
1035 
 
1036 
       -- activities triggered by asynchronous reset (active low)
1037 
       if reset = '0' then
1038 
                        W_ADD <= (others =>'0');
1039 
                        R_ADD <= (others =>'0');
1040 
                        D_ADD := (others => '0');
1041 
 
1042 
                        W_ADD_old := (others => '0');
1043 
 
1044 
                        full_var := '0';
1045 
                        empty_var := '1';
1046 
                        half_full_var := '0';
1047 
 
1048 
                        FULL <= full_var;
1049 
                        EMPTY <= empty_var;
1050 
                        HALF_FULL <= half_full_var;
1051 
 
1052 
                        ren_int <= '0';
1053 
                        wen_int <= '0';
1054 
 
1055 
                        datainreg <= (others => '1');
1056 
                        data_out <= (others => '1');
1057 
 
1058 
       -- activities triggered by rising edge of clock
1059 
       elsif clk'event and clk = '1'  then
1060 
 
1061 
                if ren_int = '1' and wen_int = '1' and empty_var = '1' then
1062 
                          data_out <= data_in;
1063 
 
1064 
                else
1065 
 
1066 
                        datainREG <= data_in;
1067 
 
1068 
                    if ren_int = '1' then
1069 
 
1070 
                        data_out <= dataoutREG;
1071 
                        else
1072 
                                data_out <= (others => '1');
1073 
                        end if;
1074 
 
1075 
 
1076 
 
1077 
                        W_ADD <= W_ADD_old;
1078 
 
1079 
                        if WE = '1' then
1080 
                                if  FULL_var = '0' then
1081 
                                        W_ADD_old := W_ADD_old + 1;
1082 
                                        D_ADD := D_ADD +1;
1083 
                                        wen_int <= '1';
1084 
 
1085 
                                else
1086 
                                        wen_int <= '0';
1087 
 
1088 
                                end if;
1089 
 
1090 
                        else
1091 
                                wen_int <= '0';
1092 
 
1093 
                    end if;
1094 
 
1095 
 
1096 
                        if RE = '1' then
1097 
                                if  EMPTY_var = '0' then
1098 
                                        R_ADD <= R_ADD + 1;
1099 
                                        D_ADD := D_ADD -1;
1100 
                                        ren_int <= '1';
1101 
                                else
1102 
                                        ren_int <= '0';
1103 
 
1104 
                                end if;
1105 
 
1106 
                        else
1107 
                                ren_int <= '0';
1108 
                    end if;
1109 
 
1110 
 
1111 
                        full_var := '0';
1112 
                        empty_var := '0';
1113 
                        half_full_var := '0';
1114 
 
1115 
 
1116 
                        if D_ADD = MAX_ADDR then
1117 
                                full_var := '1';
1118 
 
1119 
                        end if;
1120 
 
1121 
                        if D_ADD = MIN_ADDR then
1122 
                                empty_var := '1';
1123 
 
1124 
                        end if;
1125 
 
1126 
                        if D_ADD(ADD_WIDTH -1) = '1' then
1127 
                                half_full_var := '1';
1128 
 
1129 
                        end if;
1130 
 
1131 
                        FULL <= full_var;
1132 
                        EMPTY <= empty_var;
1133 
                        HALF_FULL <= half_full_var;
1134 
 
1135 
 
1136 
                end if;
1137 
          end if;
1138 
 
1139 
   end process ADD_gen;
1140 
 
1141 
-------------------------------------------------------------------------------
1142 
 
1143 
 
1144 
end FIFO_v7;
1145 
-------------------------------------------------------------------------------
1146 
-------------------------------------------------------------------------------
1147 
 
1148 
 
1149 8 khatib 
configuration fifo_conf of fifo is
1150 
        for fifo_v1
1151 
                for memcore:dpmem
1152 
                        use entity work.dpmem(dpmem_v3);
1153 
                end for;
1154 
        end for;
1155 
 
1156 
end fifo_conf;
1157 
 
1158 
 

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