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[/] [memory_cores/] [trunk/] [FIFO/] [fifo.vhdl] - Blame information for rev 8

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1 8 khatib 
-------------------------------------------------------------------------------
2 
--
3 
-- Copyright Jamil Khatib 1999
4 
--
5 
--
6 
-- This VHDL design file is an open design; you can redistribute it and/or
7 
-- modify it and/or implement it under the terms of the Openip General Public
8 
-- License as it is going to be published by the OpenIP Organization and any
9 
-- coming versions of this license.
10 
-- You can check the draft license at
11 
-- http://www.openip.org/oc/license.html
12 
--
13 
--
14 
-- Creator : Jamil Khatib
15 
-- Date 10/10/99
16 
--
17 
-- version 0.19991226
18 
--
19 
-- This file was tested on the ModelSim 5.2EE
20 
-- The test vecors for model sim is included in vectors.do file
21 
-- This VHDL design file is proved through simulation but not verified on Silicon
22 
--
23 
--
24 
-------------------------------------------------------------------------------
25 
-------------------------------------------------------------------------------
26 
 
27 
 
28 
LIBRARY ieee;
29 
USE ieee.std_logic_1164.ALL;
30 
 
31 
USE ieee.std_logic_signed.ALL;
32 
 
33 
 
34 
 
35 
-- Dual port Memory core
36 
 
37 
 
38 
 
39 
ENTITY dpmem IS
40 
generic ( ADD_WIDTH: integer := 8 ;
41 
                 WIDTH : integer := 8);
42 
  PORT (
43 
    clk      : IN  std_logic;                                -- write clock
44 
    reset    : IN  std_logic;                                -- System Reset
45 
    W_add    : IN  std_logic_vector(add_width -1 downto 0);  -- Write Address
46 
    R_add    : IN  std_logic_vector(add_width -1 downto 0);  -- Read Address
47 
    Data_In  : IN  std_logic_vector(WIDTH - 1  DOWNTO 0);    -- input data
48 
    Data_Out : OUT std_logic_vector(WIDTH -1   DOWNTO 0);    -- output Data
49 
    WR       : IN  std_logic;                                -- Write Enable
50 
    RE       : IN  std_logic);                               -- Read Enable
51 
END dpmem;
52 
 
53 
-------------------------------------------------------------------------------
54 
-------------------------------------------------------------------------------
55 
 
56 
ARCHITECTURE dpmem_v3 OF dpmem IS
57 
 
58 
 
59 
  TYPE data_array IS ARRAY (integer range <>) OF std_logic_vector(WIDTH -1  DOWNTO 0);
60 
                                        -- Memory Type
61 
  SIGNAL data : data_array(0 to (2** add_width) );  -- Local data
62 
 
63 
 
64 
 
65 
  procedure init_mem(signal memory_cell : inout data_array ) is
66 
  begin
67 
 
68 
    for i in 0 to (2** add_width) loop
69 
      memory_cell(i) <= (others => '0');
70 
    end loop;
71 
 
72 
  end init_mem;
73 
 
74 
 
75 
BEGIN  -- dpmem_v3
76 
 
77 
  PROCESS (clk, reset)
78 
 
79 
  BEGIN  -- PROCESS
80 
 
81 
 
82 
    -- activities triggered by asynchronous reset (active low)
83 
    IF reset = '0' THEN
84 
      data_out <= (OTHERS => '1');
85 
      init_mem ( data);
86 
 
87 
      -- activities triggered by rising edge of clock
88 
    ELSIF clk'event AND clk = '1' THEN
89 
      IF RE = '1' THEN
90 
        data_out <= data(conv_integer(R_add));
91 
      else
92 
        data_out <= (OTHERS => '1');    -- Defualt value
93 
      END IF;
94 
 
95 
      IF WR = '1' THEN
96 
        data(conv_integeR(W_add)) <= Data_In;
97 
      END IF;
98 
    END IF;
99 
 
100 
 
101 
 
102 
  END PROCESS;
103 
 
104 
 
105 
END dpmem_v3;
106 
 
107 
 
108 
-------------------------------------------------------------------------------
109 
-------------------------------------------------------------------------------
110 
 
111 
library ieee;
112 
use ieee.std_logic_1164.all;
113 
USE ieee.std_logic_signed.ALL;
114 
USE ieee.std_logic_arith.ALL;
115 
 
116 
 
117 
entity FIFO is
118 
 
119 
    generic (WIDTH : integer := 8;      -- FIFO word width
120 
             ADD_WIDTH : integer := 8); -- Address Width
121 
 
122 
    port (Data_in : in std_logic_vector(WIDTH - 1 downto 0);  -- Input data
123 
          Data_out : out std_logic_vector(WIDTH - 1 downto 0);  -- Out put data
124 
          clk : in std_logic;           -- System Clock
125 
          Reset : in std_logic;         -- System global Reset
126 
          RE : in std_logic;            -- Read Enable
127 
          WE : in std_logic;            -- Write Enable
128 
          Full : buffer std_logic;      -- Full Flag
129 
          Half_full : out std_logic;    -- Half Full Flag
130 
          Empty : buffer std_logic);    -- Empty Flag
131 
 
132 
end FIFO;
133 
 
134 
-------------------------------------------------------------------------------
135 
-------------------------------------------------------------------------------
136 
 
137 
-- Input data _is_ latched
138 
 
139 
library ieee;
140 
use ieee.std_logic_1164.all;
141 
use ieee.numeric_std.all;
142 
--USE ieee.std_logic_signed.ALL;
143 
--USE ieee.std_logic_arith.ALL;
144 
 
145 
-------------------------------------------------------------------------------
146 
-- purpose: FIFO Architecture
147 
architecture FIFO_v1 of FIFO is
148 
 
149 
-- constant values
150 
        constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
151 
        constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
152 
        constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) :="01111111";--(ADD_WIDTH -1 downto ADD_WIDTH -1 => '0' ,others => '1');
153 
 
154 
        signal Data_in_del : std_logic_vector(WIDTH - 1 downto 0);  -- delayed Data in
155 
 
156 
 
157 
    signal R_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Read Address
158 
    signal W_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Write Address
159 
        signal D_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Diff Address
160 
 
161 
    signal REN_INT : std_logic;                 -- Internal Read Enable
162 
    signal WEN_INT : std_logic;                 -- Internal Write Enable
163 
 
164 
        component dpmem
165 
            generic (ADD_WIDTH : integer := 8;
166 
                                 WIDTH : integer := 8 );
167 
 
168 
        port (clk : in std_logic;
169 
            reset : in std_logic;
170 
                w_add : in std_logic_vector(ADD_WIDTH -1  downto 0 );
171 
            r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
172 
            data_in : in std_logic_vector(WIDTH - 1 downto 0);
173 
            data_out : out std_logic_vector(WIDTH - 1 downto 0 );
174 
            WR  : in std_logic;
175 
            RE  : in std_logic);
176 
        end component;
177 
 
178 
 
179 
 
180 
begin  -- FIFO_v1
181 
-------------------------------------------------------------------------------
182 
 
183 
memcore: dpmem
184 
generic map (WIDTH => 8,
185 
                                ADD_WIDTH =>8)
186 
        port map (clk => clk,
187 
                         reset => reset,
188 
                         w_add => w_add,
189 
                         r_add => r_add,
190 
                         Data_in => data_in_del,
191 
                         data_out => data_out,
192 
                         wr => wen_int,
193 
                         re => ren_int);
194 
 
195 
-------------------------------------------------------------------------------
196 
 
197 
Sync_data: process(clk,reset)
198 
        begin -- process Sync_data
199 
                if reset ='0' then
200 
                        data_in_del <= (others =>'0');
201 
 
202 
                elsif clk'event and clk = '1'  then
203 
                        data_in_del <= data_in;
204 
                else
205 
                        data_in_del <= data_in_del;
206 
                end if;
207 
 
208 
 
209 
        end process Sync_data;
210 
 
211 
-------------------------------------------------------------------------------
212 
 
213 
wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0';
214 
 
215 
ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0';
216 
 
217 
--w_r_gen: process(we,re,FULL,EMPTY)
218 
 
219 
--begin
220 
 
221 
--      if WE = '1' and (FULL = '0') then
222 
--                      wen_int <= '1';
223 
--        else
224 
--                      wen_int <= '0';
225 
 
226 
--    end if;
227 
 
228 
--      if RE = '1' and ( EMPTY = '0') then
229 
--              ren_int <= '1';
230 
--     else
231 
--              ren_int <= '0';
232 
--    end if;
233 
 
234 
--end process w_r_gen;
235 
 
236 
-------------------------------------------------------------------------------
237 
 
238 
 
239 
Add_gen: process(clk,reset)
240 
        variable q1 : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Counter state
241 
        variable q2 : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Counter state
242 
        variable q3 : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Counter state
243 
 
244 
   begin  -- process ADD_gen
245 
 
246 
       -- activities triggered by asynchronous reset (active low)
247 
       if reset = '0' then
248 
                        q1 := (others =>'0');
249 
                        q2 := (others =>'0');
250 
                        q3 := (others =>'0');
251 
--                      wen_int <= '0';
252 
--                      ren_int <= '0';
253 
       -- activities triggered by rising edge of clock
254 
       elsif clk'event and clk = '1'  then
255 
 
256 
                if WE = '1' and ( FULL = '0') then
257 
                        q1 := q1 + 1;
258 
                        q3 := q3 +1;
259 
                   --   wen_int <= '1';
260 
        else
261 
                        q1 := q1;
262 
                        q3 := q3;
263 
                        --wen_int <= '0';
264 
 
265 
            end if;
266 
 
267 
                if RE = '1' and ( EMPTY = '0') then
268 
                        q2 := q2 + 1;
269 
                        q3 := q3 -1;
270 
                        --ren_int <= '1';
271 
        else
272 
                        q2 := q2;
273 
                        q3 := q3;
274 
                        --ren_int <= '0';
275 
            end if;
276 
 
277 
       end if;
278 
 
279 
            R_ADD  <= q2;
280 
                W_ADD  <= q1;
281 
                D_ADD  <= q3;
282 
 
283 
   end process ADD_gen;
284 
 
285 
-------------------------------------------------------------------------------
286 
 
287 
        FULL      <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
288 
        EMPTY     <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) =  MIN_ADDR) else '0';
289 
        HALF_FULL <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) >  HALF_ADDR) else '0';
290 
 
291 
 
292 
-------------------------------------------------------------------------------
293 
 
294 
 
295 
 
296 
end FIFO_v1;
297 
 
298 
-------------------------------------------------------------------------------
299 
-------------------------------------------------------------------------------
300 
-- Ren_int & Wen_int are synchronized with the clock
301 
 
302 
library ieee;
303 
use ieee.std_logic_1164.all;
304 
use ieee.numeric_std.all;
305 
--USE ieee.std_logic_signed.ALL;
306 
--USE ieee.std_logic_arith.ALL;
307 
 
308 
-------------------------------------------------------------------------------
309 
-- purpose: FIFO Architecture
310 
architecture FIFO_v2 of FIFO is
311 
 
312 
-- constant values
313 
        constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
314 
        constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
315 
        constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := "01111111";--(ADD_WIDTH -1 => '0', others => '1');
316 
 
317 
 
318 
    signal R_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Read Address
319 
    signal W_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Write Address
320 
        signal D_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Diff Address
321 
 
322 
    signal REN_INT : std_logic;                 -- Internal Read Enable
323 
    signal WEN_INT : std_logic;                 -- Internal Write Enable
324 
 
325 
        component dpmem
326 
            generic (ADD_WIDTH : integer := 8;
327 
                                 WIDTH : integer := 8 );
328 
 
329 
        port (clk : in std_logic;
330 
            reset : in std_logic;
331 
                w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
332 
            r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
333 
            data_in : in std_logic_vector(WIDTH - 1 downto 0);
334 
            data_out : out std_logic_vector(WIDTH - 1 downto 0 );
335 
            WR  : in std_logic;
336 
            RE  : in std_logic);
337 
        end component;
338 
 
339 
 
340 
 
341 
begin  -- FIFO_v2
342 
 
343 
-------------------------------------------------------------------------------
344 
 
345 
memcore: dpmem
346 
        generic map (WIDTH => 8,
347 
                                ADD_WIDTH =>8)
348 
 
349 
        port map (clk => clk,
350 
                         reset => reset,
351 
                         w_add => w_add,
352 
                         r_add => r_add,
353 
                         Data_in => data_in,
354 
                         data_out => data_out,
355 
                         wr => wen_int,
356 
                         re => ren_int);
357 
 
358 
-------------------------------------------------------------------------------
359 
 
360 
cont_gen: process(clk,reset)
361 
   begin  -- process cont_gen
362 
 
363 
       -- activities triggered by asynchronous reset (active low)
364 
       if reset = '0' then
365 
                        wen_int <= '0';
366 
                        ren_int <= '0';
367 
       -- activities triggered by rising edge of clock
368 
       elsif clk'event and clk = '1'  then
369 
 
370 
                if WE = '1' and (not FULL = '1') then
371 
                        wen_int <= '1';
372 
        else
373 
                        wen_int <= '0';
374 
 
375 
            end if;
376 
 
377 
                if RE = '1' and (not EMPTY = '1') then
378 
                        ren_int <= '1';
379 
        else
380 
                        ren_int <= '0';
381 
            end if;
382 
 
383 
       end if;
384 
 
385 
   end process cont_gen;
386 
 
387 
 
388 
-------------------------------------------------------------------------------
389 
 
390 
Add_gen: process(clk,reset)
391 
        variable q1 : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Counter state
392 
        variable q2 : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Counter state
393 
        variable q3 : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Counter state
394 
 
395 
   begin  -- process ADD_gen
396 
 
397 
       -- activities triggered by asynchronous reset (active low)
398 
       if reset = '0' then
399 
                        q1 := (others =>'0');
400 
                        q2 := (others =>'0');
401 
                        q3 := (others =>'0');
402 
        -- activities triggered by rising edge of clock
403 
       elsif clk'event and clk = '1'  then
404 
 
405 
                if WE = '1' and ( FULL = '0') then
406 
                        q1 := q1 + 1;
407 
                        q3 := q3 +1;
408 
         else
409 
                        q1 := q1;
410 
                        q3 := q3;
411 
 
412 
            end if;
413 
 
414 
                if RE = '1' and ( EMPTY = '0') then
415 
                        q2 := q2 + 1;
416 
                        q3 := q3 -1;
417 
        else
418 
                        q2 := q2;
419 
                        q3 := q3;
420 
            end if;
421 
 
422 
       end if;
423 
 
424 
            R_ADD  <= q2;
425 
                W_ADD  <= q1;
426 
                D_ADD  <= q3;
427 
 
428 
   end process ADD_gen;
429 
 
430 
-------------------------------------------------------------------------------
431 
 
432 
        FULL      <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) =  MAX_ADDR) else '0';
433 
        EMPTY     <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) =  MIN_ADDR) else '0';
434 
        HALF_FULL <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) >  HALF_ADDR) else '0';
435 
 
436 
-------------------------------------------------------------------------------
437 
 
438 
end FIFO_v2;
439 
 
440 
-------------------------------------------------------------------------------
441 
-------------------------------------------------------------------------------
442 
 
443 
-- Input data is _NOT_ latched
444 
 
445 
library ieee;
446 
use ieee.std_logic_1164.all;
447 
use ieee.numeric_std.all;
448 
--USE ieee.std_logic_signed.ALL;
449 
--USE ieee.std_logic_arith.ALL;
450 
 
451 
-------------------------------------------------------------------------------
452 
-- purpose: FIFO Architecture
453 
architecture FIFO_v3 of FIFO is
454 
 
455 
-- constant values
456 
        constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
457 
        constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
458 
        constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) :="01111111";--(ADD_WIDTH -1 downto ADD_WIDTH -1 => '0' ,others => '1');
459 
 
460 
 
461 
    signal R_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Read Address
462 
    signal W_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Write Address
463 
        signal D_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Diff Address
464 
 
465 
    signal REN_INT : std_logic;                 -- Internal Read Enable
466 
    signal WEN_INT : std_logic;                 -- Internal Write Enable
467 
 
468 
        component dpmem
469 
            generic (ADD_WIDTH : integer := 8;
470 
                                 WIDTH : integer := 8 );
471 
 
472 
        port (clk : in std_logic;
473 
            reset : in std_logic;
474 
                w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
475 
            r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
476 
            data_in : in std_logic_vector(WIDTH - 1 downto 0);
477 
            data_out : out std_logic_vector(WIDTH - 1 downto 0 );
478 
            WR  : in std_logic;
479 
            RE  : in std_logic);
480 
        end component;
481 
 
482 
 
483 
 
484 
begin  -- FIFO_v3
485 
 
486 
-------------------------------------------------------------------------------
487 
 
488 
memcore: dpmem
489 
generic map (WIDTH => 8,
490 
                                ADD_WIDTH =>8)
491 
        port map (clk => clk,
492 
                         reset => reset,
493 
                         w_add => w_add,
494 
                         r_add => r_add,
495 
                         Data_in => data_in,
496 
                         data_out => data_out,
497 
                         wr => wen_int,
498 
                         re => ren_int);
499 
 
500 
-------------------------------------------------------------------------------
501 
 
502 
wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0';
503 
 
504 
ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0';
505 
 
506 
 
507 
-------------------------------------------------------------------------------
508 
 
509 
Add_gen: process(clk,reset)
510 
        variable q1 : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Counter state
511 
        variable q2 : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Counter state
512 
        variable q3 : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Counter state
513 
 
514 
   begin  -- process ADD_gen
515 
 
516 
       -- activities triggered by asynchronous reset (active low)
517 
       if reset = '0' then
518 
                        q1 := (others =>'0');
519 
                        q2 := (others =>'0');
520 
                        q3 := (others =>'0');
521 
       -- activities triggered by rising edge of clock
522 
       elsif clk'event and clk = '1'  then
523 
 
524 
                if WE = '1' and ( FULL = '0') then
525 
                        q1 := q1 + 1;
526 
                        q3 := q3 +1;
527 
        else
528 
                        q1 := q1;
529 
                        q3 := q3;
530 
 
531 
            end if;
532 
 
533 
                if RE = '1' and ( EMPTY = '0') then
534 
                        q2 := q2 + 1;
535 
                        q3 := q3 -1;
536 
        else
537 
                        q2 := q2;
538 
                        q3 := q3;
539 
            end if;
540 
 
541 
       end if;
542 
 
543 
            R_ADD  <= q2;
544 
                W_ADD  <= q1;
545 
                D_ADD  <= q3;
546 
 
547 
   end process ADD_gen;
548 
 
549 
-------------------------------------------------------------------------------
550 
 
551 
        FULL      <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
552 
        EMPTY     <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) =  MIN_ADDR) else '0';
553 
        HALF_FULL <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) >  HALF_ADDR) else '0';
554 
 
555 
 
556 
-------------------------------------------------------------------------------
557 
 
558 
 
559 
end FIFO_v3;
560 
 
561 
 
562 
-------------------------------------------------------------------------------
563 
-------------------------------------------------------------------------------
564 
 
565 
-- This arch was synthesized by webfitter
566 
-- It is the same as fifo_v1 but
567 
-- 1. address variables was changed to signals
568 
-- 2. else statement was removed from process sync_data
569 
-- 3. address-width was changed to 3 instead of 8
570 
-- Input data _is_ latched
571 
 
572 
library ieee;
573 
-- numeric package genertes compile error by webfitter compiler
574 
use ieee.std_logic_1164.all;
575 
USE ieee.std_logic_signed.ALL;
576 
USE ieee.std_logic_arith.ALL;
577 
 
578 
-------------------------------------------------------------------------------
579 
-- purpose: FIFO Architecture
580 
architecture FIFO_v4 of FIFO is
581 
 
582 
-- constant values
583 
        constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
584 
        constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
585 
        constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) :="01111111";--(ADD_WIDTH -1 downto ADD_WIDTH -1 => '0' ,others => '1');
586 
 
587 
        signal Data_in_del : std_logic_vector(WIDTH - 1 downto 0);  -- delayed Data in
588 
 
589 
 
590 
    signal R_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Read Address
591 
    signal W_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Write Address
592 
        signal D_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Diff Address
593 
 
594 
    signal REN_INT : std_logic;                 -- Internal Read Enable
595 
    signal WEN_INT : std_logic;                 -- Internal Write Enable
596 
 
597 
        component dpmem
598 
            generic (ADD_WIDTH : integer := 8;
599 
                                 WIDTH : integer := 8 );
600 
 
601 
        port (clk : in std_logic;
602 
            reset : in std_logic;
603 
                w_add : in std_logic_vector(ADD_WIDTH -1  downto 0 );
604 
            r_add : in std_logic_vector(ADD_WIDTH -1  downto 0 );
605 
            data_in : in std_logic_vector(WIDTH - 1 downto 0);
606 
            data_out : out std_logic_vector(WIDTH - 1 downto 0 );
607 
            WR  : in std_logic;
608 
            RE  : in std_logic);
609 
        end component;
610 
 
611 
 
612 
 
613 
begin  -- FIFO_v4
614 
-------------------------------------------------------------------------------
615 
 
616 
memcore: dpmem
617 
generic map (WIDTH => 8,
618 
                                ADD_WIDTH =>8)
619 
        port map (clk => clk,
620 
                         reset => reset,
621 
                         w_add => w_add,
622 
                         r_add => r_add,
623 
                         Data_in => data_in_del,
624 
                         data_out => data_out,
625 
                         wr => wen_int,
626 
                         re => ren_int);
627 
 
628 
-------------------------------------------------------------------------------
629 
 
630 
Sync_data: process(clk,reset)
631 
        begin -- process Sync_data
632 
                if reset ='0' then
633 
                        data_in_del <= (others =>'0');
634 
 
635 
                elsif clk'event and clk = '1'  then
636 
                        data_in_del <= data_in;
637 
 
638 
-- else statemnet was removed due to error (hdl
639 
--
640 
                end if;
641 
 
642 
 
643 
        end process Sync_data;
644 
 
645 
-------------------------------------------------------------------------------
646 
 
647 
wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0';
648 
 
649 
ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0';
650 
 
651 
-------------------------------------------------------------------------------
652 
 
653 
 
654 
Add_gen: process(clk,reset)
655 
-- The variables was replaced by add signals
656 
 
657 
   begin  -- process ADD_gen
658 
 
659 
       -- activities triggered by asynchronous reset (active low)
660 
       if reset = '0' then
661 
                        W_ADD <= (others =>'0');
662 
                        R_ADD <= (others =>'0');
663 
                        D_ADD <= (others =>'0');
664 
       -- activities triggered by rising edge of clock
665 
       elsif clk'event and clk = '1'  then
666 
 
667 
                if WE = '1' and ( FULL = '0') then
668 
                        W_ADD <= W_ADD + 1;
669 
                        D_ADD <= D_ADD +1;
670 
--        else
671 
--                      W_ADD <= W_ADD;
672 
--                      D_ADD <= D_ADD;
673 
 
674 
            end if;
675 
 
676 
                if RE = '1' and ( EMPTY = '0') then
677 
                        R_ADD <= R_ADD + 1;
678 
                        D_ADD <= D_ADD -1;
679 
--        else
680 
--                      R_ADD <= R_ADD;
681 
--                      D_ADD <= D_ADD;
682 
            end if;
683 
 
684 
       end if;
685 
 
686 
 
687 
   end process ADD_gen;
688 
 
689 
-------------------------------------------------------------------------------
690 
 
691 
        FULL      <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
692 
        EMPTY     <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) =  MIN_ADDR) else '0';
693 
        HALF_FULL <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) >  HALF_ADDR) else '0';
694 
 
695 
 
696 
-------------------------------------------------------------------------------
697 
 
698 
 
699 
 
700 
end FIFO_v4;
701 
 
702 
-------------------------------------------------------------------------------
703 
 
704 
-------------------------------------------------------------------------------
705 
-------------------------------------------------------------------------------
706 
 
707 
-- synthesized using webfitter
708 
-- Input data is _NOT_ latched
709 
-- The same as fifo_v3 but without the use of the variables in add_gen process
710 
-- else case in add_gen "RE and WE" was removed
711 
 
712 
library ieee;
713 
use ieee.std_logic_1164.all;
714 
--use ieee.numeric_std.all;
715 
USE ieee.std_logic_signed.ALL;
716 
USE ieee.std_logic_arith.ALL;
717 
 
718 
-------------------------------------------------------------------------------
719 
-- purpose: FIFO Architecture
720 
architecture FIFO_v5 of FIFO is
721 
 
722 
-- constant values
723 
        constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
724 
        constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
725 
        constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) :="01111111";--(ADD_WIDTH -1 downto ADD_WIDTH -1 => '0' ,others => '1');
726 
 
727 
    signal R_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Read Address
728 
    signal W_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Write Address
729 
        signal D_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Diff Address
730 
 
731 
    signal REN_INT : std_logic;                 -- Internal Read Enable
732 
    signal WEN_INT : std_logic;                 -- Internal Write Enable
733 
 
734 
        component dpmem
735 
            generic (ADD_WIDTH : integer := 8;
736 
                                 WIDTH : integer := 8 );
737 
 
738 
        port (clk : in std_logic;
739 
            reset : in std_logic;
740 
                w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
741 
            r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
742 
            data_in : in std_logic_vector(WIDTH - 1 downto 0);
743 
            data_out : out std_logic_vector(WIDTH - 1 downto 0 );
744 
            WR  : in std_logic;
745 
            RE  : in std_logic);
746 
        end component;
747 
 
748 
 
749 
 
750 
begin  -- FIFO_v5
751 
 
752 
-------------------------------------------------------------------------------
753 
 
754 
memcore: dpmem
755 
generic map (WIDTH => 8,
756 
                                ADD_WIDTH =>8)
757 
        port map (clk => clk,
758 
                         reset => reset,
759 
                         w_add => w_add,
760 
                         r_add => r_add,
761 
                         Data_in => data_in,
762 
                         data_out => data_out,
763 
                         wr => wen_int,
764 
                         re => ren_int);
765 
 
766 
-------------------------------------------------------------------------------
767 
 
768 
wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0';
769 
 
770 
ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0';
771 
 
772 
 
773 
-------------------------------------------------------------------------------
774 
 
775 
Add_gen: process(clk,reset)
776 
 
777 
   begin  -- process ADD_gen
778 
 
779 
       -- activities triggered by asynchronous reset (active low)
780 
       if reset = '0' then
781 
                        W_ADD <= (others =>'0');
782 
                        R_ADD <= (others =>'0');
783 
                        D_ADD <= (others =>'0');
784 
       -- activities triggered by rising edge of clock
785 
       elsif clk'event and clk = '1'  then
786 
 
787 
                if WE = '1' and ( FULL = '0') then
788 
                        W_ADD <= W_ADD + 1;
789 
                        D_ADD <= D_ADD +1;
790 
--        else
791 
--                      W_ADD <= W_ADD;
792 
--                      D_ADD <= D_ADD;
793 
 
794 
            end if;
795 
 
796 
                if RE = '1' and ( EMPTY = '0') then
797 
                        R_ADD <= R_ADD + 1;
798 
                        D_ADD <= D_ADD -1;
799 
--        else
800 
--                      R_ADD <= R_ADD;
801 
--                      D_ADD <= D_ADD;
802 
            end if;
803 
 
804 
       end if;
805 
 
806 
--          R_ADD  <= q2;
807 
--              W_ADD  <= q1;
808 
--              D_ADD  <= q3;
809 
 
810 
   end process ADD_gen;
811 
 
812 
-------------------------------------------------------------------------------
813 
 
814 
        FULL      <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
815 
        EMPTY     <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) =  MIN_ADDR) else '0';
816 
        HALF_FULL <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) >  HALF_ADDR) else '0';
817 
 
818 
 
819 
-------------------------------------------------------------------------------
820 
 
821 
 
822 
end FIFO_v5;
823 
 
824 
-------------------------------------------------------------------------------
825 
-------------------------------------------------------------------------------
826 
 
827 
configuration fifo_conf of fifo is
828 
        for fifo_v1
829 
                for memcore:dpmem
830 
                        use entity work.dpmem(dpmem_v3);
831 
                end for;
832 
        end for;
833 
 
834 
end fifo_conf;
835 
 
836 
 

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