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[/] [mesi_isc/] [trunk/] [sim/] [run_sim] - Blame information for rev 4
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#//////////////////////////////////////////////////////////////////
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#//// ////
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#//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
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#//// ////
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#//// This source file may be used and distributed without ////
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#//// restriction provided that this copyright statement is not ////
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#//// removed from the file and that any derivative work contains ////
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#//// the original copyright notice and the associated disclaimer. ////
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#//// ////
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#//// This source file is free software; you can redistribute it ////
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#//// and/or modify it under the terms of the GNU Lesser General ////
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#//// Public License as published by the Free Software Foundation; ////
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#//// either version 2.1 of the License, or (at your option) any ////
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#//// later version. ////
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#//// ////
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#//// This source is distributed in the hope that it will be ////
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#//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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#//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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#//// PURPOSE. See the GNU Lesser General Public License for more ////
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#//// details. ////
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#//// ////
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#//// You should have received a copy of the GNU Lesser General ////
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#//// Public License along with this source; if not, download it ////
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#//// from http://www.opencores.org/lgpl.shtml ////
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#//// ////
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#//////////////////////////////////////////////////////////////////////
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#//////////////////////////////////////////////////////////////////////
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#//// ////
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#//// MESI_ISC Project ////
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#//// ////
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#//// Author(s): ////
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#//// - Yair Amitay yair.amitay@yahoo.com ////
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#//// www.linkedin.com/in/yairamitay ////
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#//// ////
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#//////////////////////////////////////////////////////////////////////
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\rm mesi_isc.out
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iverilog -o mesi_isc.out \
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-I ../src/rtl \
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-I ../src/tb \
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-y ../src/rtl \
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-y ../src/tb \
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-c sim.cmd \
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-v \
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> iverilog.log
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grep error iverilog.log
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vvp -l sim.log \
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mesi_isc.out
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