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[/] [mesi_isc/] [trunk/] [src/] [rtl/] [mesi_isc_breq_fifos.v] - Blame information for rev 8

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  MESI_ISC Project                                            ////
////                                                              ////
////  Author(s):                                                  ////
////      - Yair Amitay       yair.amitay@yahoo.com               ////
////                          www.linkedin.com/in/yairamitay      ////
////                                                              ////
////  Description                                                 ////
////  mesi_isc_breq_fifos                                         ////
////  -------------------                                         ////
////  Stores all the snoop transactions. Keeps the transactions   ////
////  until the cpu receives the transactions                     ////
////                                                              ////
////  The functional ports of the block are arranged in arrays.   ////
////  Each functional port is an array which contains one signal  ////
////  for each snoop fifo.                                        ////
////  The order of the signals, of width X (each signal has       //// 
////  X-1:0 bits), in the port is described below.                ////
////  All the bits of the first signal are located in the port    ////
////  least significant bits. Then, the second signal is located  ////
////  in the next X bits, etc.                                    ////
////                                                              ////
////  For a port that contains M (M>1) signals of width X (X>0)   ////
////  signal_N[X-1:0] = port[(N+1)*X-1:N*X].                      ////
////                                                              ////
////  For example for a port with 4 signals of 8 bits             ////
////  signal_0[7:0] = port[(N+1)*X-1:N*X] = port[(N+1)*8-1:N*8] = ////
////                = port[(0+1)*8-1:0*8] = port[7:0]             ////
////  signal_1[7:0] = port[(1+1)*8-1:1*8] = port[15:8]            ////
////  signal_2[7:0] = port[(2+1)*8-1:2*8] = port[23:16]           ////
////  signal_3[7:0] = port[(3+1)*8-1:3*8] = port[31:24]           ////
////                                                              ////
////  To Do:                                                      ////
////   -                                                          ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "mesi_isc_define.v"
 
module mesi_isc_breq_fifos
    (
     // Inputs
     clk,
     rst,
     mbus_cmd_array_i,
     mbus_addr_array_i,
     broad_fifo_status_full_i,
     // Outputs
     mbus_ack_array_o,
     broad_fifo_wr_o,
     broad_addr_o,
     broad_type_o,
     broad_cpu_id_o,
     broad_id_o
   );
 
parameter
  MBUS_CMD_WIDTH           = 3,
  ADDR_WIDTH               = 32,
  BROAD_TYPE_WIDTH         = 2,
  BROAD_ID_WIDTH           = 7,
  BREQ_FIFO_SIZE           = 2,
  BREQ_FIFO_SIZE_LOG2      = 1;
 
// Inputs
//================================
// System
input                   clk;          // System clock
input                   rst;          // Active high system reset
 
// Main buses
input [4*MBUS_CMD_WIDTH-1:0] mbus_cmd_array_i; // Main bus command (array)
input [4*ADDR_WIDTH-1:0] mbus_addr_array_i; // Main bus address (array)
 
// From mesi_isc_broad_fifo
input                    broad_fifo_status_full_i; // The broad fifo is full
                                      // and can't receive another broadcast
                                      // request
 
// Outputs
//================================
// Main buses
output [3:0]             mbus_ack_array_o; // Bus acknowledge for receiving the
                                      // broadcast request
// To mesi_isc_broad_fifo
output                   broad_fifo_wr_o; // Write the broadcast request
output [ADDR_WIDTH-1:0]  broad_addr_o; // Address of the broadcast request
output [BROAD_TYPE_WIDTH-1:0] broad_type_o; // Type of the broadcast request
output [1:0]             broad_cpu_id_o; // ID of the initiator CPU
                                      // broad in the broad fifo
output [BROAD_ID_WIDTH-1:0] broad_id_o; // The ID of the broadcast request
 
 
// Regs & wires
//================================
wire [3:0]               fifo_status_empty_array;
wire [3:0]              fifo_status_full_array;
wire [4*ADDR_WIDTH-1:0] broad_addr_array;
wire [4*BROAD_TYPE_WIDTH-1:0] broad_type_array;
wire [4*BROAD_ID_WIDTH-1:0] broad_id_array;
wire [3:0]               fifo_wr_array;
wire [3:0]               fifo_rd_array;
wire [4*BROAD_TYPE_WIDTH-1:0] breq_type_array;
wire [4*2-1:0]          breq_cpu_id_array;
wire [4*BROAD_ID_WIDTH-1:0] breq_id_array;
wire [4*2-1:0]               broad_cpu_id_array;
 
// Breq fifo control
//================================
mesi_isc_breq_fifos_cntl #(MBUS_CMD_WIDTH,
                           ADDR_WIDTH,
                           BROAD_TYPE_WIDTH,
                           BROAD_ID_WIDTH)
   mesi_isc_breq_fifos_cntl
    (
     // Inputs
     .clk                   (clk),
     .rst                   (rst),
     .mbus_cmd_array_i      (mbus_cmd_array_i [4*MBUS_CMD_WIDTH-1     :0]),
     .fifo_status_empty_array_i (fifo_status_empty_array            [3:0]),
     .fifo_status_full_array_i  (fifo_status_full_array             [3:0]),
     .broad_fifo_status_full_i (broad_fifo_status_full_i),
     .broad_addr_array_i    (broad_addr_array  [4*ADDR_WIDTH-1        :0]),
     .broad_type_array_i    (broad_type_array  [4*BROAD_TYPE_WIDTH-1  :0]),
     .broad_id_array_i      (broad_id_array    [4*BROAD_ID_WIDTH-1    :0]),
     // Outputs
     .mbus_ack_array_o      (mbus_ack_array_o                        [3:0]),
     .fifo_wr_array_o       (fifo_wr_array                          [3:0]),
     .fifo_rd_array_o       (fifo_rd_array                          [3:0]),
     .broad_fifo_wr_o       (broad_fifo_wr_o),
     .broad_addr_o          (broad_addr_o      [ADDR_WIDTH-1          :0]),
     .broad_type_o          (broad_type_o      [BROAD_TYPE_WIDTH-1    :0]),
     .broad_cpu_id_o        (broad_cpu_id_o                         [1:0]),
     .broad_id_o            (broad_id_o        [BROAD_ID_WIDTH-1      :0]),
     .breq_type_array_o     (breq_type_array   [4*BROAD_TYPE_WIDTH-1  :0]),
     .breq_cpu_id_array_o   (breq_cpu_id_array [4*2-1                 :0]),
     .breq_id_array_o       (breq_id_array     [4*BROAD_ID_WIDTH-1    :0])
     );
 
// Breq fifo 3
//================================
mesi_isc_basic_fifo #(ADDR_WIDTH         +  // DATA_WIDTH
                      BROAD_TYPE_WIDTH   +
                      2                  +  // BROAD_CPU_ID_WIDTH
                      BROAD_ID_WIDTH,
                      BREQ_FIFO_SIZE,       // FIFO_SIZE
                      BREQ_FIFO_SIZE_LOG2)  // FIFO_SIZE_LOG2
   //  \ /  (\ / marks the fifo ID) 
   fifo_3
    (
     // Inputs
     .clk                   (clk),
     .rst                   (rst),
                            //            \ /
     .wr_i                  (fifo_wr_array[3]),
                            //            \ /
     .rd_i                  (fifo_rd_array[3]),
                            //                 \ /
     .data_i                ({mbus_addr_array_i[(3+1)*ADDR_WIDTH-1:
                            //                          \ /
                                                         3*ADDR_WIDTH],
                            //                 \ /
                              breq_type_array [(3+1)*BROAD_TYPE_WIDTH-1:
                            //                          \ /
                                                         3*BROAD_TYPE_WIDTH],
                            //                  \ /
                              breq_cpu_id_array[(3+1)*2-1:
                            //                          \ /
                                                         3*2],
                            //                 \ /
                              breq_id_array   [(3+1)*BROAD_ID_WIDTH-1:
                            //                          \ /
                                                         3*BROAD_ID_WIDTH]}),
     // Outputs
     //                     //                 \ /
     .data_o                ({broad_addr_array [(3+1)*ADDR_WIDTH-1:
                            //                          \ /
                                                         3*ADDR_WIDTH],
                            //                 \ /
                             broad_type_array  [(3+1)*BROAD_TYPE_WIDTH-1:
                            //                          \ /
                                                         3*BROAD_TYPE_WIDTH],
                            //                  \ /
                             broad_cpu_id_array[(3+1)*2-1:
                            //                          \ /
                                                         3*2],
                            //                 \ /
                             broad_id_array    [(3+1)*BROAD_ID_WIDTH-1:
                            //                          \ /
                                                         3*BROAD_ID_WIDTH]}),
                            //                             \ /
     .status_empty_o        (fifo_status_empty_array       [3]),
                            //                             \ /
     .status_full_o         (fifo_status_full_array        [3])
     );
 
// Breq fifo 2
//================================
mesi_isc_basic_fifo #(ADDR_WIDTH         +  // DATA_WIDTH
                      BROAD_TYPE_WIDTH   +
                      2                  +  // BROAD_CPU_ID_WIDTH
                      BROAD_ID_WIDTH,
                      BREQ_FIFO_SIZE,       // FIFO_SIZE
                      BREQ_FIFO_SIZE_LOG2)  // FIFO_SIZE_LOG2
   //  \ /  (\ / marks the fifo ID) 
   fifo_2
    (
     // Inputs
     .clk                   (clk),
     .rst                   (rst),
                            //            \ /
     .wr_i                  (fifo_wr_array[2]),
                            //            \ /
     .rd_i                  (fifo_rd_array[2]),
                            //                 \ /
     .data_i                ({mbus_addr_array_i[(2+1)*ADDR_WIDTH-1:
                            //                          \ /
                                                         2*ADDR_WIDTH],
                            //                 \ /
                              breq_type_array [(2+1)*BROAD_TYPE_WIDTH-1:
                            //                          \ /
                                                         2*BROAD_TYPE_WIDTH],
                            //                  \ /
                              breq_cpu_id_array[(2+1)*2-1:
                            //                          \ /
                                                         2*2],
                            //                 \ /
                              breq_id_array   [(2+1)*BROAD_ID_WIDTH-1:
                            //                          \ /
                                                         2*BROAD_ID_WIDTH]}),
     // Outputs
     //                     //                 \ /
     .data_o                ({broad_addr_array [(2+1)*ADDR_WIDTH-1:
                            //                          \ /
                                                         2*ADDR_WIDTH],
                            //                 \ /
                             broad_type_array  [(2+1)*BROAD_TYPE_WIDTH-1:
                            //                          \ /
                                                         2*BROAD_TYPE_WIDTH],
                            //                  \ /
                             broad_cpu_id_array[(2+1)*2-1:
                            //                          \ /
                                                         2*2],
                            //                 \ /
                             broad_id_array    [(2+1)*BROAD_ID_WIDTH-1:
                            //                          \ /
                                                         2*BROAD_ID_WIDTH]}),
                            //                             \ /
     .status_empty_o        (fifo_status_empty_array       [2]),
                            //                             \ /
     .status_full_o         (fifo_status_full_array        [2])
     );
 
// Breq fifo 1
//================================
mesi_isc_basic_fifo #(ADDR_WIDTH         +  // DATA_WIDTH
                      BROAD_TYPE_WIDTH   +
                      2                  +  // BROAD_CPU_ID_WIDTH
                      BROAD_ID_WIDTH,
                      BREQ_FIFO_SIZE,       // FIFO_SIZE
                      BREQ_FIFO_SIZE_LOG2)  // FIFO_SIZE_LOG2
   //  \ /  (\ / marks the fifo ID) 
   fifo_1
    (
     // Inputs
     .clk                   (clk),
     .rst                   (rst),
                            //            \ /
     .wr_i                  (fifo_wr_array[1]),
                            //            \ /
     .rd_i                  (fifo_rd_array[1]),
                            //                 \ /
     .data_i                ({mbus_addr_array_i[(1+1)*ADDR_WIDTH-1:
                            //                          \ /
                                                         1*ADDR_WIDTH],
                            //                 \ /
                              breq_type_array [(1+1)*BROAD_TYPE_WIDTH-1:
                            //                          \ /
                                                         1*BROAD_TYPE_WIDTH],
                            //                  \ /
                              breq_cpu_id_array[(1+1)*2-1:
                            //                          \ /
                                                         1*2],
                            //                 \ /
                              breq_id_array   [(1+1)*BROAD_ID_WIDTH-1:
                            //                          \ /
                                                         1*BROAD_ID_WIDTH]}),
     // Outputs
     //                     //                 \ /
     .data_o                ({broad_addr_array [(1+1)*ADDR_WIDTH-1:
                            //                          \ /
                                                         1*ADDR_WIDTH],
                            //                 \ /
                             broad_type_array  [(1+1)*BROAD_TYPE_WIDTH-1:
                            //                          \ /
                                                         1*BROAD_TYPE_WIDTH],
                            //                  \ /
                             broad_cpu_id_array[(1+1)*2-1:
                            //                          \ /
                                                         1*2],
                            //                 \ /
                             broad_id_array    [(1+1)*BROAD_ID_WIDTH-1:
                            //                          \ /
                                                         1*BROAD_ID_WIDTH]}),
                            //                             \ /
     .status_empty_o        (fifo_status_empty_array       [1]),
                            //                             \ /
     .status_full_o         (fifo_status_full_array        [1])
     );
 
// Breq fifo 0
//================================
mesi_isc_basic_fifo #(ADDR_WIDTH         +  // DATA_WIDTH
                      BROAD_TYPE_WIDTH   +
                      2                  +  // BROAD_CPU_ID_WIDTH
                      BROAD_ID_WIDTH,
                      BREQ_FIFO_SIZE,       // FIFO_SIZE
                      BREQ_FIFO_SIZE_LOG2)  // FIFO_SIZE_LOG2
   //  \ /  (\ / marks the fifo ID) 
   fifo_0
    (
     // Inputs
     .clk                   (clk),
     .rst                   (rst),
                            //            \ /
     .wr_i                  (fifo_wr_array[0]),
                            //            \ /
     .rd_i                  (fifo_rd_array[0]),
                            //                 \ /
     .data_i                ({mbus_addr_array_i[(0+1)*ADDR_WIDTH-1:
                            //                          \ /
                                                         0*ADDR_WIDTH],
                            //                 \ /
                              breq_type_array [(0+1)*BROAD_TYPE_WIDTH-1:
                            //                          \ /
                                                         0*BROAD_TYPE_WIDTH],
                            //                  \ /
                              breq_cpu_id_array[(0+1)*2-1:
                            //                          \ /
                                                         0*2],
                            //                 \ /
                              breq_id_array   [(0+1)*BROAD_ID_WIDTH-1:
                            //                          \ /
                                                         0*BROAD_ID_WIDTH]}),
     // Outputs
     //                     //                 \ /
     .data_o                ({broad_addr_array [(0+1)*ADDR_WIDTH-1:
                            //                          \ /
                                                         0*ADDR_WIDTH],
                            //                 \ /
                             broad_type_array  [(0+1)*BROAD_TYPE_WIDTH-1:
                            //                          \ /
                                                         0*BROAD_TYPE_WIDTH],
                            //                  \ /
                             broad_cpu_id_array[(0+1)*2-1:
                            //                          \ /
                                                         0*2],
                            //                 \ /
                             broad_id_array    [(0+1)*BROAD_ID_WIDTH-1:
                            //                          \ /
                                                         0*BROAD_ID_WIDTH]}),
                            //                             \ /
     .status_empty_o        (fifo_status_empty_array       [0]),
                            //                             \ /
     .status_full_o         (fifo_status_full_array        [0])
     );
 
endmodule

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[/] [mesi_isc/] [trunk/] [src/] [rtl/] [mesi_isc_breq_fifos.v] - Blame information for rev 8

Line No.	Rev	Author	Line
1	2	yaira	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Copyright (C) 2009 Authors and OPENCORES.ORG ////`
4			`//// ////`
5			`//// This source file may be used and distributed without ////`
6			`//// restriction provided that this copyright statement is not ////`
7			`//// removed from the file and that any derivative work contains ////`
8			`//// the original copyright notice and the associated disclaimer. ////`
9			`//// ////`
10			`//// This source file is free software; you can redistribute it ////`
11			`//// and/or modify it under the terms of the GNU Lesser General ////`
12			`//// Public License as published by the Free Software Foundation; ////`
13			`//// either version 2.1 of the License, or (at your option) any ////`
14			`//// later version. ////`
15			`//// ////`
16			`//// This source is distributed in the hope that it will be ////`
17			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
18			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
19			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
20			`//// details. ////`
21			`//// ////`
22			`//// You should have received a copy of the GNU Lesser General ////`
23			`//// Public License along with this source; if not, download it ////`
24			`//// from http://www.opencores.org/lgpl.shtml ////`
25			`//// ////`
26			`//////////////////////////////////////////////////////////////////////`
27
28			`//////////////////////////////////////////////////////////////////////`
29			`//// ////`
30			`//// MESI_ISC Project ////`
31			`//// ////`
32			`//// Author(s): ////`
33			`//// - Yair Amitay yair.amitay@yahoo.com ////`
34			`//// www.linkedin.com/in/yairamitay ////`
35			`//// ////`
36			`//// Description ////`
37			`//// mesi_isc_breq_fifos ////`
38			`//// ------------------- ////`
39			`//// Stores all the snoop transactions. Keeps the transactions ////`
40			`//// until the cpu receives the transactions ////`
41			`//// ////`
42			`//// The functional ports of the block are arranged in arrays. ////`
43			`//// Each functional port is an array which contains one signal ////`
44			`//// for each snoop fifo. ////`
45			`//// The order of the signals, of width X (each signal has ////`
46			`//// X-1:0 bits), in the port is described below. ////`
47			`//// All the bits of the first signal are located in the port ////`
48			`//// least significant bits. Then, the second signal is located ////`
49			`//// in the next X bits, etc. ////`
50			`//// ////`
51			`//// For a port that contains M (M>1) signals of width X (X>0) ////`
52			`//// signal_N[X-1:0] = port[(N+1)X-1:NX]. ////`
53			`//// ////`
54			`//// For example for a port with 4 signals of 8 bits ////`
55			`//// signal_0[7:0] = port[(N+1)X-1:NX] = port[(N+1)8-1:N8] = ////`
56			`//// = port[(0+1)8-1:08] = port[7:0] ////`
57			`//// signal_1[7:0] = port[(1+1)8-1:18] = port[15:8] ////`
58			`//// signal_2[7:0] = port[(2+1)8-1:28] = port[23:16] ////`
59			`//// signal_3[7:0] = port[(3+1)8-1:38] = port[31:24] ////`
60			`//// ////`
61			`//// To Do: ////`
62			`//// - ////`
63			`//// ////`
64			`//////////////////////////////////////////////////////////////////////`
65
66			`include "mesi_isc_define.v"
67
68			`module mesi_isc_breq_fifos`
69			`(`
70			`// Inputs`
71			`clk,`
72			`rst,`
73			`mbus_cmd_array_i,`
74			`mbus_addr_array_i,`
75			`broad_fifo_status_full_i,`
76			`// Outputs`
77			`mbus_ack_array_o,`
78			`broad_fifo_wr_o,`
79			`broad_addr_o,`
80			`broad_type_o,`
81			`broad_cpu_id_o,`
82			`broad_id_o`
83			`);`
84
85			`parameter`
86			`MBUS_CMD_WIDTH = 3,`
87			`ADDR_WIDTH = 32,`
88			`BROAD_TYPE_WIDTH = 2,`
89			`BROAD_ID_WIDTH = 7,`
90			`BREQ_FIFO_SIZE = 2,`
91			`BREQ_FIFO_SIZE_LOG2 = 1;`
92
93			`// Inputs`
94			`//================================`
95			`// System`
96			`input clk; // System clock`
97			`input rst; // Active high system reset`
98
99			`// Main buses`
100			`input [4*MBUS_CMD_WIDTH-1:0] mbus_cmd_array_i; // Main bus command (array)`
101			`input [4*ADDR_WIDTH-1:0] mbus_addr_array_i; // Main bus address (array)`
102
103			`// From mesi_isc_broad_fifo`
104			`input broad_fifo_status_full_i; // The broad fifo is full`
105			`// and can't receive another broadcast`
106			`// request`
107
108			`// Outputs`
109			`//================================`
110			`// Main buses`
111			`output [3:0] mbus_ack_array_o; // Bus acknowledge for receiving the`
112			`// broadcast request`
113			`// To mesi_isc_broad_fifo`
114			`output broad_fifo_wr_o; // Write the broadcast request`
115			`output [ADDR_WIDTH-1:0] broad_addr_o; // Address of the broadcast request`
116			`output [BROAD_TYPE_WIDTH-1:0] broad_type_o; // Type of the broadcast request`
117			`output [1:0] broad_cpu_id_o; // ID of the initiator CPU`
118			`// broad in the broad fifo`
119			`output [BROAD_ID_WIDTH-1:0] broad_id_o; // The ID of the broadcast request`
120
121
122			`// Regs & wires`
123			`//================================`
124			`wire [3:0] fifo_status_empty_array;`
125			`wire [3:0] fifo_status_full_array;`
126			`wire [4*ADDR_WIDTH-1:0] broad_addr_array;`
127			`wire [4*BROAD_TYPE_WIDTH-1:0] broad_type_array;`
128			`wire [4*BROAD_ID_WIDTH-1:0] broad_id_array;`
129			`wire [3:0] fifo_wr_array;`
130			`wire [3:0] fifo_rd_array;`
131			`wire [4*BROAD_TYPE_WIDTH-1:0] breq_type_array;`
132			`wire [4*2-1:0] breq_cpu_id_array;`
133			`wire [4*BROAD_ID_WIDTH-1:0] breq_id_array;`
134			`wire [4*2-1:0] broad_cpu_id_array;`
135
136			`// Breq fifo control`
137			`//================================`
138			`mesi_isc_breq_fifos_cntl #(MBUS_CMD_WIDTH,`
139			`ADDR_WIDTH,`
140			`BROAD_TYPE_WIDTH,`
141			`BROAD_ID_WIDTH)`
142			`mesi_isc_breq_fifos_cntl`
143			`(`
144			`// Inputs`
145			`.clk (clk),`
146			`.rst (rst),`
147			`.mbus_cmd_array_i (mbus_cmd_array_i [4*MBUS_CMD_WIDTH-1 :0]),`
148			`.fifo_status_empty_array_i (fifo_status_empty_array [3:0]),`
149			`.fifo_status_full_array_i (fifo_status_full_array [3:0]),`
150			`.broad_fifo_status_full_i (broad_fifo_status_full_i),`
151			`.broad_addr_array_i (broad_addr_array [4*ADDR_WIDTH-1 :0]),`
152			`.broad_type_array_i (broad_type_array [4*BROAD_TYPE_WIDTH-1 :0]),`
153			`.broad_id_array_i (broad_id_array [4*BROAD_ID_WIDTH-1 :0]),`
154			`// Outputs`
155			`.mbus_ack_array_o (mbus_ack_array_o [3:0]),`
156			`.fifo_wr_array_o (fifo_wr_array [3:0]),`
157			`.fifo_rd_array_o (fifo_rd_array [3:0]),`
158			`.broad_fifo_wr_o (broad_fifo_wr_o),`
159			`.broad_addr_o (broad_addr_o [ADDR_WIDTH-1 :0]),`
160			`.broad_type_o (broad_type_o [BROAD_TYPE_WIDTH-1 :0]),`
161			`.broad_cpu_id_o (broad_cpu_id_o [1:0]),`
162			`.broad_id_o (broad_id_o [BROAD_ID_WIDTH-1 :0]),`
163			`.breq_type_array_o (breq_type_array [4*BROAD_TYPE_WIDTH-1 :0]),`
164			`.breq_cpu_id_array_o (breq_cpu_id_array [4*2-1 :0]),`
165			`.breq_id_array_o (breq_id_array [4*BROAD_ID_WIDTH-1 :0])`
166			`);`
167
168			`// Breq fifo 3`
169			`//================================`
170			`mesi_isc_basic_fifo #(ADDR_WIDTH + // DATA_WIDTH`
171			`BROAD_TYPE_WIDTH +`
172			`2 + // BROAD_CPU_ID_WIDTH`
173			`BROAD_ID_WIDTH,`
174			`BREQ_FIFO_SIZE, // FIFO_SIZE`
175			`BREQ_FIFO_SIZE_LOG2) // FIFO_SIZE_LOG2`
176			`// \ / (\ / marks the fifo ID)`
177			`fifo_3`
178			`(`
179			`// Inputs`
180			`.clk (clk),`
181			`.rst (rst),`
182			`// \ /`
183			`.wr_i (fifo_wr_array[3]),`
184			`// \ /`
185			`.rd_i (fifo_rd_array[3]),`
186			`// \ /`
187			`.data_i ({mbus_addr_array_i[(3+1)*ADDR_WIDTH-1:`
188			`// \ /`
189			`3*ADDR_WIDTH],`
190			`// \ /`
191			`breq_type_array [(3+1)*BROAD_TYPE_WIDTH-1:`
192			`// \ /`
193			`3*BROAD_TYPE_WIDTH],`
194			`// \ /`
195			`breq_cpu_id_array[(3+1)*2-1:`
196			`// \ /`
197			`3*2],`
198			`// \ /`
199			`breq_id_array [(3+1)*BROAD_ID_WIDTH-1:`
200			`// \ /`
201			`3*BROAD_ID_WIDTH]}),`
202			`// Outputs`
203			`// // \ /`
204			`.data_o ({broad_addr_array [(3+1)*ADDR_WIDTH-1:`
205			`// \ /`
206			`3*ADDR_WIDTH],`
207			`// \ /`
208			`broad_type_array [(3+1)*BROAD_TYPE_WIDTH-1:`
209			`// \ /`
210			`3*BROAD_TYPE_WIDTH],`
211			`// \ /`
212			`broad_cpu_id_array[(3+1)*2-1:`
213			`// \ /`
214			`3*2],`
215			`// \ /`
216			`broad_id_array [(3+1)*BROAD_ID_WIDTH-1:`
217			`// \ /`
218			`3*BROAD_ID_WIDTH]}),`
219			`// \ /`
220			`.status_empty_o (fifo_status_empty_array [3]),`
221			`// \ /`
222			`.status_full_o (fifo_status_full_array [3])`
223			`);`
224
225			`// Breq fifo 2`
226			`//================================`
227			`mesi_isc_basic_fifo #(ADDR_WIDTH + // DATA_WIDTH`
228			`BROAD_TYPE_WIDTH +`
229			`2 + // BROAD_CPU_ID_WIDTH`
230			`BROAD_ID_WIDTH,`
231			`BREQ_FIFO_SIZE, // FIFO_SIZE`
232			`BREQ_FIFO_SIZE_LOG2) // FIFO_SIZE_LOG2`
233			`// \ / (\ / marks the fifo ID)`
234			`fifo_2`
235			`(`
236			`// Inputs`
237			`.clk (clk),`
238			`.rst (rst),`
239			`// \ /`
240			`.wr_i (fifo_wr_array[2]),`
241			`// \ /`
242			`.rd_i (fifo_rd_array[2]),`
243			`// \ /`
244			`.data_i ({mbus_addr_array_i[(2+1)*ADDR_WIDTH-1:`
245			`// \ /`
246			`2*ADDR_WIDTH],`
247			`// \ /`
248			`breq_type_array [(2+1)*BROAD_TYPE_WIDTH-1:`
249			`// \ /`
250			`2*BROAD_TYPE_WIDTH],`
251			`// \ /`
252			`breq_cpu_id_array[(2+1)*2-1:`
253			`// \ /`
254			`2*2],`
255			`// \ /`
256			`breq_id_array [(2+1)*BROAD_ID_WIDTH-1:`
257			`// \ /`
258			`2*BROAD_ID_WIDTH]}),`
259			`// Outputs`
260			`// // \ /`
261			`.data_o ({broad_addr_array [(2+1)*ADDR_WIDTH-1:`
262			`// \ /`
263			`2*ADDR_WIDTH],`
264			`// \ /`
265			`broad_type_array [(2+1)*BROAD_TYPE_WIDTH-1:`
266			`// \ /`
267			`2*BROAD_TYPE_WIDTH],`
268			`// \ /`
269			`broad_cpu_id_array[(2+1)*2-1:`
270			`// \ /`
271			`2*2],`
272			`// \ /`
273			`broad_id_array [(2+1)*BROAD_ID_WIDTH-1:`
274			`// \ /`
275			`2*BROAD_ID_WIDTH]}),`
276			`// \ /`
277			`.status_empty_o (fifo_status_empty_array [2]),`
278			`// \ /`
279			`.status_full_o (fifo_status_full_array [2])`
280			`);`
281
282			`// Breq fifo 1`
283			`//================================`
284			`mesi_isc_basic_fifo #(ADDR_WIDTH + // DATA_WIDTH`
285			`BROAD_TYPE_WIDTH +`
286			`2 + // BROAD_CPU_ID_WIDTH`
287			`BROAD_ID_WIDTH,`
288			`BREQ_FIFO_SIZE, // FIFO_SIZE`
289			`BREQ_FIFO_SIZE_LOG2) // FIFO_SIZE_LOG2`
290			`// \ / (\ / marks the fifo ID)`
291			`fifo_1`
292			`(`
293			`// Inputs`
294			`.clk (clk),`
295			`.rst (rst),`
296			`// \ /`
297			`.wr_i (fifo_wr_array[1]),`
298			`// \ /`
299			`.rd_i (fifo_rd_array[1]),`
300			`// \ /`
301			`.data_i ({mbus_addr_array_i[(1+1)*ADDR_WIDTH-1:`
302			`// \ /`
303			`1*ADDR_WIDTH],`
304			`// \ /`
305			`breq_type_array [(1+1)*BROAD_TYPE_WIDTH-1:`
306			`// \ /`
307			`1*BROAD_TYPE_WIDTH],`
308			`// \ /`
309			`breq_cpu_id_array[(1+1)*2-1:`
310			`// \ /`
311			`1*2],`
312			`// \ /`
313			`breq_id_array [(1+1)*BROAD_ID_WIDTH-1:`
314			`// \ /`
315			`1*BROAD_ID_WIDTH]}),`
316			`// Outputs`
317			`// // \ /`
318			`.data_o ({broad_addr_array [(1+1)*ADDR_WIDTH-1:`
319			`// \ /`
320			`1*ADDR_WIDTH],`
321			`// \ /`
322			`broad_type_array [(1+1)*BROAD_TYPE_WIDTH-1:`
323			`// \ /`
324			`1*BROAD_TYPE_WIDTH],`
325			`// \ /`
326			`broad_cpu_id_array[(1+1)*2-1:`
327			`// \ /`
328			`1*2],`
329			`// \ /`
330			`broad_id_array [(1+1)*BROAD_ID_WIDTH-1:`
331			`// \ /`
332			`1*BROAD_ID_WIDTH]}),`
333			`// \ /`
334			`.status_empty_o (fifo_status_empty_array [1]),`
335			`// \ /`
336			`.status_full_o (fifo_status_full_array [1])`
337			`);`
338
339			`// Breq fifo 0`
340			`//================================`
341			`mesi_isc_basic_fifo #(ADDR_WIDTH + // DATA_WIDTH`
342			`BROAD_TYPE_WIDTH +`
343			`2 + // BROAD_CPU_ID_WIDTH`
344			`BROAD_ID_WIDTH,`
345			`BREQ_FIFO_SIZE, // FIFO_SIZE`
346			`BREQ_FIFO_SIZE_LOG2) // FIFO_SIZE_LOG2`
347			`// \ / (\ / marks the fifo ID)`
348			`fifo_0`
349			`(`
350			`// Inputs`
351			`.clk (clk),`
352			`.rst (rst),`
353			`// \ /`
354			`.wr_i (fifo_wr_array[0]),`
355			`// \ /`
356			`.rd_i (fifo_rd_array[0]),`
357			`// \ /`
358			`.data_i ({mbus_addr_array_i[(0+1)*ADDR_WIDTH-1:`
359			`// \ /`
360			`0*ADDR_WIDTH],`
361			`// \ /`
362			`breq_type_array [(0+1)*BROAD_TYPE_WIDTH-1:`
363			`// \ /`
364			`0*BROAD_TYPE_WIDTH],`
365			`// \ /`
366			`breq_cpu_id_array[(0+1)*2-1:`
367			`// \ /`
368			`0*2],`
369			`// \ /`
370			`breq_id_array [(0+1)*BROAD_ID_WIDTH-1:`
371			`// \ /`
372			`0*BROAD_ID_WIDTH]}),`
373			`// Outputs`
374			`// // \ /`
375			`.data_o ({broad_addr_array [(0+1)*ADDR_WIDTH-1:`
376			`// \ /`
377			`0*ADDR_WIDTH],`
378			`// \ /`
379			`broad_type_array [(0+1)*BROAD_TYPE_WIDTH-1:`
380			`// \ /`
381			`0*BROAD_TYPE_WIDTH],`
382			`// \ /`
383			`broad_cpu_id_array[(0+1)*2-1:`
384			`// \ /`
385			`0*2],`
386			`// \ /`
387			`broad_id_array [(0+1)*BROAD_ID_WIDTH-1:`
388			`// \ /`
389			`0*BROAD_ID_WIDTH]}),`
390			`// \ /`
391			`.status_empty_o (fifo_status_empty_array [0]),`
392			`// \ /`
393			`.status_full_o (fifo_status_full_array [0])`
394			`);`
395
396			`endmodule`