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[/] [mesi_isc/] [trunk/] [src/] [tb/] [mesi_isc_tb_sanity_check.v] - Blame information for rev 5

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1 2 yaira 
//////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  MESI_ISC Project                                            ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Yair Amitay       yair.amitay@yahoo.com               ////
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////                          www.linkedin.com/in/yairamitay      ////
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////                                                              ////
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////  Description                                                 ////
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////  mesi_isc_tb                                                 ////
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////  -------------------                                         ////
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////  Project test bench.                                         ////
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////  Check coherency rules 1,2, and 3.                           ////
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////  Check fifos overflow and underflow.                         ////
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////                                                              ////
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////  To Do:                                                      ////
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////   -                                                          ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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// Sanity checks
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//================================
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// Sanity Check 1 - coherency rules
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//================================
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//
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// Rule | time  | CPU ID  | Memory | Address | Data | Condition   |
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//      |       |         | Event  |         |      |             |
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// -----|-------|---------|--------|---------|------|-------------|
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//      |  x    |   1     |  WR    |  A1     |  D1  |
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//   1  |-------|---------|--------|---------|------|
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//      |  x+1  |   1     |  RD    |  A1     |  D1  |
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// -----|-------|---------|--------|---------|------|
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//      |  x    |   1     |  WR    |  A1     |  D1  |
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//   2  |-------|---------|--------|---------|------|
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//      |  x+1  |   2     |  RD    |  A1     |  D1  |
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// -----|-------|---------|--------|---------|------|
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//      |  x    |   1     |  WR    |  A1     |  D1  |
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//      |-------|---------|--------|---------|------|
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//      |  x+1  |   2     |  WD    |  A1     |  D2  |
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//   3  |-------|---------|--------|---------|------|
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//      |  y    |   3     |  RD    |  A1     |  D2  |
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//      |-------|---------|--------|---------|------|--------------|
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//      |  y+1  |   3     |  RD    |  A1     |  D1  |  Not allowed |
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// -----|-------|---------|--------|---------|------|--------------|
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//
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// For each read from the memory, check that the read data contains the most
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// update written data. The check is done separately for each CPU written data.
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// This check covers the three rules for coherency system.
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// task sanity_check_rule1
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task sanity_check_rule1_rule2;
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input [3:0]              cpu_id;
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input [ADDR_WIDTH-1:0]   mbus_addr;
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input [DATA_WIDTH-1:0]   mbus_wr_data;
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reg   [DATA_WIDTH-1:0]   cur_mem_data;
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begin
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`ifdef messages
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  $display("Message: check err 7. time:%d", $time);
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`endif
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  cur_mem_data = mem[mbus_addr];
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  if (cur_mem_data[(3+1)*8-1 : 3*8] > mbus_wr_data[(3+1)*8-1 : 3*8] |
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      cur_mem_data[(2+1)*8-1 : 2*8] > mbus_wr_data[(2+1)*8-1 : 2*8] |
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      cur_mem_data[(1+1)*8-1 : 1*8] > mbus_wr_data[(1+1)*8-1 : 1*8] |
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      cur_mem_data[(0+1)*8-1 : 0*8] > mbus_wr_data[(0+1)*8-1 : 0*8])
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  begin
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    $display("ERROR 7. The current memory data is bigger then the written data\n");
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    $display("  CPU: %h, Cur data: %h, Written data: %h, Address: %h, time:%d\n",
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             cpu_id,
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             cur_mem_data,
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             mbus_wr_data,
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             mbus_addr,
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             $time);
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    @(negedge clk) $finish();
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  end
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end
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endtask
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// Sanity Check 2- cache states
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//================================
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// Checks that, at any time, there are not 2 cache lines or more, that contains
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// the same memory address, with stats M or state E.
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always @(posedge clk or posedge rst)
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  for (k=0; k < 4; k = k + 1)
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    if (mbus_ack[k]) sanity_check_cache_status(mbus_addr_array[k]);
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// task sanity_check_cache_status;
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task sanity_check_cache_status;
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input [ADDR_WIDTH-1:0]   mbus_addr;
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reg [1:0]                num_of_lines_in_m_e_state;
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begin
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`ifdef messages
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     $display("Message: check err 6. time:%d", $time);
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`endif
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  num_of_lines_in_m_e_state = 0;
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  //               \ /
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  if(mesi_isc_tb_cpu3.cache_state[mbus_addr] == `MESI_ISC_TB_CPU_MESI_E |
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  //               \ /
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     mesi_isc_tb_cpu3.cache_state[mbus_addr] == `MESI_ISC_TB_CPU_MESI_M)
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     num_of_lines_in_m_e_state = num_of_lines_in_m_e_state + 1;
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  if(mesi_isc_tb_cpu2.cache_state[mbus_addr] == `MESI_ISC_TB_CPU_MESI_E |
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  //               \ /
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     mesi_isc_tb_cpu2.cache_state[mbus_addr] == `MESI_ISC_TB_CPU_MESI_M)
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     num_of_lines_in_m_e_state = num_of_lines_in_m_e_state + 1;
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  if(mesi_isc_tb_cpu1.cache_state[mbus_addr] == `MESI_ISC_TB_CPU_MESI_E |
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  //               \ /
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     mesi_isc_tb_cpu1.cache_state[mbus_addr] == `MESI_ISC_TB_CPU_MESI_M)
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     num_of_lines_in_m_e_state = num_of_lines_in_m_e_state + 1;
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  if(mesi_isc_tb_cpu0.cache_state[mbus_addr] == `MESI_ISC_TB_CPU_MESI_E |
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  //               \ /
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     mesi_isc_tb_cpu0.cache_state[mbus_addr] == `MESI_ISC_TB_CPU_MESI_M)
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     num_of_lines_in_m_e_state = num_of_lines_in_m_e_state + 1;
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  if (num_of_lines_in_m_e_state > 1)
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  begin
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     $display("Error 6. %d of cache lines are in M or E state. time:%d\n",
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                                                 num_of_lines_in_m_e_state,
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                                                 $time);
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     @(negedge clk) $finish;
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  end
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end
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endtask
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// Error state
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//================================
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`ifdef mesi_isc_debug
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always @(mesi_isc.mesi_isc_breq_fifos.fifo_3.dbg_fifo_overflow or
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         mesi_isc.mesi_isc_breq_fifos.fifo_3.dbg_fifo_underflow or
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         mesi_isc.mesi_isc_breq_fifos.fifo_2.dbg_fifo_overflow or
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         mesi_isc.mesi_isc_breq_fifos.fifo_2.dbg_fifo_underflow or
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         mesi_isc.mesi_isc_breq_fifos.fifo_1.dbg_fifo_overflow or
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         mesi_isc.mesi_isc_breq_fifos.fifo_1.dbg_fifo_underflow or
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         mesi_isc.mesi_isc_breq_fifos.fifo_0.dbg_fifo_overflow or
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         mesi_isc.mesi_isc_breq_fifos.fifo_0.dbg_fifo_underflow or
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         mesi_isc.mesi_isc_broad.broad_fifo.dbg_fifo_overflow or
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         mesi_isc.mesi_isc_broad.broad_fifo.dbg_fifo_underflow)
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if (mesi_isc.mesi_isc_breq_fifos.fifo_3.dbg_fifo_overflow  |
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    mesi_isc.mesi_isc_breq_fifos.fifo_3.dbg_fifo_underflow |
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    mesi_isc.mesi_isc_breq_fifos.fifo_2.dbg_fifo_overflow  |
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    mesi_isc.mesi_isc_breq_fifos.fifo_2.dbg_fifo_underflow |
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    mesi_isc.mesi_isc_breq_fifos.fifo_1.dbg_fifo_overflow  |
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    mesi_isc.mesi_isc_breq_fifos.fifo_1.dbg_fifo_underflow |
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    mesi_isc.mesi_isc_breq_fifos.fifo_0.dbg_fifo_overflow  |
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    mesi_isc.mesi_isc_breq_fifos.fifo_0.dbg_fifo_underflow |
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    mesi_isc.mesi_isc_broad.broad_fifo.dbg_fifo_overflow   |
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    mesi_isc.mesi_isc_broad.broad_fifo.dbg_fifo_underflow)
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  begin
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    $display("ERROR 8. Fifo overflow or underflow\n");
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    $display("mesi_isc.mesi_isc_breq_fifos.fifo_3.dbg_fifo_overflow = %h,              mesi_isc.mesi_isc_breq_fifos.fifo_3.dbg_fifo_underflow = %h,    mesi_isc.mesi_isc_breq_fifos.fifo_2.dbg_fifo_overflow = %h,    mesi_isc.mesi_isc_breq_fifos.fifo_2.dbg_fifo_underflow = %h,    mesi_isc.mesi_isc_breq_fifos.fifo_1.dbg_fifo_overflow = %h,    mesi_isc.mesi_isc_breq_fifos.fifo_1.dbg_fifo_underflow = %h,    mesi_isc.mesi_isc_breq_fifos.fifo_0.dbg_fifo_overflow = %h,    mesi_isc.mesi_isc_breq_fifos.fifo_0.dbg_fifo_underflow = %h,    mesi_isc.mesi_isc_broad.broad_fifo.dbg_fifo_overflow = %h,    mesi_isc.mesi_isc_broad.broad_fifo.dbg_fifo_underflow = %h",    mesi_isc.mesi_isc_breq_fifos.fifo_3.dbg_fifo_overflow,
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    mesi_isc.mesi_isc_breq_fifos.fifo_3.dbg_fifo_underflow,
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    mesi_isc.mesi_isc_breq_fifos.fifo_2.dbg_fifo_overflow,
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    mesi_isc.mesi_isc_breq_fifos.fifo_2.dbg_fifo_underflow,
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    mesi_isc.mesi_isc_breq_fifos.fifo_1.dbg_fifo_overflow,
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    mesi_isc.mesi_isc_breq_fifos.fifo_1.dbg_fifo_underflow,
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    mesi_isc.mesi_isc_breq_fifos.fifo_0.dbg_fifo_overflow,
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    mesi_isc.mesi_isc_breq_fifos.fifo_0.dbg_fifo_underflow,
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    mesi_isc.mesi_isc_broad.broad_fifo.dbg_fifo_overflow,
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    mesi_isc.mesi_isc_broad.broad_fifo.dbg_fifo_underflow);
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    $finish();
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  end
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`endif
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