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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1356256126919 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "PowerPlay Power Analyzer Quartus II 32-bit " "Running Quartus II 32-bit PowerPlay Power Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition " "Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1356256126919 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 23 11:48:46 2012 " "Processing started: Sun Dec 23 11:48:46 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1356256126919 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1356256126919 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_pow --read_settings_files=on --write_settings_files=off mesi_isc -c mesi_isc " "Command: quartus_pow --read_settings_files=on --write_settings_files=off mesi_isc -c mesi_isc" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1356256126920 ""}
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{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0 -1 1356256127452 ""}
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{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0 -1 1356256127453 ""}
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{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "mesi_isc.sdc " "Synopsys Design Constraints File file not found: 'mesi_isc.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "" 0 -1 1356256128244 ""}
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{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk " "Node: clk was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1 1356256128250 "|mesi_isc|clk"}
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{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "" 0 -1 1356256128251 ""}
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{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "" 0 -1 1356256128259 ""}
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{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "" 0 -1 1356256128259 ""}
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{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "" 0 -1 1356256128284 ""}
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{ "Warning" "WPUTIL_PUTIL_NO_CLK_DOMAINS_FOUND" "" "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" { } { } 0 222013 "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" 0 0 "" 0 -1 1356256128285 ""}
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{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "" 0 -1 1356256128307 ""}
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{ "Info" "IPATFAM_USING_ADVANCED_IO_POWER" "" "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" { } { } 0 218000 "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" 0 0 "" 0 -1 1356256128742 ""}
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{ "Warning" "WPAN_PAN_NO_THERMAL_MODEL_SELECTED" "" "No board thermal model was selected. Analyzing without board thermal modeling." { } { } 0 215044 "No board thermal model was selected. Analyzing without board thermal modeling." 0 0 "" 0 -1 1356256128769 ""}
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{ "Info" "IPAN_AVG_TOGGLE_RATE_PER_DESIGN" "0.000 millions of transitions / sec " "Average toggle rate for this design is 0.000 millions of transitions / sec" { } { } 0 215049 "Average toggle rate for this design is %1!s!" 0 0 "" 0 -1 1356256136718 ""}
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{ "Info" "IPAN_PAN_TOTAL_POWER_ESTIMATION" "178.89 mW " "Total thermal power estimate for the design is 178.89 mW" { } { { "/opt/12.0sp2/quartus/linux/Report_Window_01.qrpt" "" { Report "/opt/12.0sp2/quartus/linux/Report_Window_01.qrpt" "Compiler" "" "" "" "" { } "PowerPlay Power Analyzer Summary" } } } 0 215031 "Total thermal power estimate for the design is %1!s!" 0 0 "" 0 -1 1356256136728 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "PowerPlay Power Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit PowerPlay Power Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "428 " "Peak virtual memory: 428 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1356256136835 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 23 11:48:56 2012 " "Processing ended: Sun Dec 23 11:48:56 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1356256136835 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1356256136835 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Total CPU time (on all processors): 00:00:10" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1356256136835 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1356256136835 ""}
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