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[/] [microprocessor/] [trunk/] [bench/] [VHDL/] [Adress.vhd] - Blame information for rev 4

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-------------------------------------------------------------------------------
-- Adress Unit 
-- 
-- 
-------------------------------------------------------------------------------
 
library IEEE;
 
use IEEE.STD_LOGIC_1164.all;
 
entity adress_data is
        port(
        ctrl_adress : in std_logic_vector (1 downto 0);
        adress_8 :    in std_logic_vector (7 downto 0);
        adress_16  :  out std_logic_vector (15 downto 0)
             );
end adress_data ;
 
architecture archi_adress_data of adress_data is
signal s_adress_16 : std_logic_vector (15 downto 0);
 
begin
        process (ctrl_adress,adress_8)
        begin
        case ctrl_adress is
                when "10"=>
                s_adress_16(7 downto 0)<= adress_8 ;
                when "01"=>
                s_adress_16(15 downto 8)<= adress_8 ;
                when "11"=>
                adress_16 <= s_adress_16 ;
                when others =>
        end case ;
        end process ;
 
end archi_adress_data ;
 
--------------------------
--------------------------
 
library IEEE;
 
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
entity pc_adress is
        port (
             pc_inc :           in std_logic ;
             reset       :              in std_logic ;
                 adress  :          out std_logic_vector (15 downto 0);
                 adress_16_in  :    in std_logic_vector (15 downto 0);
                 ctrl_adress_pc  :      in std_logic ;
                 ctrl_adress_out :      in std_logic ;
                 ret_adress_out :   out std_logic_vector (15 downto 0);
                 lock_pc :                      in std_logic
                 );
 
end pc_adress ;
 
architecture archi_pc_adress  of pc_adress  is
begin
 
process (reset,pc_inc,ctrl_adress_pc,adress_16_in,ctrl_adress_out)
variable pc : std_logic_vector (15 downto 0);
begin
 
if (ctrl_adress_pc='1')then
pc := adress_16_in  ;
else
   if reset = '1' then
     pc    :="0000000000000000" ;
     adress<="0000000000000000" ;
   else
    if (pc_inc'event and pc_inc='1')then
          if pc<65535 then
        if (lock_pc='0')then
                  pc := pc + 1 ;
        end if ;
          else
        pc:="0000000000000000" ;
      end if;
    end if ;
    end if ;
end if ;
 
 
if ctrl_adress_out='1' then
  adress <= pc ;
  ret_adress_out <= pc ;
end if ;
 
end process ;
 
end archi_pc_adress ;

Line No.	Rev	Author	Line
1	2	yacinenet	`-------------------------------------------------------------------------------`
2			`-- Adress Unit`
3			`--`
4			`--`
5			`-------------------------------------------------------------------------------`
6
7			`library IEEE;`
8
9			`use IEEE.STD_LOGIC_1164.all;`
10
11			`entity adress_data is`
12			`port(`
13			`ctrl_adress : in std_logic_vector (1 downto 0);`
14			`adress_8 : in std_logic_vector (7 downto 0);`
15			`adress_16 : out std_logic_vector (15 downto 0)`
16			`);`
17			`end adress_data ;`
18
19			`architecture archi_adress_data of adress_data is`
20			`signal s_adress_16 : std_logic_vector (15 downto 0);`
21
22			`begin`
23			`process (ctrl_adress,adress_8)`
24			`begin`
25			`case ctrl_adress is`
26			`when "10"=>`
27			`s_adress_16(7 downto 0)<= adress_8 ;`
28			`when "01"=>`
29			`s_adress_16(15 downto 8)<= adress_8 ;`
30			`when "11"=>`
31			`adress_16 <= s_adress_16 ;`
32			`when others =>`
33			`end case ;`
34			`end process ;`
35
36			`end archi_adress_data ;`
37
38			`--------------------------`
39			`--------------------------`
40
41			`library IEEE;`
42
43			`use IEEE.STD_LOGIC_1164.all;`
44			`use IEEE.STD_LOGIC_UNSIGNED.all;`
45
46			`entity pc_adress is`
47			`port (`
48			`pc_inc : in std_logic ;`
49			`reset : in std_logic ;`
50			`adress : out std_logic_vector (15 downto 0);`
51			`adress_16_in : in std_logic_vector (15 downto 0);`
52			`ctrl_adress_pc : in std_logic ;`
53			`ctrl_adress_out : in std_logic ;`
54			`ret_adress_out : out std_logic_vector (15 downto 0);`
55			`lock_pc : in std_logic`
56			`);`
57
58			`end pc_adress ;`
59
60			`architecture archi_pc_adress of pc_adress is`
61			`begin`
62
63			`process (reset,pc_inc,ctrl_adress_pc,adress_16_in,ctrl_adress_out)`
64			`variable pc : std_logic_vector (15 downto 0);`
65			`begin`
66
67			`if (ctrl_adress_pc='1')then`
68			`pc := adress_16_in ;`
69			`else`
70			`if reset = '1' then`
71			`pc :="0000000000000000" ;`
72			`adress<="0000000000000000" ;`
73			`else`
74			`if (pc_inc'event and pc_inc='1')then`
75			`if pc<65535 then`
76			`if (lock_pc='0')then`
77			`pc := pc + 1 ;`
78			`end if ;`
79			`else`
80			`pc:="0000000000000000" ;`
81			`end if;`
82			`end if ;`
83			`end if ;`
84			`end if ;`
85
86
87			`if ctrl_adress_out='1' then`
88			`adress <= pc ;`
89			`ret_adress_out <= pc ;`
90			`end if ;`
91
92			`end process ;`
93
94			`end archi_pc_adress ;`

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[/] [microprocessor/] [trunk/] [bench/] [VHDL/] [Adress.vhd] - Blame information for rev 4