URL https://opencores.org/ocsvn/microprocessor/microprocessor/trunk

Subversion Repositories microprocessor

[/] [microprocessor/] [trunk/] [bench/] [VHDL/] [FSM.vhd] - Blame information for rev 4

Details | Compare with Previous | View Log


-------------------------------------------------------------------------------
-- FSM (Finite State Machine) 
-- 
-- 
-------------------------------------------------------------------------------
 
library IEEE;
 
use IEEE.STD_LOGIC_1164.all;
 
entity FSM is
        port (
        clk :              in std_logic ;
        d_in_FSM :         in std_logic_vector (7 downto 0);
        reset :            in std_logic ;
        compar2FSM :       in std_logic ;
    wo :               out std_logic ;
    oe :               out std_logic ;
        pc_inc :           out std_logic ;
        data2compar :      out std_logic_vector (7 downto 0);
        selec_fonc_compar: out std_logic_vector (1 downto 0);
        selec_reg_resu1 :  out std_logic_vector (2 downto 0);
        adress_in :        in std_logic_vector (15 downto 0);
        ctrl_alu :         out std_logic_vector (3 downto 0);
        ctrl_adress :      out std_logic_vector (1 downto 0);
        adress_8 :         out std_logic_vector (7 downto 0);
        c_data_out :       out std_logic ;
        c_adress_out :     out std_logic ;
        c_flag_out :       out std_logic ;
        c_inALU :              out std_logic ;
        resu_compar :      out std_logic ;
        reg_resu2 :        in std_logic_vector (7 downto 0);
        c_in_compar :      out std_logic ;
        c_adress2_out :    out std_logic ;
        reg_flag2FSM :     in std_logic_vector (4 downto 0);
        p2fsm :            in std_logic ;
        fsm2p :            out std_logic ;
        lock_fsm2pc :      out std_logic
              );
end FSM ;
 
architecture archi_FSM  of FSM  is
 
type stat_type is (s0,s01,s1,s2,s21,s22,s23,s24,s25,s26,s27,s28,
s29,s3,s31,s32,s33,s34,s35,s36,s37,s4,s41,s42,s43,s44,s45,s46,
s5,s6,s7,s_ck1,s_ck2,s_ck3,s_ck4,s_ck5,s_ck6,s_ck7,s_ck8,s_ck9,
s_ck10,s_ck11,s8,s81,s9,s91,s92,s93,s94,s95,s96,s97,s98,s99,s10,s10a,
s10b,s10c,s10d,s10e,s10f,s10g,s10h);
 
 
signal tempo  :       std_logic_vector (7 downto 0);
signal tempo1  :      std_logic_vector (3 downto 0);
signal temp_adress :  std_logic_vector (15 downto 0);
signal statu :        std_logic ;
signal var_flag :     std_logic ;
signal lock_fsm :     std_logic ;
signal state  :       stat_type ;
 
begin
 
process (reset,clk,d_in_FSM)
begin
  if (reset='1') then
        c_flag_out<='0';
        pc_inc<='0';
        selec_reg_resu1<="000";
        ctrl_alu<="0000";
        var_flag<='0';
        ctrl_adress<="00";
        wo <='0';
        oe <='1';
        adress_8<="00000000";
        statu<='0';
        c_inALU<='0';
        c_adress_out<='0';
        selec_fonc_compar<="00";
        c_in_compar<='0';
        fsm2p<='0';
        data2compar<="00000000";
        temp_adress<="0000000000000000";
        tempo<="00000000";
        c_data_out<='0';
        resu_compar<='0';
        c_adress2_out<='1';
        lock_fsm<='1';
        tempo1<="0000";
        lock_fsm2pc<='0';
        state<=s0;
  else
    if (clk'event and clk='1')then
          if (p2fsm='0')then
            wo <='0';
            oe <='1';
                lock_fsm2pc<='0';
          else
            if(p2fsm='1')then
                  if (lock_fsm='1') then
                oe <='0';
                    fsm2p<='1';
                    lock_fsm2pc<='1';
                  end if;
            end if;
          end if;
 
          tempo<=d_in_FSM ;
        case state is
        when s0 =>
        pc_inc<='0';
          if (lock_fsm='1') then
                 pc_inc<='1';
                 statu<= '0' ;
                 state<=s01;
          end if ;
        when s01 =>
        pc_inc<='0';
        state<=s1;
        when s1=>
          if statu = '0' then
                 case tempo is
                     when "00000001"=>     --------------------- begin of ALU
                     ctrl_alu<="0001";
                                 state<=s3;
                     when "00000010"=>
                     ctrl_alu<="0010";
                                 state<=s3;
                     when "00000011"=>
                     ctrl_alu<="0011";
                                 state<=s3;
                     when "00000100"=>
                                 tempo1<="0100";
                                 state<=s2;
                     when "00000101"=>
                                 tempo1<="0101";
                                 state<=s2;
                     when "00000110"=>
                                 tempo1<="0110";
                                 state<=s2;
                     when "00000111"=>
                                 tempo1<="0111";
                                 state<=s2;
                     when "00001000"=>
                                 tempo1<="1000";
                                 state<=s2;
                     when "00001001"=>
                     ctrl_alu<="1001";
                                 state<=s3;
                     when "00001010"=>
                     ctrl_alu<="1010" ;
                                 state<=s3;
                                 when "00001011"=>
                     ctrl_alu<="1011";
                                 state<=s3;
                                 when "00001100"=>
                     ctrl_alu<="1100" ;
                                 state<=s3;           ----------------------- end of ALU  
 
                                 when "00010000"=>        -------- acces to adress  
                                 state<=s4;
                                 when "00100000"=>        -------- return to address PC 
                     state<=s9;
 
                                 when "00110000"=>        -- comparison >,<,=
                                 state<=s5;
                                 when "01000000"=>
                     state<=s6;
                                 when "01010000"=>
                     state<=s7;
 
                                 when "01100000"=>        -- Release of the result
                                 c_data_out<='1';
                     state<=s0;
 
                                 when "01110000"=>        -- load flag register
                                 c_flag_out<='1';
                     pc_inc<='1';
                                 state<=s0;
 
                                 when "10000000"=>        -- shift/rot
                     selec_reg_resu1<="001";
                                 pc_inc<='1';
                                 state<=s0;
                                 when "10010000"=>
                     selec_reg_resu1<="010";
                                 pc_inc<='1';
                                 state<=s0;
                                 when "10100000"=>
                     selec_reg_resu1<="011";
                                 pc_inc<='1';
                                 state<=s0;
                                 when "10110000"=>
                     selec_reg_resu1<="100";
                                 pc_inc<='1';
                                 state<=s0;
                                 when "11000000"=>
                     selec_reg_resu1<="101";
                                 pc_inc<='1';
                                 state<=s0;
                                 when "11010000"=>
                     selec_reg_resu1<="110";
                                 pc_inc<='1';
                                 state<=s0;
 
                                 when "11110000"=>        --  whrite
                                 state<=s8;
 
                                 when "10000001"=>                 -- if  zero
                                 var_flag<=reg_flag2FSM(0);
                                 state<=s10;
 
                                 when "11110010"=>                 -- if  parity
                                 var_flag<=reg_flag2FSM(1);
                                 state<=s10;
 
                                 when "11110011"=>                 -- if  'comparison'
                                 var_flag<=reg_flag2FSM(4);
                             state<=s10;
 
                                 when "11110100"=>                 -- if  cary
                                 var_flag<=reg_flag2FSM(2);
                                 state<=s10;
 
                                 when "11110101"=>                 -- if  overflow
                                 var_flag<=reg_flag2FSM(3);
                                 state<=s10;
 
                                 when others =>
 
                 end case ;
           end if ;
 
         when s2=>        -----  opcode a ,b =
         lock_fsm<='0';
         statu<= '1' ;
         c_inALU<='1';
         pc_inc<='1';
         state<=s21;
         when s21=>
         pc_inc<='0';
         state<=s22;
         when s22 =>
         ctrl_alu <= tempo1 ;
         state<=s23;
         when s23=>   --- 1st clk
         state<=s24;
     when s24=>   --- clk
         state<=s25;
         when s25=>       --- clk
         state<=s26;
         when s26=>       --- clk
         state<=s27;
         when s27=>       --- clk
         state<=s28;
     when s28=>   --- clk
         selec_reg_resu1<= "111";       -- record the result in the register
         state<=s29;
         when s29=>
         selec_reg_resu1<= "000";
         pc_inc<='1';
         c_inALU<='0';
         lock_fsm<='1';
         ctrl_alu <= "0000" ;
         state<=s0;
 
         when s3=>              ------- opcode a =
         lock_fsm<='0';
         statu<= '1' ;
         c_inALU<='1';
         pc_inc<='1';
         state<=s31;
         when s31=>
         pc_inc<='0';
         state<=s32;
         when s32 =>    --- 1stclk                       
         state<=s33;
         when s33 =>    ---  clk                         
         state<=s34;
         when s34 =>    ---  clk
         state<=s35;
         when s35=>             ---  clk
         state<=s36;
         when s36 =>    ---  clk                         
         selec_reg_resu1<= "111";         -- record the result in the register
         state<=s37;
         when s37 =>
         selec_reg_resu1<= "000";
         pc_inc<='1';
         c_inALU<='0';
         lock_fsm<='1';
         ctrl_alu <= "0000" ;
         state<=s0;
 
         when s4=>
         lock_fsm<='0';
         temp_adress<=adress_in ;
         pc_inc<='1';
         state<=s41;
         when s41=>
         pc_inc<='0';
         adress_8<=tempo ;
         ctrl_adress<="01" ;
         state<=s42;
         when s42=>
         pc_inc<='1';
         state<=s43;
         when s43 =>
         pc_inc<='0';
         adress_8<=tempo ;
         ctrl_adress<="10" ;
         state<=s44;
         when s44 =>
         ctrl_adress<="11" ;
         state<=s45;
         when s45=>
         ctrl_adress<="00" ;
         c_adress_out <= '1';
         state<=s46;
         when s46=>
         c_adress_out <= '0';
         lock_fsm<='1';
         state<=s0;
 
         when s5=>               --- comparison  <
         selec_reg_resu1<= "000";
         data2compar<=reg_resu2 ;
         selec_fonc_compar<="01" ;
         pc_inc<='1';
         state<=s_ck1;
 
         when s6=>               --- comparison          >
         selec_reg_resu1<= "000";
         data2compar<=reg_resu2 ;
     selec_fonc_compar<="10" ;
     pc_inc<='1';
         state<=s_ck1;
 
         when s7=>               --- comparison          =
         selec_reg_resu1<= "000";
         data2compar<=reg_resu2 ;
         selec_fonc_compar<="11" ;
         pc_inc<='1';
         state<=s_ck1;
 
         when s_ck1 =>
         lock_fsm<='0';
         pc_inc<='0';
         c_in_compar<='1';
         statu<= '1' ;
         state<=s_ck2;
         when s_ck2=>    -- 1st clk 
         state<=s_ck3;
         when s_ck3=>    --  clk        
         state<=s_ck4;
         when s_ck4 =>   --  clk        
         state<=s_ck5;
         when s_ck5=>    --  clk        
         state<=s_ck6;
         when s_ck6=>    --  clk        
         state<=s_ck7;
         when s_ck7=>    --  clk        
         state<=s_ck8;
         when s_ck8=>    --  clk 
         state<=s_ck9;
         when s_ck9=>    --  clk        
         state<=s_ck10;
         when s_ck10=>   --  clk 
         state<=s_ck11;
         when s_ck11=>   --  clk 
         resu_compar <= compar2FSM ;
         pc_inc<='1';
         c_in_compar<='0';
         lock_fsm<='1';
         state<=s0;
 
         when s8=>               -- whrite
         pc_inc<='1';
         wo <='1';
         oe <='1';
         c_data_out<='1';
         state<=s81;
         when s81=>
         pc_inc<='0';
         c_data_out<='0';
         state<=s0;
 
         when s9=>              -- return to adress      
         lock_fsm<='0';
         c_adress2_out<='0' ;
         pc_inc<='0';
         adress_8<=temp_adress(7 downto 0) ;
         ctrl_adress<="10" ;
         state<=s91;
         when s91=>
         adress_8<=temp_adress(15 downto 8) ;
         ctrl_adress<="01" ;
         state<=s92;
         when s92=>
         ctrl_adress<="11" ;
         c_adress_out <= '1';
         state<=s93;
         when s93 =>
         c_adress_out <= '0';
         state<=s94;
         when s94 =>
         pc_inc<='1';
         ctrl_adress<="00" ;
         state<=s95;
         when s95 =>
     pc_inc<='0';
         state<=s96;
         when s96 =>
         pc_inc<='1';
         state<=s97;
         when s97 =>
         pc_inc<='0';
         state<=s98 ;
         when s98 =>
         pc_inc<='1';
         state<=s99 ;
         when s99 =>
         pc_inc<='0';
         c_adress2_out<='1' ;
         lock_fsm<='1';
         state<=s0;
 
         when s10 =>    -- is yes ;; 
         if var_flag = '1' then
         pc_inc<='1';
         state<=s0;
         else
         state<=s10a ;
         end if ;
 
         when s10a =>
         tempo<="00000000";
         lock_fsm<='0';
         pc_inc<='1';
         state<=s10b;
         when s10b =>
         pc_inc<='0';
         state<=s10c;
         when s10c =>
         pc_inc<='1';
         state<=s10d;
         when s10d =>
         pc_inc<='0';
         state<=s10e;
         when s10e =>
         pc_inc<='1';
         state<=s10f;
         when s10f =>
         pc_inc<='0';
         state<=s10g;
         when s10g =>
         pc_inc<='1';
         state<=s10h;
     when s10h =>
         c_adress2_out <= '1';
         lock_fsm<='1';
         state<=s0 ;
 
         when others =>
     end case ;
     end if ;
  end if;
 
end process ;
 
end archi_FSM ;

Browse

Tools

Subversion Repositories microprocessor

[/] [microprocessor/] [trunk/] [bench/] [VHDL/] [FSM.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	yacinenet	`-------------------------------------------------------------------------------`
2			`-- FSM (Finite State Machine)`
3			`--`
4			`--`
5			`-------------------------------------------------------------------------------`
6
7			`library IEEE;`
8
9			`use IEEE.STD_LOGIC_1164.all;`
10
11			`entity FSM is`
12			`port (`
13			`clk : in std_logic ;`
14			`d_in_FSM : in std_logic_vector (7 downto 0);`
15			`reset : in std_logic ;`
16			`compar2FSM : in std_logic ;`
17			`wo : out std_logic ;`
18			`oe : out std_logic ;`
19			`pc_inc : out std_logic ;`
20			`data2compar : out std_logic_vector (7 downto 0);`
21			`selec_fonc_compar: out std_logic_vector (1 downto 0);`
22			`selec_reg_resu1 : out std_logic_vector (2 downto 0);`
23			`adress_in : in std_logic_vector (15 downto 0);`
24			`ctrl_alu : out std_logic_vector (3 downto 0);`
25			`ctrl_adress : out std_logic_vector (1 downto 0);`
26			`adress_8 : out std_logic_vector (7 downto 0);`
27			`c_data_out : out std_logic ;`
28			`c_adress_out : out std_logic ;`
29			`c_flag_out : out std_logic ;`
30			`c_inALU : out std_logic ;`
31			`resu_compar : out std_logic ;`
32			`reg_resu2 : in std_logic_vector (7 downto 0);`
33			`c_in_compar : out std_logic ;`
34			`c_adress2_out : out std_logic ;`
35			`reg_flag2FSM : in std_logic_vector (4 downto 0);`
36			`p2fsm : in std_logic ;`
37			`fsm2p : out std_logic ;`
38			`lock_fsm2pc : out std_logic`
39			`);`
40			`end FSM ;`
41
42			`architecture archi_FSM of FSM is`
43
44			`type stat_type is (s0,s01,s1,s2,s21,s22,s23,s24,s25,s26,s27,s28,`
45			`s29,s3,s31,s32,s33,s34,s35,s36,s37,s4,s41,s42,s43,s44,s45,s46,`
46			`s5,s6,s7,s_ck1,s_ck2,s_ck3,s_ck4,s_ck5,s_ck6,s_ck7,s_ck8,s_ck9,`
47			`s_ck10,s_ck11,s8,s81,s9,s91,s92,s93,s94,s95,s96,s97,s98,s99,s10,s10a,`
48			`s10b,s10c,s10d,s10e,s10f,s10g,s10h);`
49
50
51			`signal tempo : std_logic_vector (7 downto 0);`
52			`signal tempo1 : std_logic_vector (3 downto 0);`
53			`signal temp_adress : std_logic_vector (15 downto 0);`
54			`signal statu : std_logic ;`
55			`signal var_flag : std_logic ;`
56			`signal lock_fsm : std_logic ;`
57			`signal state : stat_type ;`
58
59			`begin`
60
61			`process (reset,clk,d_in_FSM)`
62			`begin`
63			`if (reset='1') then`
64			`c_flag_out<='0';`
65			`pc_inc<='0';`
66			`selec_reg_resu1<="000";`
67			`ctrl_alu<="0000";`
68			`var_flag<='0';`
69			`ctrl_adress<="00";`
70			`wo <='0';`
71			`oe <='1';`
72			`adress_8<="00000000";`
73			`statu<='0';`
74			`c_inALU<='0';`
75			`c_adress_out<='0';`
76			`selec_fonc_compar<="00";`
77			`c_in_compar<='0';`
78			`fsm2p<='0';`
79			`data2compar<="00000000";`
80			`temp_adress<="0000000000000000";`
81			`tempo<="00000000";`
82			`c_data_out<='0';`
83			`resu_compar<='0';`
84			`c_adress2_out<='1';`
85			`lock_fsm<='1';`
86			`tempo1<="0000";`
87			`lock_fsm2pc<='0';`
88			`state<=s0;`
89			`else`
90			`if (clk'event and clk='1')then`
91			`if (p2fsm='0')then`
92			`wo <='0';`
93			`oe <='1';`
94			`lock_fsm2pc<='0';`
95			`else`
96			`if(p2fsm='1')then`
97			`if (lock_fsm='1') then`
98			`oe <='0';`
99			`fsm2p<='1';`
100			`lock_fsm2pc<='1';`
101			`end if;`
102			`end if;`
103			`end if;`
104
105			`tempo<=d_in_FSM ;`
106			`case state is`
107			`when s0 =>`
108			`pc_inc<='0';`
109			`if (lock_fsm='1') then`
110			`pc_inc<='1';`
111			`statu<= '0' ;`
112			`state<=s01;`
113			`end if ;`
114			`when s01 =>`
115			`pc_inc<='0';`
116			`state<=s1;`
117			`when s1=>`
118			`if statu = '0' then`
119			`case tempo is`
120			`when "00000001"=> --------------------- begin of ALU`
121			`ctrl_alu<="0001";`
122			`state<=s3;`
123			`when "00000010"=>`
124			`ctrl_alu<="0010";`
125			`state<=s3;`
126			`when "00000011"=>`
127			`ctrl_alu<="0011";`
128			`state<=s3;`
129			`when "00000100"=>`
130			`tempo1<="0100";`
131			`state<=s2;`
132			`when "00000101"=>`
133			`tempo1<="0101";`
134			`state<=s2;`
135			`when "00000110"=>`
136			`tempo1<="0110";`
137			`state<=s2;`
138			`when "00000111"=>`
139			`tempo1<="0111";`
140			`state<=s2;`
141			`when "00001000"=>`
142			`tempo1<="1000";`
143			`state<=s2;`
144			`when "00001001"=>`
145			`ctrl_alu<="1001";`
146			`state<=s3;`
147			`when "00001010"=>`
148			`ctrl_alu<="1010" ;`
149			`state<=s3;`
150			`when "00001011"=>`
151			`ctrl_alu<="1011";`
152			`state<=s3;`
153			`when "00001100"=>`
154			`ctrl_alu<="1100" ;`
155			`state<=s3; ----------------------- end of ALU`
156
157			`when "00010000"=> -------- acces to adress`
158			`state<=s4;`
159			`when "00100000"=> -------- return to address PC`
160			`state<=s9;`
161
162			`when "00110000"=> -- comparison >,<,=`
163			`state<=s5;`
164			`when "01000000"=>`
165			`state<=s6;`
166			`when "01010000"=>`
167			`state<=s7;`
168
169			`when "01100000"=> -- Release of the result`
170			`c_data_out<='1';`
171			`state<=s0;`
172
173			`when "01110000"=> -- load flag register`
174			`c_flag_out<='1';`
175			`pc_inc<='1';`
176			`state<=s0;`
177
178			`when "10000000"=> -- shift/rot`
179			`selec_reg_resu1<="001";`
180			`pc_inc<='1';`
181			`state<=s0;`
182			`when "10010000"=>`
183			`selec_reg_resu1<="010";`
184			`pc_inc<='1';`
185			`state<=s0;`
186			`when "10100000"=>`
187			`selec_reg_resu1<="011";`
188			`pc_inc<='1';`
189			`state<=s0;`
190			`when "10110000"=>`
191			`selec_reg_resu1<="100";`
192			`pc_inc<='1';`
193			`state<=s0;`
194			`when "11000000"=>`
195			`selec_reg_resu1<="101";`
196			`pc_inc<='1';`
197			`state<=s0;`
198			`when "11010000"=>`
199			`selec_reg_resu1<="110";`
200			`pc_inc<='1';`
201			`state<=s0;`
202
203			`when "11110000"=> -- whrite`
204			`state<=s8;`
205
206			`when "10000001"=> -- if zero`
207			`var_flag<=reg_flag2FSM(0);`
208			`state<=s10;`
209
210			`when "11110010"=> -- if parity`
211			`var_flag<=reg_flag2FSM(1);`
212			`state<=s10;`
213
214			`when "11110011"=> -- if 'comparison'`
215			`var_flag<=reg_flag2FSM(4);`
216			`state<=s10;`
217
218			`when "11110100"=> -- if cary`
219			`var_flag<=reg_flag2FSM(2);`
220			`state<=s10;`
221
222			`when "11110101"=> -- if overflow`
223			`var_flag<=reg_flag2FSM(3);`
224			`state<=s10;`
225
226			`when others =>`
227
228			`end case ;`
229			`end if ;`
230
231			`when s2=> ----- opcode a ,b =`
232			`lock_fsm<='0';`
233			`statu<= '1' ;`
234			`c_inALU<='1';`
235			`pc_inc<='1';`
236			`state<=s21;`
237			`when s21=>`
238			`pc_inc<='0';`
239			`state<=s22;`
240			`when s22 =>`
241			`ctrl_alu <= tempo1 ;`
242			`state<=s23;`
243			`when s23=> --- 1st clk`
244			`state<=s24;`
245			`when s24=> --- clk`
246			`state<=s25;`
247			`when s25=> --- clk`
248			`state<=s26;`
249			`when s26=> --- clk`
250			`state<=s27;`
251			`when s27=> --- clk`
252			`state<=s28;`
253			`when s28=> --- clk`
254			`selec_reg_resu1<= "111"; -- record the result in the register`
255			`state<=s29;`
256			`when s29=>`
257			`selec_reg_resu1<= "000";`
258			`pc_inc<='1';`
259			`c_inALU<='0';`
260			`lock_fsm<='1';`
261			`ctrl_alu <= "0000" ;`
262			`state<=s0;`
263
264			`when s3=> ------- opcode a =`
265			`lock_fsm<='0';`
266			`statu<= '1' ;`
267			`c_inALU<='1';`
268			`pc_inc<='1';`
269			`state<=s31;`
270			`when s31=>`
271			`pc_inc<='0';`
272			`state<=s32;`
273			`when s32 => --- 1stclk`
274			`state<=s33;`
275			`when s33 => --- clk`
276			`state<=s34;`
277			`when s34 => --- clk`
278			`state<=s35;`
279			`when s35=> --- clk`
280			`state<=s36;`
281			`when s36 => --- clk`
282			`selec_reg_resu1<= "111"; -- record the result in the register`
283			`state<=s37;`
284			`when s37 =>`
285			`selec_reg_resu1<= "000";`
286			`pc_inc<='1';`
287			`c_inALU<='0';`
288			`lock_fsm<='1';`
289			`ctrl_alu <= "0000" ;`
290			`state<=s0;`
291
292			`when s4=>`
293			`lock_fsm<='0';`
294			`temp_adress<=adress_in ;`
295			`pc_inc<='1';`
296			`state<=s41;`
297			`when s41=>`
298			`pc_inc<='0';`
299			`adress_8<=tempo ;`
300			`ctrl_adress<="01" ;`
301			`state<=s42;`
302			`when s42=>`
303			`pc_inc<='1';`
304			`state<=s43;`
305			`when s43 =>`
306			`pc_inc<='0';`
307			`adress_8<=tempo ;`
308			`ctrl_adress<="10" ;`
309			`state<=s44;`
310			`when s44 =>`
311			`ctrl_adress<="11" ;`
312			`state<=s45;`
313			`when s45=>`
314			`ctrl_adress<="00" ;`
315			`c_adress_out <= '1';`
316			`state<=s46;`
317			`when s46=>`
318			`c_adress_out <= '0';`
319			`lock_fsm<='1';`
320			`state<=s0;`
321
322			`when s5=> --- comparison <`
323			`selec_reg_resu1<= "000";`
324			`data2compar<=reg_resu2 ;`
325			`selec_fonc_compar<="01" ;`
326			`pc_inc<='1';`
327			`state<=s_ck1;`
328
329			`when s6=> --- comparison >`
330			`selec_reg_resu1<= "000";`
331			`data2compar<=reg_resu2 ;`
332			`selec_fonc_compar<="10" ;`
333			`pc_inc<='1';`
334			`state<=s_ck1;`
335
336			`when s7=> --- comparison =`
337			`selec_reg_resu1<= "000";`
338			`data2compar<=reg_resu2 ;`
339			`selec_fonc_compar<="11" ;`
340			`pc_inc<='1';`
341			`state<=s_ck1;`
342
343			`when s_ck1 =>`
344			`lock_fsm<='0';`
345			`pc_inc<='0';`
346			`c_in_compar<='1';`
347			`statu<= '1' ;`
348			`state<=s_ck2;`
349			`when s_ck2=> -- 1st clk`
350			`state<=s_ck3;`
351			`when s_ck3=> -- clk`
352			`state<=s_ck4;`
353			`when s_ck4 => -- clk`
354			`state<=s_ck5;`
355			`when s_ck5=> -- clk`
356			`state<=s_ck6;`
357			`when s_ck6=> -- clk`
358			`state<=s_ck7;`
359			`when s_ck7=> -- clk`
360			`state<=s_ck8;`
361			`when s_ck8=> -- clk`
362			`state<=s_ck9;`
363			`when s_ck9=> -- clk`
364			`state<=s_ck10;`
365			`when s_ck10=> -- clk`
366			`state<=s_ck11;`
367			`when s_ck11=> -- clk`
368			`resu_compar <= compar2FSM ;`
369			`pc_inc<='1';`
370			`c_in_compar<='0';`
371			`lock_fsm<='1';`
372			`state<=s0;`
373
374			`when s8=> -- whrite`
375			`pc_inc<='1';`
376			`wo <='1';`
377			`oe <='1';`
378			`c_data_out<='1';`
379			`state<=s81;`
380			`when s81=>`
381			`pc_inc<='0';`
382			`c_data_out<='0';`
383			`state<=s0;`
384
385			`when s9=> -- return to adress`
386			`lock_fsm<='0';`
387			`c_adress2_out<='0' ;`
388			`pc_inc<='0';`
389			`adress_8<=temp_adress(7 downto 0) ;`
390			`ctrl_adress<="10" ;`
391			`state<=s91;`
392			`when s91=>`
393			`adress_8<=temp_adress(15 downto 8) ;`
394			`ctrl_adress<="01" ;`
395			`state<=s92;`
396			`when s92=>`
397			`ctrl_adress<="11" ;`
398			`c_adress_out <= '1';`
399			`state<=s93;`
400			`when s93 =>`
401			`c_adress_out <= '0';`
402			`state<=s94;`
403			`when s94 =>`
404			`pc_inc<='1';`
405			`ctrl_adress<="00" ;`
406			`state<=s95;`
407			`when s95 =>`
408			`pc_inc<='0';`
409			`state<=s96;`
410			`when s96 =>`
411			`pc_inc<='1';`
412			`state<=s97;`
413			`when s97 =>`
414			`pc_inc<='0';`
415			`state<=s98 ;`
416			`when s98 =>`
417			`pc_inc<='1';`
418			`state<=s99 ;`
419			`when s99 =>`
420			`pc_inc<='0';`
421			`c_adress2_out<='1' ;`
422			`lock_fsm<='1';`
423			`state<=s0;`
424
425			`when s10 => -- is yes ;;`
426			`if var_flag = '1' then`
427			`pc_inc<='1';`
428			`state<=s0;`
429			`else`
430			`state<=s10a ;`
431			`end if ;`
432
433			`when s10a =>`
434			`tempo<="00000000";`
435			`lock_fsm<='0';`
436			`pc_inc<='1';`
437			`state<=s10b;`
438			`when s10b =>`
439			`pc_inc<='0';`
440			`state<=s10c;`
441			`when s10c =>`
442			`pc_inc<='1';`
443			`state<=s10d;`
444			`when s10d =>`
445			`pc_inc<='0';`
446			`state<=s10e;`
447			`when s10e =>`
448			`pc_inc<='1';`
449			`state<=s10f;`
450			`when s10f =>`
451			`pc_inc<='0';`
452			`state<=s10g;`
453			`when s10g =>`
454			`pc_inc<='1';`
455			`state<=s10h;`
456			`when s10h =>`
457			`c_adress2_out <= '1';`
458			`lock_fsm<='1';`
459			`state<=s0 ;`
460
461			`when others =>`
462			`end case ;`
463			`end if ;`
464			`end if;`
465
466			`end process ;`
467
468			`end archi_FSM ;`