Subversion Repositories microriscii

The encoding info is scattered in the source I'm gonna organize it all soon.

Registers:

0000: $SP - Stack Pointer

0001: $GP - Global Pointer

0010: $RA - Return Address

0011: $SYS - System

0100: $R0 - General Purpose Registers

0101: $R1

0110: $R2

0111: $R3

1000: $R4

1001: $R5

1010: $R6

1011: $R7

1100: $T0 - Temporary Registers

1101: $T1

1110: $T2

1111: $T3

MicroRISC II Instruction Set

Arithmetic:

ADD

SUB

MUL(U) // Optional / By default it is included

DIV(U) // Optional

MOD(U) // Optional

SHR

SHL

ROR

ROL

PCNT // Population One Count

PCNTZ // Population Zero Count

PCNTC // Population Change Count

RND // Random Number Generator

Arguments: reg,reg,reg

Arguments: reg,reg,imm16

0100:

| OP(4) | ALUOP(4) | REGD(4) | REGA(4) | REGB(4) | VOID(12) |

0101:

| OP(4) | ALUOP(4) | REGD(4) | REGA(4) | IMM(16) |

Logic:

OR

AND

XOR

NOT

Arguments: reg,reg,reg

0010:

| OP(4) | LOGICOP(2) | VOID(2) | REGD(4) | REGA(4) | REGB(4) | VOID(12) |

0011:

| OP(4) | LOGICOP(2) | HIGH/LOW(1) | VOID(1) | REGD(4) | REGA(4) | VOID(16) |

Memory:

LB/LW/LD(S)

SB/SW/SD

Arguments: reg,[reg+imm16]

0001:

| OP(4) | STORE/LOAD(1) | SIGNED(1) | SIZE(2) | REGD(4) | REGA(4) | IMM(16) |

Branch:

J(L) 1000

JR(L) 1001

BEQ(L) 1010

BNE(L) 1011

BZ(L) 1100

BNZ(L) 1101

BC(L) 1110

BNC(L) 1111

| OP(4) | REGD(4) | REGA(4) | REGB(4) | IMM(16) |

BLT(L)

BLTU(L)

BNL(L)

BNLU(L)

BGT(L)

BGTU(L)

BNG(L)

BNGU(L)

0111:

| OP(4) | BranchOP(4) | REGD(4) | REGA(4) | REGB(4) | VOID(4) | IMM(8) |

Interupts/Special:

NOP // No Operation

LLW imm16 // Load Low Word // Erases register and places 16bit value

LHW     imm16 // Load High Word // Erases register and places the 16bit value

SIV reg // Set Interupt Vector

GIV reg // Get Interupt Vector

THROW reg // Throw and load soft cause(16 bits)

THROW imm16 // Throw

CAUSE reg // Get Cause(32 bits)

IRET reg // Interupt Return

GPRSR reg // Get Program Restore State Register(Carry,etc.)

SPRSR reg // Set Program Restore State Register

SWMC // Switch Microcode Size(16bit/32bit)

0000:

| OP(4) | SOP(4) | REGD(4) | REGA(4) | IMM(16) |