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[/] [microriscii/] [trunk/] [verilog/] [rtl/] [cmp.v] - Blame information for rev 17

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//--------------------------------------------------------------------------------------------------
//
// Title       : cmp
// Design      : MicroRISCII
// Author      : Ali Mashtizadeh
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps
 
// Left to simplify decodeing
//`define               CMP_J           4'b0000
//`define               CMP_JR          4'b0001
`define         CMP_EQ          4'b0010
`define         CMP_NE          4'b0011
`define         CMP_C           4'b0100
`define         CMP_NC          4'b0101
`define         CMP_Z           4'b0110
`define         CMP_NZ          4'b0111
`define         CMP_LT          4'b1000
`define         CMP_NLT         4'b1001
`define         CMP_LTS         4'b1010
`define         CMP_NLTS        4'b1011
`define         CMP_GT          4'b1100
`define         CMP_NGT         4'b1101
`define         CMP_GTS         4'b1110
`define         CMP_NGTS        4'b1111
 
module cmp(a,b,cmp_op,true,c);
        // Inputs
        input   [31:0]   a;
        wire    [31:0]   a;
        input   [31:0]   b;
        wire    [31:0]   b;
        input   [3:0]    cmp_op;
        wire    [3:0]    cmp_op;
        input                   c;
        wire                    c;
        // Outputs
        output                  true;
        reg                             true;
        // Internal
        reg                             eq;
        reg                             lt;
        reg                             gt;
        reg                             lts;
        reg                             gts;
        reg                             z;
 
        always @ (a || b)
                begin
                        if (a == b)
                                eq = 1'b1;
                        else
                                eq = 1'b0;
                        if (a < b)
                                lt = 1'b1;
                        else
                                lt = 1'b0;
                        if ((a[30:0] < b[30]) && a[31] && b[31])
                                lts = 1'b1;
                        else if (a[31] == 1'b1 && b[31] == 1'b0)
                                lts = 1'b1;
                        else
                                lts = 1'b0;
                        if (a > b)
                                gt = 1'b1;
                        else
                                gt = 1'b0;
                        if ((a[30:0] > b[30]) && a[31] && b[31])
                                gts = 1'b1;
                        else if (a[31] == 1'b0 && b[31] == 1'b1)
                                gts = 1'b1;
                        else
                                gts = 1'b0;
                        if (a == 32'b0)
                                z = 1'b1;
                        else
                                z = 1'b0;
                end
 
        always @ (cmp_op || eq || z || c || lt || gt)
                case (cmp_op)
                        //`CMP_J : true = 1'b1; // Taken care of in decoder
                        //`CMP_JR : true = 1'b1; // Taken care of in decoder
                        `CMP_EQ : true = eq;
                        `CMP_NE : true = !(eq);
                        `CMP_Z : true = z;
                        `CMP_NZ : true = !(z);
                        `CMP_C : true = c;
                        `CMP_NC : true = !(c);
                        `CMP_LT : true = lts;
                        `CMP_NLT : true = !(lts);
                        `CMP_LTS : true = lt;
                        `CMP_NLTS : true = !(lt);
                        `CMP_GT : true = gts;
                        `CMP_NGT : true = !(gts);
                        `CMP_GTS : true = gt;
                        `CMP_NGTS : true = !(gt);
                endcase
 
endmodule

Line No.	Rev	Author	Line
1	12	alikat	`//--------------------------------------------------------------------------------------------------`
2			`//`
3			`// Title : cmp`
4			`// Design : MicroRISCII`
5			`// Author : Ali Mashtizadeh`
6			`//`
7			`//-------------------------------------------------------------------------------------------------`
8			`timescale 1ps / 1ps
9
10			`// Left to simplify decodeing`
11			//`define CMP_J 4'b0000
12			//`define CMP_JR 4'b0001
13			`define CMP_EQ 4'b0010
14			`define CMP_NE 4'b0011
15			`define CMP_C 4'b0100
16			`define CMP_NC 4'b0101
17			`define CMP_Z 4'b0110
18			`define CMP_NZ 4'b0111
19			`define CMP_LT 4'b1000
20			`define CMP_NLT 4'b1001
21			`define CMP_LTS 4'b1010
22			`define CMP_NLTS 4'b1011
23			`define CMP_GT 4'b1100
24			`define CMP_NGT 4'b1101
25			`define CMP_GTS 4'b1110
26			`define CMP_NGTS 4'b1111
27
28			`module cmp(a,b,cmp_op,true,c);`
29			`// Inputs`
30			`input [31:0] a;`
31			`wire [31:0] a;`
32			`input [31:0] b;`
33			`wire [31:0] b;`
34			`input [3:0] cmp_op;`
35			`wire [3:0] cmp_op;`
36			`input c;`
37			`wire c;`
38			`// Outputs`
39			`output true;`
40			`reg true;`
41			`// Internal`
42			`reg eq;`
43			`reg lt;`
44			`reg gt;`
45			`reg lts;`
46			`reg gts;`
47			`reg z;`
48
49			`always @ (a \|\| b)`
50			`begin`
51			`if (a == b)`
52			`eq = 1'b1;`
53			`else`
54			`eq = 1'b0;`
55			`if (a < b)`
56			`lt = 1'b1;`
57			`else`
58			`lt = 1'b0;`
59			`if ((a[30:0] < b[30]) && a[31] && b[31])`
60			`lts = 1'b1;`
61			`else if (a[31] == 1'b1 && b[31] == 1'b0)`
62			`lts = 1'b1;`
63			`else`
64			`lts = 1'b0;`
65			`if (a > b)`
66			`gt = 1'b1;`
67			`else`
68			`gt = 1'b0;`
69			`if ((a[30:0] > b[30]) && a[31] && b[31])`
70			`gts = 1'b1;`
71			`else if (a[31] == 1'b0 && b[31] == 1'b1)`
72			`gts = 1'b1;`
73			`else`
74			`gts = 1'b0;`
75			`if (a == 32'b0)`
76			`z = 1'b1;`
77			`else`
78			`z = 1'b0;`
79			`end`
80
81			`always @ (cmp_op \|\| eq \|\| z \|\| c \|\| lt \|\| gt)`
82			`case (cmp_op)`
83			//`CMP_J : true = 1'b1; // Taken care of in decoder
84			//`CMP_JR : true = 1'b1; // Taken care of in decoder
85			`CMP_EQ : true = eq;
86			`CMP_NE : true = !(eq);
87			`CMP_Z : true = z;
88			`CMP_NZ : true = !(z);
89			`CMP_C : true = c;
90			`CMP_NC : true = !(c);
91			`CMP_LT : true = lts;
92			`CMP_NLT : true = !(lts);
93			`CMP_LTS : true = lt;
94			`CMP_NLTS : true = !(lt);
95			`CMP_GT : true = gts;
96			`CMP_NGT : true = !(gts);
97			`CMP_GTS : true = gt;
98			`CMP_NGTS : true = !(gt);
99			`endcase`
100
101			`endmodule`

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[/] [microriscii/] [trunk/] [verilog/] [rtl/] [cmp.v] - Blame information for rev 17