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[/] [microriscii/] [trunk/] [verilog/] [rtl/] [lu.v] - Blame information for rev 17

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1 8 alikat 
//--------------------------------------------------------------------------------------------------
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//
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// Title       : lu
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// Design      : MicroRISCII
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// Author      : Ali Mashtizadeh
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//
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//--------------------------------------------------------------------------------------------------
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`timescale 1ps / 1ps
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`define         LOGIC_NOT       4'b00
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`define         LOGIC_OR        4'b01
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`define         LOGIC_AND       4'b10
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`define         LOGIC_XOR       4'b11
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module lu(a,b,logic_op,o);
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        // Inputs
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        input   [31:0]   a;
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        wire    [31:0]   a;
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        input   [31:0]   b;
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        wire    [31:0]   b;
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        input   [3:0]    logic_op;
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        wire    [3:0]    logic_op;
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        // Outputs
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        output  [31:0]   o;
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        reg             [31:0]   o;
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        always @ (logic_op || a || b)
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                case (logic_op)
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                        `LOGIC_NOT :  o = !(a);
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                        `LOGIC_OR : o = a || b;
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                        `LOGIC_AND : o = a && b;
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                        `LOGIC_XOR : o = a ^^ b;
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                endcase
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endmodule

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