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[/] [mini_aes/] [trunk/] [README] - Blame information for rev 21

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# $Id: README,v 1.1.1.1 2005-12-06 02:47:45 arif_endro Exp $
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Directory Layout
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.
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|-- bench  -> the test bench directory
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|
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|-- data   -> data files, `ecb_tbl.txt' file used for verification.
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|
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|-- doc    -> documentation files
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|
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`-- source -> the VHDL source of this project.
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Test Bench
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If you want to run the test bench, then go to the bench subdirectory and
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then run the modelsim do file, i.e. `modelsim_bench.do'. This simulation
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will generate an output into a file called `ecb_tbl_result_enc.txt' and
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`ecb_tbl_result_dec.txt', then you can analyze those file to see the
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result.
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Sincerely,
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Arif E. Nugroho
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