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arif_endro |
# $Id: modelsim_bench.do,v 1.1.1.1 2005-12-06 02:47:46 arif_endro Exp $
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# destroy .wave
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quit -sim
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vlib work
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vcom -cover bcesx ../source/bram_block_a.vhdl
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vcom -cover bcesx ../source/bram_block_b.vhdl
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vcom -cover bcesx ../source/counter2bit.vhdl
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vcom -cover bcesx ../source/key_scheduler.vhdl
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vcom -cover bcesx ../source/xtime.vhdl
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vcom -cover bcesx ../source/mix_column.vhdl
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vcom -cover bcesx ../source/folded_register.vhdl
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vcom -cover bcesx ../source/mini_aes.vhdl
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vcom -cover bcesx input.vhdl
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vcom -cover bcesx output.vhdl
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vcom -cover bcesx modelsim_bench.vhdl
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# vsim -coverage modelsim_bench
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vsim modelsim_bench
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# .wave.tree zoomrange {0ns} {200ns}
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# .wave.tree zoomrange {4000ns} {4400ns}
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# .wave.tree zoomin 2
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add wave sim:/modelsim_bench/clock_enc
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add wave sim:/modelsim_bench/clear_enc
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add wave sim:/modelsim_bench/my_aes_enc/enc
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add wave sim:/modelsim_bench/done_enc
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add wave sim:/modelsim_bench/test_iteration_enc
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add wave -hex sim:/modelsim_bench/data_i_enc
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add wave -hex sim:/modelsim_bench/key_i_enc
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add wave -hex sim:/modelsim_bench/cipher_o_enc
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add wave -hex sim:/modelsim_bench/data_o_enc
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add wave sim:/modelsim_bench/my_output_enc/passed
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add wave sim:/modelsim_bench/my_output_enc/failed
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add wave sim:/modelsim_bench/clock_dec
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add wave sim:/modelsim_bench/clear_dec
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add wave sim:/modelsim_bench/my_aes_dec/enc
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add wave sim:/modelsim_bench/done_dec
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add wave sim:/modelsim_bench/test_iteration_dec
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add wave -hex sim:/modelsim_bench/data_i_dec
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add wave -hex sim:/modelsim_bench/key_i_dec
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add wave -hex sim:/modelsim_bench/cipher_o_dec
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add wave -hex sim:/modelsim_bench/data_o_dec
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add wave sim:/modelsim_bench/my_output_dec/passed
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add wave sim:/modelsim_bench/my_output_dec/failed
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run 21300ns
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