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[/] [mini_aes/] [trunk/] [bench/] [output.vhdl] - Blame information for rev 16

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1 7 arif_endro
-- $Id: output.vhdl,v 1.2 2005-12-23 04:27:00 arif_endro Exp $
2 2 arif_endro
-------------------------------------------------------------------------------
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-- Title       : Output
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-- Project     : Mini AES 128 
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-------------------------------------------------------------------------------
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-- File        : output.vhdl
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-- Author      : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Created     : 2005/12/03
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-- Last update : 
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-- Simulators  : ModelSim SE PLUS 6.0
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-- Synthesizers: ISE Xilinx 6.3i
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-- Target      : 
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-------------------------------------------------------------------------------
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-- Description : Output file to analize and record output of test bench.
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-------------------------------------------------------------------------------
16 16 arif_endro
-- Copyright (C) 2005 Arif Endro Nugroho
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-------------------------------------------------------------------------------
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-- 
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--         THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ASSOCIATED DISCLAIMER.
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-- 
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-------------------------------------------------------------------------------
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-- 
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--         THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- 
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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entity output is
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  port (
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    clock          : in std_logic;
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    clear          : in std_logic;
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    load           : in std_logic;
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    enc            : in std_logic;
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    done           : in std_logic;
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    test_iteration : in integer;
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    verifier       : in std_logic_vector (007 downto 000);
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    data_o         : in std_logic_vector (007 downto 000)
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    );
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end output;
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architecture test_bench of output is
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  file out_enc_file_ptr : text open write_mode is "ecb_tbl_result_enc.txt";
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  file out_dec_file_ptr : text open write_mode is "ecb_tbl_result_dec.txt";
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  signal failed         : integer := 0;
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  signal passed         : integer := 0;
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65 7 arif_endro
  type fifo16x8 is array (0 to 15) of std_logic_vector (7 downto 0);
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  signal fifo_verifier : fifo16x8 :=
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  (
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   B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
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   B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
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   B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
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   B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000"
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  );
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  signal counter : integer range 0 to 15 := 0;
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  signal current_verifier : std_logic_vector (7 downto 0);
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begin
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  process(clock, clear)
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  begin
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  if (clear = '1') then
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     counter <= 0;
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  elsif (clock = '1' and clock'event) then
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     if (done = '0') then
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        counter <= 0;
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     elsif (counter < 15 ) then
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        counter <= counter + 1;
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     else
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        counter <= 0;
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     end if;
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  end if;
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  end process;
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  current_verifier <= fifo_verifier(counter);
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  process(clock, clear)
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  begin
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  if (clear = '1') then
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  fifo_verifier <= (others => ( others => '0'));
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  elsif(clock = '1' and clock'event) then
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     if (load = '1') then
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     fifo_verifier <= (fifo_verifier (1 to 15) & verifier);
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     end if;
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  end if;
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  end process;
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  process (clock)
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    variable out_line                     : line;
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  begin
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    if (clock = '1' and clock'event) then
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      if (done = '1') then
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        write(out_line, string'("Test ====> "));
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        write(out_line, test_iteration);
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        write(out_line, string'(" byte "));
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        write(out_line, counter);
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        if ( enc = '0') then
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          writeline(out_enc_file_ptr, out_line);
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        else
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          writeline(out_dec_file_ptr, out_line);
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        end if;
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        write(out_line, string'("Expected : "));
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        write(out_line, current_verifier);
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        if ( enc = '0') then
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          writeline(out_enc_file_ptr, out_line);
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        else
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          writeline(out_dec_file_ptr, out_line);
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        end if;
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        write(out_line, string'("Got      : "));
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        write(out_line, data_o);
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        if ( enc = '0') then
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          writeline(out_enc_file_ptr, out_line);
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        else
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          writeline(out_dec_file_ptr, out_line);
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        end if;
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        write(out_line, string'("Status   : "));
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        if (current_verifier = data_o ) then
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          write (out_line, string'("OK"));
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          passed <= passed + 1;
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        else
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          write (out_line, string'("FAILED"));
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          failed <= failed + 1;
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        end if;
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        if ( enc = '0') then
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          writeline(out_enc_file_ptr, out_line);
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        else
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          writeline(out_dec_file_ptr, out_line);
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        end if;
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      end if;
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    end if;
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  end process;
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end test_bench;

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