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% $Id: mini_aes.tex,v 1.1.1.1 2005-12-06 02:48:28 arif_endro Exp $
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%
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% Title : Mini AES 128
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%
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% Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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%
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% Description : Master Documentation File.
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%
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% Copyright (C) 2005 Arif E. Nugroho <arif_endro@yahoo.com>
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\documentclass[a4paper,12pt]{report}
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\usepackage[english]{babel}
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\usepackage[dvips,english,none,light,portrait]{draftcopy}
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\usepackage{fancyvrb} % enable custom verbatim env.
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\usepackage{float} % enable floating images
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\usepackage{graphicx} % enable graphics in this document
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\usepackage{titlesec} % enable customization title
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\usepackage{fancyhdr} % enable customization header e.g. page number
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\usepackage{setspace} % Custom line spacing
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\usepackage{palatino}
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%\usepackage{times} % Default font for report
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\usepackage{indentfirst} % to make identation after sectioning
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\usepackage[pdftitle={Mini AES 128},
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pdfauthor={Copyright (C) 2005 Arif E. Nugroho},
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pdfsubject={Mini AES 128},
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pdfkeywords={AES},
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colorlinks=false, bookmarksnumbered=false, ps2pdf,
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pdfpagemode=none
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]{hyperref}
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\setlength{\topmargin} {0cm}
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\setlength{\textwidth} {16cm}
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\setlength{\oddsidemargin} {0cm}
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\setlength{\evensidemargin}{0cm}
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\setlength{\parindent}{1cm} % set paragraph indentation 1cm almost
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% equal to 5 character
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\lhead{\scriptsize{\textsf{\rightmark}}}
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\rhead{\thepage}
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\chead{}
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\lfoot{}
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\rfoot{}
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\cfoot{Arif E. Nugroho\\www.opencores.org}
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\titlelabel{\thetitle.\quad}
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% Chapter heading layout
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\titleformat{\chapter}[display]
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{\normalfont\Large\filcenter\bfseries}
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{ \vspace{1pc} \LARGE\thechapter}
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{1pc} { \vspace{1pc} \Huge}
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\onehalfspacing
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\makeatletter
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% numbering in equation by chapter
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\renewcommand\theequation{\arabic{chapter}-\arabic{equation}}
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\@addtoreset{equation}{chapter}
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% numbering in figure by section
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% numbering in table by section
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\@addtoreset{table}{chapter}
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\makeatother
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\title{\\Large\textbf{Mini AES 128}\\}
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\author{Arif E. Nugroho\\
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Department of Electrical Engineering\\
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Institut Teknologi Bandung, Indonesia\\
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e-mail: arif\_endro@yahoo.com}
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\date{}
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\begin{document}
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\begin{titlepage}
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\tt
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\thispagestyle{empty}
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\center
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{\Large\textbf{Mini AES 128\\}}
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\vspace{2.0cm}
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%\begin{figure}[H]
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%\center
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%\includegraphics[width=4.0cm,height=4.0cm]{oc_logo.eps}
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%\end{figure}
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\vspace{4.5cm}
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\normalsize
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\textbf{Arif E. Nugroho}\\
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$\overline{\textbf{arif\_endro@opencores.org}}$\\
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\vspace{1.50cm}
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%Progress: 60\%
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\vspace{2.00cm}
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\begin{figure}[H]
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\center
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\includegraphics[width=3.0cm,height=3.0cm]{oc_logo.eps}
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\end{figure}
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\vspace{1.50cm}
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\textbf{
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\begin{tabular}{p{4.0cm}p{10cm}}
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& VLSI Research Group\\
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& LabTek VIII Institut Teknologi Bandung\\
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& Jl.~Ganesha 10 Bandung 40141\\
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& West Java, Indonesia\\
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\end{tabular}
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}
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\end{titlepage}
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\pagenumbering{roman}
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\tableofcontents
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%\listoffigures
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\pagestyle{fancy}
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\chapter{AES 128}
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\pagenumbering{arabic}
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\vspace{2cm}
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\section{Introduction}
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The National Institute of Standards and Technology (NIST) choose the
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Rijndael algorithm as the new Advanced Encryption Standard (AES) in
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2001. Rijndael algorithm is a symmetric block cipher that can process
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data block of 128 bits, using cipher keys with length of 128, 192, and
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256 bits. The algorithm can be used on different key length and may be
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referred to as "AES-128", "AES-192", and "AES-256". This crypto core is
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a hardware implementation of Rijndael algorithm that process 128 bit
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block of data using 128 bit key or ussually called as AES-128.
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\section{Circuit Architecture}
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The architecture of this implementation is based on the paper described
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by P. Chodowiec \cite{chodowiec}, the schematic diagram of circuit
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implementation is as follows:
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\begin{figure}[H]
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\center
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\includegraphics[width=15cm,height=10cm]{circuit_schematic.eps}
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\caption{Circuit schematic}
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\label{circuit_schematic}
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\end{figure}
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\section{Simulation}
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Simulation is done by ModelSim 6.0 SE, the simulation is performed to
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verify the correctness of design. The encryption and decrption units has
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been verified using Electronic Codebook (ECB) method and passed 128 test
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vector verification phase of Tables Known Answer Test (KAT).
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\section{Synthesize}
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This design has been synthesized using ISE Xilinx 6.3i, here is the
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summary of the area utilization in FPGA Xilinx:
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\begin{table}[H]
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\center
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\includegraphics[width=8cm,height=2.5cm]{area.eps}
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\caption{Area utilizations summary}
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\label{area}
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\end{table}
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The maximum clock frequency is 50.155 MHz (Minimum period 19.938ns)
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\section{Circuit Explanation}
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\begin{figure}[H]
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\center
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\includegraphics[width=5cm,height=4cm]{aes128block.eps}
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\caption{AES 128 Input - Output Pin}
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\label{aes128block}
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\end{figure}
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The AES 128 is composed from four subcircuit, these subcircuit are :
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\begin{itemize}
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\item ShiftRow
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\item SubByte
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\item MixColumn
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\item KeyScheduler
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\end{itemize}
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%These subcircuit is the main component that build AES 128.
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\subsection{ShiftRow}
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ShiftRow transformation is performed by arranging the sequence of input
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data to be processed, these transformation is performed this way:
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\begin{displaymath}
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\left\{
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\begin{array}{lcl}
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input & & output \\
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0,5,a,f & => & 0,1,2,3\\
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4,9,e,3 & => & 4,5,6,7\\
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8,d,2,7 & => & 8,9,a,b\\
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c,1,6,b & => & c,d,e,f\\
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\end{array}
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\right\}
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\end{displaymath}
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the InvShiftRow transformations operations is performed using the
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following sequence of input data:
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\begin{displaymath}
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\left\{
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\begin{array}{lcl}
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input & & output \\
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0,d,a,7 & => & 0,1,2,3\\
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4,1,e,b & => & 4,5,6,7\\
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8,5,2,f & => & 8,9,a,b\\
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c,9,6,3 & => & c,d,e,f\\
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\end{array}
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\right\}
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\end{displaymath}
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\subsection{SubByte}
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SubByte transformation is implemented using dedicated block RAM, SubByte
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transformation occupy 4 Kb Block RAM in 512x8 configurations.
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\subsection{MixColumn}
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The MixColumn is implemented using matrix calculation of following equation:
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\begin{equation}
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c(x) =~'03'~x^3 +~'01'~x^2 +~'01'~x +~'02'.
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\end{equation}
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matrix form of above equation is:
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\begin{displaymath}
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\left[ \begin{array}{c} b_0\\ b_1\\ b_2\\ b_3\\ \end{array} \right]
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=
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\left[ \begin{array}{c} 02~03~01~01\\ 01~02~03~01\\ 01~01~02~03\\ 03~01~01~02\\ \end{array} \right]
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\left[ \begin{array}{c} a_0\\ a_1\\ a_2\\ a_3\\ \end{array} \right]
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\end{displaymath}
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The InvMixColumn operations is performed using following equation:
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\begin{equation}
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d(x) =~'0b'~x^3 +~'0d'~x^2 +~'09'~x +~'0e'.
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\end{equation}
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in matrix representation is:
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\begin{displaymath}
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\left[ \begin{array}{c} d_0\\ d_1\\ d_2\\ d_3\\ \end{array} \right]
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=
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\left[ \begin{array}{c} 0e~0b~0d~09\\ 09~0e~0b~0d\\ 0d~09~0e~0b\\ 0b~0d~09~0e\\ \end{array} \right]
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\left[ \begin{array}{c} c_0\\ c_1\\ c_2\\ c_3\\ \end{array} \right]
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\end{displaymath}
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The InvMixColumn can be implemented using resource sharing, by following
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equation:
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\begin{equation}
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c(x) \otimes d(x) =~'01'
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\end{equation}
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then if we multiply both side with $d^2(x)$ then it become:
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\begin{equation}
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c(x) \otimes d^2(x) = d(x)
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\end{equation}
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above equation state that we can get the InvMixColumn using
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multiplication of MixColumn operations and $d^2(x)$:
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\begin{equation}
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d^2(x) =~'04'~x^2 +~'05'.
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\end{equation}
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and matrix representation of above equation is:
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\begin{displaymath}
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\left[ \begin{array}{c} e_0\\ e_1\\ e_2\\ e_3\\ \end{array} \right]
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=
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\left[ \begin{array}{c} 05~00~04~00\\ 00~05~00~04\\ 04~00~05~00\\ 00~04~00~05\\ \end{array} \right]
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\left[ \begin{array}{c} c_0\\ c_1\\ c_2\\ c_3\\ \end{array} \right]
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\end{displaymath}
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\subsection{KeyScheduler}
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The KeyScheduler is implemented using the following schematic diagram:
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\begin{figure}[H]
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\center
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\includegraphics[width=9cm,height=6cm]{key_scheduler.eps}
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\caption{KeyScheduler Schematics}
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\label{key_scheduler}
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\end{figure}
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\section{TODO}
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\begin{itemize}
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%\item Finish decryption circuit.
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\item Optimize Key Scheduler storage allocations implementations.
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\item Optimize folded register implementation.
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\item Implement TriState Buffer for switching SubBytes utilization.
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\item Update documentation.
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\item CleanUp code.
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\end{itemize}
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\begin{thebibliography}{1}
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\bibitem{chodowiec}
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Pawel Chodowiec and Kris Gaj, \textbf{Very Compact FPGA Implementation
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of the AES Algorithm}, CHES 2003, LNCS 2779, pp. 319-333
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\bibitem{fips197}
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Federal Information Processing Standards Publication 197,
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\textbf{Advanced Encryption Standard (AES)}, National Institute of
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Standards and Technology, 2001.
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\bibitem{rijndael}
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Daemen J. and Rijmen V., \textbf{AES Proposal: The Rijndael Block Cipher},\\
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\href{http://www.esat.kuleuven.ac.be/~rijmen/rijndael/Rijndael.pdf}{http://www.esat.kuleuven.ac.be/\~~rijmen/rijndael/Rijndael.pdf}
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%\bibitem{wada}
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%Tom Wada, \textbf{2-D Product Code Iterative Decoder},\\
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%\href{http://www.ie.u-ryukyu.ac.jp/\~\ wada/design06/spec\_e.html}
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% {http://www.ie.u-ryukyu.ac.jp/\~\ wada/design06/spec\_e.html}\\
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% October 1$^{st}$, 2005
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\end{thebibliography}
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\appendix
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| 344 |
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| 345 |
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\chapter{Informations}
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| 346 |
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\section{Tools}
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| 348 |
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\begin{itemize}
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| 350 |
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\item \textbf{ModelSim 6.0} The Simulator
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| 351 |
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\item \textbf{Xilinx 6.3i} The Synthesizer
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| 352 |
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\item \textbf{VIM} (Vi IMproved) / \textbf{Emacs} The Editor
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| 353 |
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\item \textbf{\LaTeX}~~The Typesetter
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| 354 |
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\item \textbf{OpenOffice.org 2.0} The Drawer
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| 355 |
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\end{itemize}
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| 356 |
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\vspace{1cm}
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| 358 |
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\begin{tabbing}
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| 359 |
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\textbf{Version: 1.0}
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| 360 |
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\end{tabbing}
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\end{document}
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