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[/] [mini_aes/] [trunk/] [source/] [counter2bit.vhdl] - Blame information for rev 15

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1 2 arif_endro
-- $Id: counter2bit.vhdl,v 1.1.1.1 2005-12-06 02:48:32 arif_endro Exp $
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-------------------------------------------------------------------------------
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-- Title       : Counter 2 bit
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-- Project     : Mini AES 128 
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-------------------------------------------------------------------------------
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-- File        : counter2bit.vhdl
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-- Author      : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Created     : 2005/12/03
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-- Last update : 
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-- Simulators  : ModelSim SE PLUS 6.0
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-- Synthesizers: ISE Xilinx 6.3i
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-- Target      : 
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-------------------------------------------------------------------------------
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-- Description : Counter 2 bit (e.g. from 0 to 3)
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-------------------------------------------------------------------------------
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-- Copyright (C) 2005 Arif Endro Nugroho
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-------------------------------------------------------------------------------
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-- 
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--         THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ASSOCIATED DISCLAIMER.
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-- 
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-------------------------------------------------------------------------------
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-- 
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--         THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- 
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity counter2bit is
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   port (
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      clock : in  std_logic;
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      clear : in  std_logic;
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      count : out std_logic_vector (1 downto 0)
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      );
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end counter2bit;
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architecture data_flow of counter2bit is
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signal tmp : std_logic_vector (1 downto 0) := ( B"00" );
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begin
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   process (clock, clear)
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   begin
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      if (clear = '1') then
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         tmp <= "00";
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      elsif (clock = '1' and clock'event) then
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         tmp <= tmp + 1;
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      end if;
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   end process;
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   count <= tmp;
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end data_flow;

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