OpenCores
URL https://opencores.org/ocsvn/mini_aes/mini_aes/trunk

Subversion Repositories mini_aes

[/] [mini_aes/] [trunk/] [source/] [io_interface.vhdl] - Blame information for rev 14

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 arif_endro 
-- $Id: io_interface.vhdl,v 1.1 2005-12-23 04:19:55 arif_endro Exp $
2 
-------------------------------------------------------------------------------
3 
-- Title       : IO Interface
4 
-- Project     : Mini AES 128
5 
-------------------------------------------------------------------------------
6 
-- File        : io_interface.vhdl
7 
-- Author      : "Arif E. Nugroho" <arif_endro@yahoo.com>
8 
-- Created     : 2005/12/22
9 
-- Last update :
10 
-- Simulators  : ModelSim SE PLUS 6.0
11 
-- Synthesizers: ISE Xilinx 6.3i
12 
-- Target      :
13 
-------------------------------------------------------------------------------
14 
-- Description : IO Interface used to implement 8bit communications.
15 
-------------------------------------------------------------------------------
16 
-- Copyright (C) 2005 Arif E. Nugroho
17 
-- This VHDL design file is an open design; you can redistribute it and/or
18 
-- modify it and/or implement it after contacting the author
19 
-------------------------------------------------------------------------------
20 
-------------------------------------------------------------------------------
21 
--
22 
--         THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
23 
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
24 
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
25 
-- ASSOCIATED DISCLAIMER.
26 
--
27 
-------------------------------------------------------------------------------
28 
--
29 
--         THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
30 
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
31 
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
32 
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
34 
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
35 
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
36 
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
37 
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
38 
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 
--
40 
-------------------------------------------------------------------------------
41 
library ieee;
42 
use ieee.std_logic_1164.all;
43 
use ieee.std_logic_arith.all;
44 
use ieee.std_logic_unsigned.all;
45 
 
46 
entity io_interface is
47 
   port (
48 
      clock      : in  std_logic;
49 
      clear      : in  std_logic;
50 
      load_i     : in  std_logic;
51 
      load_i_int : out std_logic;
52 
      data_i     : in  std_logic_vector (7 downto 0);
53 
      key_i      : in  std_logic_vector (7 downto 0);
54 
      data_o     : out std_logic_vector (7 downto 0);
55 
      data_o_int : in  std_logic_vector (127 downto 000);
56 
      data_i_int : out std_logic_vector (127 downto 000);
57 
      key_i_int  : out std_logic_vector (127 downto 000);
58 
      done_o_int : in  std_logic;
59 
      done_o     : out std_logic
60 
      );
61 
end io_interface;
62 
 
63 
architecture data_flow of io_interface is
64 
 
65 
type fifo16x8 is array ( 0 to 15 ) of std_logic_vector (7 downto 0);
66 
 
67 
signal fifo_data : fifo16x8 :=
68 
(
69 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
70 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
71 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
72 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000"
73 
);
74 
 
75 
signal fifo_key : fifo16x8 :=
76 
(
77 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
78 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
79 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
80 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000"
81 
);
82 
 
83 
signal fifo_output : fifo16x8 :=
84 
(
85 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
86 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
87 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
88 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000"
89 
);
90 
 
91 
signal load_core   : std_logic := '0';
92 
signal done_int    : std_logic := '0';
93 
signal up_counter  : integer range 0 to 15 := 0;
94 
-- signal data_o_int : std_logic_vector (127 downto 000) :=
95 
--   ( X"3925841D_02DC09FB_DC118597_196A0B32" );  -- CT 0
96 
 
97 
begin
98 
 
99 
load_i_int <= load_core;
100 
 
101 
process(clock, clear)
102 
begin
103 
if (clear = '1') then
104 
   done_o <= '0';
105 
elsif (clock = '1' and clock'event) then
106 
   done_o <= done_int;
107 
end if;
108 
end process;
109 
 
110 
process(clock, clear)
111 
begin
112 
if (clear = '1') then
113 
   up_counter <= 0;
114 
elsif (clock = '1' and clock'event) then
115 
   if (done_o_int = '1') then
116 
      up_counter <= 0;
117 
-- elsif ((up_counter = 0) and (done_o_int = '1')) then
118 
-- elsif (done_o_int = '0' and done_o_int'event) then
119 
-- 20051219 FIXME
120 
      done_int   <= '1';
121 
   elsif (up_counter < 15 ) then
122 
      up_counter <= up_counter + 1;
123 
   else
124 
--    up_counter <= 0;
125 
      done_int   <= '0';
126 
   end if;
127 
end if;
128 
end process;
129 
 
130 
process(clock, clear)
131 
begin
132 
if (clear = '1') then
133 
   fifo_output <= (others => (others => '0'));
134 
elsif (clock = '1' and clock'event) then
135 
   if (done_o_int = '1') then
136 
      fifo_output <= ( data_o_int (127 downto 120), data_o_int (119 downto 112), data_o_int (111 downto 104),
137 
                       data_o_int (103 downto 096), data_o_int (095 downto 088), data_o_int (087 downto 080),
138 
                       data_o_int (079 downto 072), data_o_int (071 downto 064), data_o_int (063 downto 056),
139 
                       data_o_int (055 downto 048), data_o_int (047 downto 040), data_o_int (039 downto 032),
140 
                       data_o_int (031 downto 024), data_o_int (023 downto 016), data_o_int (015 downto 008),
141 
                       data_o_int (007 downto 000));
142 
   end if;
143 
end if;
144 
end process;
145 
 
146 
process(clock, clear)
147 
begin
148 
if (clear = '1') then
149 
data_o <= (others => '0');
150 
elsif (clock = '1' and clock'event) then
151 
data_o <= fifo_output(up_counter);
152 
end if;
153 
end process;
154 
 
155 
process(clock, clear)
156 
begin
157 
   if (clear = '1') then
158 
      fifo_key     <= (others => (others => '0'));
159 
      fifo_data    <= (others => (others => '0'));
160 
      load_core    <= '1';
161 
   elsif (clock = '1' and clock'event) then
162 
      if (load_i  = '1') then
163 
         fifo_key     <= (fifo_key (1 to 15) & key_i);
164 
         fifo_data    <= (fifo_data (1 to 15) & data_i);
165 
      end if;
166 
         load_core    <= load_i;
167 
   end if;
168 
end process;
169 
 
170 
key_i_int<= ( fifo_key (00) & fifo_key (01) & fifo_key (02) & fifo_key (03) &
171 
              fifo_key (04) & fifo_key (05) & fifo_key (06) & fifo_key (07) &
172 
              fifo_key (08) & fifo_key (09) & fifo_key (10) & fifo_key (11) &
173 
              fifo_key (12) & fifo_key (13) & fifo_key (14) & fifo_key (15) );
174 
 
175 
data_i_int<= ( fifo_data (00) & fifo_data (01) & fifo_data (02) & fifo_data (03) &
176 
               fifo_data (04) & fifo_data (05) & fifo_data (06) & fifo_data (07) &
177 
               fifo_data (08) & fifo_data (09) & fifo_data (10) & fifo_data (11) &
178 
               fifo_data (12) & fifo_data (13) & fifo_data (14) & fifo_data (15) );
179 
 
180 
end data_flow;

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.