OpenCores
URL https://opencores.org/ocsvn/mini_aes/mini_aes/trunk

Subversion Repositories mini_aes

[/] [mini_aes/] [trunk/] [source/] [key_scheduler.vhdl] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 arif_endro
-- $Id: key_scheduler.vhdl,v 1.1.1.1 2005-12-06 02:48:32 arif_endro Exp $
2
-------------------------------------------------------------------------------
3
-- Title       : Key Scheduler calculation
4
-- Project     : Mini AES 128 
5
-------------------------------------------------------------------------------
6
-- File        : key_scheduler.vhdl
7
-- Author      : "Arif E. Nugroho" <arif_endro@yahoo.com>
8
-- Created     : 2005/12/03
9
-- Last update : 
10
-- Simulators  : ModelSim SE PLUS 6.0
11
-- Synthesizers: ISE Xilinx 6.3i
12
-- Target      : 
13
-------------------------------------------------------------------------------
14
-- Description : Key Scheduler calculation component
15
-------------------------------------------------------------------------------
16
-- Copyright (C) 2005 Arif E. Nugroho
17
-- This VHDL design file is an open design; you can redistribute it and/or
18
-- modify it and/or implement it after contacting the author
19
-------------------------------------------------------------------------------
20
-------------------------------------------------------------------------------
21
-- 
22
--         THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
23
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
24
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
25
-- ASSOCIATED DISCLAIMER.
26
-- 
27
-------------------------------------------------------------------------------
28
-- 
29
--         THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
30
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
31
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
32
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
34
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
35
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
36
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
37
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
38
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39
-- 
40
-------------------------------------------------------------------------------
41
 
42
library ieee;
43
use ieee.std_logic_1164.all;
44
use ieee.std_logic_unsigned.all;
45
 
46
entity key_scheduler is
47
 
48
  port (
49
    clock : in  std_logic;
50
    load  : in  std_logic;
51
    key_i : in  std_logic_vector (127 downto 00);
52
    key_o : out std_logic_vector (31 downto 00);
53
    done  : out std_logic
54
    );
55
 
56
end key_scheduler;
57
 
58
architecture key_expansion of key_scheduler is
59
 
60
  component bram_block_a
61
    port (
62
      clk_a_i    : in  std_logic;
63
      en_a_i     : in  std_logic;
64
      we_a_i     : in  std_logic;
65
      di_a_i     : in  std_logic_vector (07 downto 00);
66
      addr_a_1_i : in  std_logic_vector (08 downto 00);
67
      addr_a_2_i : in  std_logic_vector (08 downto 00);
68
      do_a_1_o   : out std_logic_vector (07 downto 00);
69
      do_a_2_o   : out std_logic_vector (07 downto 00)
70
      );
71
  end component;
72
--
73
  component bram_block_b
74
    port (
75
      clk_b_i    : in  std_logic;
76
      we_b_i     : in  std_logic;
77
      en_b_i     : in  std_logic;
78
      di_b_i     : in  std_logic_vector (07 downto 00);
79
      addr_b_1_i : in  std_logic_vector (08 downto 00);
80
      addr_b_2_i : in  std_logic_vector (08 downto 00);
81
      do_b_1_o   : out std_logic_vector (07 downto 00);
82
      do_b_2_o   : out std_logic_vector (07 downto 00)
83
      );
84
  end component;
85
--
86
  component counter2bit
87
    port (
88
      clock      : in  std_logic;
89
      clear      : in  std_logic;
90
      count      : out std_logic_vector (1 downto 0));
91
  end component;
92
 
93
  type state_element is array (03 downto 00) of std_logic_vector (07 downto 00);
94
 
95
  signal   clk_a_i        : std_logic;
96
  constant enc            : std_logic                       := '0';
97
  signal   en_a_i         : std_logic;
98
  signal   we_a_i         : std_logic;
99
  signal   di_a_i         : std_logic_vector (07 downto 00) := ( B"0000_0000" );
100
  signal   addr_a_1_i     : std_logic_vector (08 downto 00);
101
  signal   addr_a_2_i     : std_logic_vector (08 downto 00);
102
  signal   do_a_1_o       : std_logic_vector (07 downto 00);
103
  signal   do_a_2_o       : std_logic_vector (07 downto 00);
104
--
105
  signal   clk_b_i        : std_logic;
106
  signal   en_b_i         : std_logic;
107
  signal   we_b_i         : std_logic;
108
  signal   di_b_i         : std_logic_vector (07 downto 00) := ( B"0000_0000" );
109
  signal   addr_b_1_i     : std_logic_vector (08 downto 00);
110
  signal   addr_b_2_i     : std_logic_vector (08 downto 00);
111
  signal   do_b_1_o       : std_logic_vector (07 downto 00);
112
  signal   do_b_2_o       : std_logic_vector (07 downto 00);
113
--
114
  signal   temp           : state_element                   := ( B"00000000", B"00000000", B"00000000", B"00000000" );
115
  signal   side_opt       : state_element                   := ( B"00000000", B"00000000", B"00000000", B"00000000" );
116
  signal   result         : state_element                   := ( B"00000000", B"00000000", B"00000000", B"00000000" );
117
--
118
  signal   rot            : std_logic                       := '0';
119
  signal   count          : std_logic_vector (1 downto 0)   := ( B"00" );
120
  signal   rcon           : std_logic_vector (07 downto 00) := ( X"01" );
121
  constant round_constant : std_logic_vector (79 downto 00) := ( X"01020408_10204080_1B36");
122
  signal   rcon10x8       : std_logic_vector (79 downto 00) := ( X"01020408_10204080_1B36");
123
  signal   fifo12x8       : std_logic_vector (95 downto 00) := ( X"00000000_00000000_00000000");
124
 
125
begin
126
 
127
  clk_a_i <= clock;
128
  clk_b_i <= clock;
129
  en_a_i  <= '1';
130
  en_b_i  <= '1';
131
  we_a_i  <= '0';
132
  we_b_i  <= '0';
133
--
134
  sbox1 : bram_block_a
135
    port map (
136
      clk_a_i    => clk_a_i,
137
      en_a_i     => en_a_i,
138
      we_a_i     => we_a_i,
139
      di_a_i     => di_a_i,
140
      addr_a_1_i => addr_a_1_i,
141
      addr_a_2_i => addr_a_2_i,
142
      do_a_1_o   => do_a_1_o,
143
      do_a_2_o   => do_a_2_o
144
      );
145
--
146
  sbox2 : bram_block_b
147
    port map (
148
      clk_b_i    => clk_b_i,
149
      we_b_i     => we_b_i,
150
      en_b_i     => en_b_i,
151
      di_b_i     => di_b_i,
152
      addr_b_1_i => addr_b_1_i,
153
      addr_b_2_i => addr_b_2_i,
154
      do_b_1_o   => do_b_1_o,
155
      do_b_2_o   => do_b_2_o
156
      );
157
--
158
  rc    : counter2bit
159
    port map (
160
      clock      => clock,
161
      clear      => load,
162
      count      => count
163
      );
164
 
165
  ---------------------------------------------------------------
166
  -- key input 127 - 96 => column 0
167
  -- key input  95 - 64 => column 1
168
  -- key input  63 - 32 => column 2
169
  -- key input  31 -  0 => column 3 (root word) (shift) (subbyte)
170
  ---------------------------------------------------------------
171
 
172
  ---------------------------------------------------------------
173
  -- Round constant table
174
  --  encrypt:        decrypt:
175
  -- round 0 : 0x0100_0000   : 0x3600_0000
176
  -- round 1 : 0x0200_0000   : 0x1B00_0000
177
  -- round 2 : 0x0400_0000   : 0x8000_0000
178
  -- round 3 : 0x0800_0000   : 0x4000_0000
179
  -- round 4 : 0x1000_0000   : 0x2000_0000
180
  -- round 5 : 0x2000_0000   : 0x1000_0000
181
  -- round 6 : 0x4000_0000   : 0x0800_0000
182
  -- round 7 : 0x8000_0000   : 0x0400_0000
183
  -- round 8 : 0x1B00_0000   : 0x0200_0000
184
  -- round 9 : 0x3600_0000   : 0x0100_0000
185
  ---------------------------------------------------------------
186
 
187
  process (clock, load)
188
  begin
189
--
190
    if (load = '1') then
191
--
192
      fifo12x8 (095 downto 000) <= key_i (127 downto 032);
193
--
194
      side_opt (3)              <= key_i (031 downto 024);
195
      side_opt (2)              <= key_i (023 downto 016);
196
      side_opt (1)              <= key_i (015 downto 008);
197
      side_opt (0)              <= key_i (007 downto 000);
198
--
199
      addr_a_1_i                <= ( enc & key_i (023 downto 016) );
200
      addr_a_2_i                <= ( enc & key_i (015 downto 008) );
201
      addr_b_1_i                <= ( enc & key_i (007 downto 000) );
202
      addr_b_2_i                <= ( enc & key_i (031 downto 024) );
203
--
204
    elsif (clock = '1' and clock'event) then
205
--
206
      fifo12x8 (95 downto 32)   <= fifo12x8 (63 downto 00);
207
      fifo12x8 (31 downto 00)   <= side_opt (3) & side_opt (2) & side_opt (1) & side_opt (0);
208
--
209
      side_opt (3)              <= result(3);
210
      side_opt (2)              <= result(2);
211
      side_opt (1)              <= result(1);
212
      side_opt (0)              <= result(0);
213
--
214
      addr_a_1_i                <= ( enc & result (2) );
215
      addr_a_2_i                <= ( enc & result (1) );
216
      addr_b_1_i                <= ( enc & result (0) );
217
      addr_b_2_i                <= ( enc & result (3) );
218
--
219
    end if;
220
--
221
  end process;
222
--
223
  process (clock, load)
224
  begin
225
--
226
    if (load = '1') then
227
--
228
      rcon10x8 (79 downto 00)   <= round_constant (79 downto 00);
229
--
230
    elsif (clock = '1' and clock'event) then
231
--
232
      if (count = "10") then
233
--
234
        rcon10x8 (79 downto 08) <= rcon10x8 (71 downto 00);
235
        rcon10x8 (07 downto 00) <= rcon10x8 (79 downto 72);
236
--
237
      end if;
238
--
239
      done                      <= not(load) and count(1) and not(count(0)) and rcon(5) and rcon(4) and rcon(2) and rcon(1);
240
--
241
    end if;
242
--
243
  end process;
244
 
245
  rcon (07 downto 00)  <= rcon10x8 (79 downto 72);
246
--
247
  rot                  <= ( not(count(1)) and not(count(0)) ) when (load = '0') else '1';
248
--
249
  temp (3)             <= (do_a_1_o xor rcon)                 when (rot = '1')  else side_opt (3);
250
  temp (2)             <= (do_a_2_o)                          when (rot = '1')  else side_opt (2);
251
  temp (1)             <= (do_b_1_o)                          when (rot = '1')  else side_opt (1);
252
  temp (0)             <= (do_b_2_o)                          when (rot = '1')  else side_opt (0);
253
--
254
  result (3)           <= temp (3) xor fifo12x8 (95 downto 88);
255
  result (2)           <= temp (2) xor fifo12x8 (87 downto 80);
256
  result (1)           <= temp (1) xor fifo12x8 (79 downto 72);
257
  result (0)           <= temp (0) xor fifo12x8 (71 downto 64);
258
--
259
  key_o (31 downto 24) <= result(3);
260
  key_o (23 downto 16) <= result(2);
261
  key_o (15 downto 08) <= result(1);
262
  key_o (07 downto 00) <= result(0);
263
 
264
end key_expansion;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.