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[/] [mini_aes/] [trunk/] [source/] [key_scheduler.vhdl] - Blame information for rev 21

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1 21 arif_endro
-- ------------------------------------------------------------------------
2 15 arif_endro
-- Copyright (C) 2005 Arif Endro Nugroho
3 21 arif_endro
-- All rights reserved.
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-- 
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
8 2 arif_endro
-- 
9 21 arif_endro
-- 1. Redistributions of source code must retain the above copyright
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--    notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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--    notice, this list of conditions and the following disclaimer in the
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--    documentation and/or other materials provided with the distribution.
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-- 3. The name of Arif Endro Nugroho may not be used to endorse or promote
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--    products derived from this software without specific prior written
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--    permission.
17 2 arif_endro
-- 
18 21 arif_endro
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
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-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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-- 
30 21 arif_endro
-- End Of License.
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-- ------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity key_scheduler is
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  port (
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    clock : in  std_logic;
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    load  : in  std_logic;
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    key_i : in  std_logic_vector (127 downto 00);
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    key_o : out std_logic_vector (31 downto 00);
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    done  : out std_logic
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    );
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end key_scheduler;
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architecture key_expansion of key_scheduler is
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  component bram_block_a
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    port (
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      clk_a_i    : in  std_logic;
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      en_a_i     : in  std_logic;
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      we_a_i     : in  std_logic;
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      di_a_i     : in  std_logic_vector (07 downto 00);
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      addr_a_1_i : in  std_logic_vector (08 downto 00);
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      addr_a_2_i : in  std_logic_vector (08 downto 00);
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      do_a_1_o   : out std_logic_vector (07 downto 00);
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      do_a_2_o   : out std_logic_vector (07 downto 00)
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      );
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  end component;
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--
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  component bram_block_b
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    port (
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      clk_b_i    : in  std_logic;
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      we_b_i     : in  std_logic;
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      en_b_i     : in  std_logic;
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      di_b_i     : in  std_logic_vector (07 downto 00);
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      addr_b_1_i : in  std_logic_vector (08 downto 00);
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      addr_b_2_i : in  std_logic_vector (08 downto 00);
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      do_b_1_o   : out std_logic_vector (07 downto 00);
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      do_b_2_o   : out std_logic_vector (07 downto 00)
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      );
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  end component;
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--
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  component counter2bit
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    port (
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      clock      : in  std_logic;
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      clear      : in  std_logic;
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      count      : out std_logic_vector (1 downto 0));
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  end component;
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  type state_element is array (03 downto 00) of std_logic_vector (07 downto 00);
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  signal   clk_a_i        : std_logic;
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  constant enc            : std_logic                       := '0';
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  signal   en_a_i         : std_logic;
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  signal   we_a_i         : std_logic;
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  signal   di_a_i         : std_logic_vector (07 downto 00) := ( B"0000_0000" );
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  signal   addr_a_1_i     : std_logic_vector (08 downto 00);
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  signal   addr_a_2_i     : std_logic_vector (08 downto 00);
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  signal   do_a_1_o       : std_logic_vector (07 downto 00);
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  signal   do_a_2_o       : std_logic_vector (07 downto 00);
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--
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  signal   clk_b_i        : std_logic;
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  signal   en_b_i         : std_logic;
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  signal   we_b_i         : std_logic;
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  signal   di_b_i         : std_logic_vector (07 downto 00) := ( B"0000_0000" );
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  signal   addr_b_1_i     : std_logic_vector (08 downto 00);
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  signal   addr_b_2_i     : std_logic_vector (08 downto 00);
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  signal   do_b_1_o       : std_logic_vector (07 downto 00);
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  signal   do_b_2_o       : std_logic_vector (07 downto 00);
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--
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  signal   temp           : state_element                   := ( B"00000000", B"00000000", B"00000000", B"00000000" );
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  signal   side_opt       : state_element                   := ( B"00000000", B"00000000", B"00000000", B"00000000" );
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  signal   result         : state_element                   := ( B"00000000", B"00000000", B"00000000", B"00000000" );
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--
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  signal   rot            : std_logic                       := '0';
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  signal   count          : std_logic_vector (1 downto 0)   := ( B"00" );
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  signal   rcon           : std_logic_vector (07 downto 00) := ( X"01" );
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  constant round_constant : std_logic_vector (79 downto 00) := ( X"01020408_10204080_1B36");
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  signal   rcon10x8       : std_logic_vector (79 downto 00) := ( X"01020408_10204080_1B36");
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  signal   fifo12x8       : std_logic_vector (95 downto 00) := ( X"00000000_00000000_00000000");
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begin
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  clk_a_i <= clock;
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  clk_b_i <= clock;
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  en_a_i  <= '1';
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  en_b_i  <= '1';
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  we_a_i  <= '0';
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  we_b_i  <= '0';
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--
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  sbox1 : bram_block_a
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    port map (
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      clk_a_i    => clk_a_i,
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      en_a_i     => en_a_i,
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      we_a_i     => we_a_i,
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      di_a_i     => di_a_i,
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      addr_a_1_i => addr_a_1_i,
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      addr_a_2_i => addr_a_2_i,
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      do_a_1_o   => do_a_1_o,
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      do_a_2_o   => do_a_2_o
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      );
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--
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  sbox2 : bram_block_b
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    port map (
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      clk_b_i    => clk_b_i,
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      we_b_i     => we_b_i,
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      en_b_i     => en_b_i,
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      di_b_i     => di_b_i,
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      addr_b_1_i => addr_b_1_i,
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      addr_b_2_i => addr_b_2_i,
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      do_b_1_o   => do_b_1_o,
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      do_b_2_o   => do_b_2_o
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      );
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--
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  rc    : counter2bit
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    port map (
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      clock      => clock,
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      clear      => load,
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      count      => count
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      );
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  ---------------------------------------------------------------
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  -- key input 127 - 96 => column 0
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  -- key input  95 - 64 => column 1
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  -- key input  63 - 32 => column 2
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  -- key input  31 -  0 => column 3 (root word) (shift) (subbyte)
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  ---------------------------------------------------------------
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  ---------------------------------------------------------------
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  -- Round constant table
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  --  encrypt:        decrypt:
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  -- round 0 : 0x0100_0000   : 0x3600_0000
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  -- round 1 : 0x0200_0000   : 0x1B00_0000
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  -- round 2 : 0x0400_0000   : 0x8000_0000
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  -- round 3 : 0x0800_0000   : 0x4000_0000
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  -- round 4 : 0x1000_0000   : 0x2000_0000
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  -- round 5 : 0x2000_0000   : 0x1000_0000
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  -- round 6 : 0x4000_0000   : 0x0800_0000
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  -- round 7 : 0x8000_0000   : 0x0400_0000
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  -- round 8 : 0x1B00_0000   : 0x0200_0000
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  -- round 9 : 0x3600_0000   : 0x0100_0000
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  ---------------------------------------------------------------
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  process (clock, load)
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  begin
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--
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    if (load = '1') then
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--
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      fifo12x8 (095 downto 000) <= key_i (127 downto 032);
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--
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      side_opt (3)              <= key_i (031 downto 024);
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      side_opt (2)              <= key_i (023 downto 016);
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      side_opt (1)              <= key_i (015 downto 008);
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      side_opt (0)              <= key_i (007 downto 000);
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--
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      addr_a_1_i                <= ( enc & key_i (023 downto 016) );
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      addr_a_2_i                <= ( enc & key_i (015 downto 008) );
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      addr_b_1_i                <= ( enc & key_i (007 downto 000) );
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      addr_b_2_i                <= ( enc & key_i (031 downto 024) );
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--
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    elsif (clock = '1' and clock'event) then
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--
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      fifo12x8 (95 downto 32)   <= fifo12x8 (63 downto 00);
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      fifo12x8 (31 downto 00)   <= side_opt (3) & side_opt (2) & side_opt (1) & side_opt (0);
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--
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      side_opt (3)              <= result(3);
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      side_opt (2)              <= result(2);
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      side_opt (1)              <= result(1);
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      side_opt (0)              <= result(0);
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--
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      addr_a_1_i                <= ( enc & result (2) );
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      addr_a_2_i                <= ( enc & result (1) );
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      addr_b_1_i                <= ( enc & result (0) );
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      addr_b_2_i                <= ( enc & result (3) );
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--
210
    end if;
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--
212
  end process;
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--
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  process (clock, load)
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  begin
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--
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    if (load = '1') then
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--
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      rcon10x8 (79 downto 00)   <= round_constant (79 downto 00);
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--
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    elsif (clock = '1' and clock'event) then
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--
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      if (count = "10") then
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--
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        rcon10x8 (79 downto 08) <= rcon10x8 (71 downto 00);
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        rcon10x8 (07 downto 00) <= rcon10x8 (79 downto 72);
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--
228
      end if;
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--
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      done                      <= not(load) and count(1) and not(count(0)) and rcon(5) and rcon(4) and rcon(2) and rcon(1);
231
--
232
    end if;
233
--
234
  end process;
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236
  rcon (07 downto 00)  <= rcon10x8 (79 downto 72);
237
--
238
  rot                  <= ( not(count(1)) and not(count(0)) ) when (load = '0') else '1';
239
--
240
  temp (3)             <= (do_a_1_o xor rcon)                 when (rot = '1')  else side_opt (3);
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  temp (2)             <= (do_a_2_o)                          when (rot = '1')  else side_opt (2);
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  temp (1)             <= (do_b_1_o)                          when (rot = '1')  else side_opt (1);
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  temp (0)             <= (do_b_2_o)                          when (rot = '1')  else side_opt (0);
244
--
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  result (3)           <= temp (3) xor fifo12x8 (95 downto 88);
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  result (2)           <= temp (2) xor fifo12x8 (87 downto 80);
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  result (1)           <= temp (1) xor fifo12x8 (79 downto 72);
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  result (0)           <= temp (0) xor fifo12x8 (71 downto 64);
249
--
250
  key_o (31 downto 24) <= result(3);
251
  key_o (23 downto 16) <= result(2);
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  key_o (15 downto 08) <= result(1);
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  key_o (07 downto 00) <= result(0);
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end key_expansion;

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