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-- $Id: mini_aes.vhdl,v 1.2 2005-12-23 04:21:39 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title       : Mini AES 128
-- Project     : Mini AES 128 
-------------------------------------------------------------------------------
-- File        : mini_aes.vhdl
-- Author      : "Arif E. Nugroho" <arif_endro@yahoo.com>
-- Created     : 2005/12/03
-- Last update : 
-- Simulators  : ModelSim SE PLUS 6.0
-- Synthesizers: ISE Xilinx 6.3i
-- Target      : 
-------------------------------------------------------------------------------
-- Description : Mini AES 128 top component
-------------------------------------------------------------------------------
-- Copyright (C) 2005 Arif E. Nugroho
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- 
--         THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
-- ASSOCIATED DISCLAIMER.
-- 
-------------------------------------------------------------------------------
-- 
--         THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- 
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity mini_aes is
  port (
    clock  : in  std_logic;
    clear  : in  std_logic;
    load_i : in  std_logic;
    enc    : in  std_logic;             -- active low (e.g. 0 = encrypt, 1 = decrypt)
    key_i  : in  std_logic_vector (7 downto 0);
    data_i : in  std_logic_vector (7 downto 0);
    data_o : out std_logic_vector (7 downto 0);
    done_o : out std_logic
    );
end mini_aes;
 
architecture data_flow of mini_aes is
 
  component io_interface
    port (
      clock      : in  std_logic;
      clear      : in  std_logic;
      load_i     : in  std_logic;
      load_i_int : out std_logic;
      data_i     : in  std_logic_vector (7 downto 0);
      key_i      : in  std_logic_vector (7 downto 0);
      data_o     : out std_logic_vector (7 downto 0);
      data_o_int : in  std_logic_vector (127 downto 000);
      data_i_int : out std_logic_vector (127 downto 000);
      key_i_int  : out std_logic_vector (127 downto 000);
      done_o_int : in  std_logic;
      done_o     : out std_logic
      );
  end component;
 
  component bram_block_a
    port (
      clk_a_i     : in  std_logic;
      en_a_i      : in  std_logic;
      we_a_i      : in  std_logic;
      di_a_i      : in  std_logic_vector (07 downto 00);
      addr_a_1_i  : in  std_logic_vector (08 downto 00);
      addr_a_2_i  : in  std_logic_vector (08 downto 00);
      do_a_1_o    : out std_logic_vector (07 downto 00);
      do_a_2_o    : out std_logic_vector (07 downto 00)
      );
  end component;
--
  component bram_block_b
    port (
      clk_b_i     : in  std_logic;
      we_b_i      : in  std_logic;
      en_b_i      : in  std_logic;
      di_b_i      : in  std_logic_vector (07 downto 00);
      addr_b_1_i  : in  std_logic_vector (08 downto 00);
      addr_b_2_i  : in  std_logic_vector (08 downto 00);
      do_b_1_o    : out std_logic_vector (07 downto 00);
      do_b_2_o    : out std_logic_vector (07 downto 00)
      );
  end component;
--
  component mix_column
    port (
      s0          : in  std_logic_vector (07 downto 00);
      s1          : in  std_logic_vector (07 downto 00);
      s2          : in  std_logic_vector (07 downto 00);
      s3          : in  std_logic_vector (07 downto 00);
      mix_col     : out std_logic_vector (31 downto 00);
      inv_mix_col : out std_logic_vector (31 downto 00)
      );
  end component;
--
  component key_scheduler
    port (
      clock       : in  std_logic;
      load        : in  std_logic;
      key_i       : in  std_logic_vector (127 downto 000);
      key_o       : out std_logic_vector (031 downto 000);
      done        : out std_logic
      );
  end component;
--
  component counter2bit
    port (
      clock       : in  std_logic;
      clear       : in  std_logic;
      count       : out std_logic_vector (1 downto 0)
      );
  end component;
--
  component folded_register
    port (
      clk_i       : in  std_logic;
      enc_i       : in  std_logic;
      load_i      : in  std_logic;
      data_i      : in  std_logic_vector (127 downto 000);
      key_i       : in  std_logic_vector (127 downto 000);
      di_0_i      : in  std_logic_vector (007 downto 000);
      di_1_i      : in  std_logic_vector (007 downto 000);
      di_2_i      : in  std_logic_vector (007 downto 000);
      di_3_i      : in  std_logic_vector (007 downto 000);
      do_0_o      : out std_logic_vector (007 downto 000);
      do_1_o      : out std_logic_vector (007 downto 000);
      do_2_o      : out std_logic_vector (007 downto 000);
      do_3_o      : out std_logic_vector (007 downto 000)
      );
  end component;
 
  type state        is array (03 downto 00) of std_logic_vector (07 downto 00);
  type allround     is array (43 downto 00) of std_logic_vector (31 downto 00);
  type partialround is array (03 downto 00) of std_logic_vector (31 downto 00);
  signal   input            : state                             := ( X"00", X"00", X"00", X"00");
  signal   key_o_srl1_p     : partialround                      :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl2_p     : partialround                      :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl3_p     : partialround                      :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl4_p     : partialround                      :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl1       : allround                          :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl2       : allround                          :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl3       : allround                          :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
--
  signal   counter          : std_logic_vector (01 downto 00)     := "00";
  signal   inner_round      : std_logic                           := '0';
  signal   key_counter_up   : integer range 0 to 43;
  signal   key_counter_down : integer range 0 to 43;
  signal   done             : std_logic                           := '0';
  signal   done_decrypt     : std_logic                           := '0';
  signal   counter1bit      : std_logic                           := '0';
  signal   done_o_int       : std_logic                           := '0';
  signal   data_i_int       : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  signal   data_o_int       : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  signal   key_i_int        : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  signal   load             : std_logic                           := '0';
  signal   load_io          : std_logic                           := '0';
  signal   di_0_i           : std_logic_vector (007 downto 000);
  signal   di_1_i           : std_logic_vector (007 downto 000);
  signal   di_2_i           : std_logic_vector (007 downto 000);
  signal   di_3_i           : std_logic_vector (007 downto 000);
  signal   do_0_o           : std_logic_vector (007 downto 000);
  signal   do_1_o           : std_logic_vector (007 downto 000);
  signal   do_2_o           : std_logic_vector (007 downto 000);
  signal   do_3_o           : std_logic_vector (007 downto 000);
  signal   current_key      : std_logic_vector (031 downto 000)   := ( X"0000_0000");
  signal   output_o         : std_logic_vector (031 downto 000)   := ( X"00000000" );
  signal   output           : std_logic_vector (031 downto 000)   := ( X"00000000" );
  signal   key_o            : std_logic_vector (031 downto 000)   := ( X"00000000" );
  signal   fifo16x8         : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  signal   fifo16x8i        : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  signal   fifo16x8o        : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  signal   key_b            : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  constant GND              : std_logic                           := '0';
  constant VCC              : std_logic                           := '1';
 
  signal   mixcol_s0_i      : std_logic_vector (007 downto 000)   := B"0000_0000";
  signal   mixcol_s1_i      : std_logic_vector (007 downto 000)   := B"0000_0000";
  signal   mixcol_s2_i      : std_logic_vector (007 downto 000)   := B"0000_0000";
  signal   mixcol_s3_i      : std_logic_vector (007 downto 000)   := B"0000_0000";
  signal   mixcol_o         : std_logic_vector (031 downto 000)   := ( X"00000000" );
  signal   inv_mixcol_o     : std_logic_vector (031 downto 000)   := ( X"00000000" );
--
  signal   en_a_i           : std_logic;
  signal   en_b_i           : std_logic;
  signal   clk_a_i          : std_logic;
  signal   clk_b_i          : std_logic;
  signal   we_a_i           : std_logic;
  signal   we_b_i           : std_logic;
  signal   di_a_i           : std_logic_vector (07 downto 00)   := B"0000_0000";
  signal   di_b_i           : std_logic_vector (07 downto 00)   := B"0000_0000";
  signal   addr_a_1_i       : std_logic_vector (08 downto 00)   := B"0_0000_0000";
  signal   addr_a_2_i       : std_logic_vector (08 downto 00)   := B"0_0000_0000";
  signal   addr_b_1_i       : std_logic_vector (08 downto 00)   := B"0_0000_0000";
  signal   addr_b_2_i       : std_logic_vector (08 downto 00)   := B"0_0000_0000";
  signal   do_a_1_o         : std_logic_vector (07 downto 00);
  signal   do_a_2_o         : std_logic_vector (07 downto 00);
  signal   do_b_1_o         : std_logic_vector (07 downto 00);
  signal   do_b_2_o         : std_logic_vector (07 downto 00);
 
--signal data_i_int : std_logic_vector (127 downto 000) :=
--( X"3243F6A8_885A308D_313198A2_E0370734" );  -- PT 0
--( X"00112233_44556677_8899AABB_CCDDEEFF" );  -- PT 1
--( X"3925841D_02DC09FB_DC118597_196A0B32" );  -- CT 0
--( X"69C4E0D8_6A7B0430_D8CDB780_70B4C55A" );  -- CT 1
--signal key_i : std_logic_vector (127 downto 000) :=
--( X"2B7E1516_28AED2A6_ABF71588_09CF4F3C" );  -- KEY 0
--( X"00010203_04050607_08090A0B_0C0D0E0F" );  -- KEY 1
 
begin
 
  clk_a_i <= clock;
  clk_b_i <= clock;
  en_a_i  <= VCC;
  en_b_i  <= VCC;
  we_a_i  <= GND;
  we_b_i  <= GND;
 
  done_o_int <= done_decrypt;
 
  my_io : io_interface
    port map (
      clock      => clock,
      clear      => clear,
      load_i     => load_i,
      load_i_int => load_io,
      data_i     => data_i,
      key_i      => key_i,
      data_o     => data_o,
      data_o_int => data_o_int,
      data_i_int => data_i_int,
      key_i_int  => key_i_int,
      done_o_int => done_o_int,
      done_o     => done_o
      );
 
  sbox1     : bram_block_a
    port map (
      clk_a_i     => clk_a_i,
      en_a_i      => en_a_i,
      we_a_i      => we_a_i,
      di_a_i      => di_a_i,
      addr_a_1_i  => addr_a_1_i,
      addr_a_2_i  => addr_a_2_i,
      do_a_1_o    => do_a_1_o,
      do_a_2_o    => do_a_2_o
      );
--
  sbox2     : bram_block_b
    port map (
      clk_b_i     => clk_b_i,
      we_b_i      => we_b_i,
      en_b_i      => en_b_i,
      di_b_i      => di_b_i,
      addr_b_1_i  => addr_b_1_i,
      addr_b_2_i  => addr_b_2_i,
      do_b_1_o    => do_b_1_o,
      do_b_2_o    => do_b_2_o
      );
--
  mixcol    : mix_column
    port map (
      s0          => mixcol_s0_i,
      s1          => mixcol_s1_i,
      s2          => mixcol_s2_i,
      s3          => mixcol_s3_i,
      mix_col     => mixcol_o,
      inv_mix_col => inv_mixcol_o
      );
--
  key       : key_scheduler
    port map (
      clock       => clock,
      load        => load,
      key_i       => key_i_int,
      key_o       => key_o,
      done        => done
      );
--
  count2bit : counter2bit
    port map (
      clock       => clock,
      clear       => load,
      count       => counter
      );
--
  foldreg   : folded_register
    port map (
      clk_i       => clock,
      enc_i       => enc,
      load_i      => load,
      data_i      => data_i_int,
      key_i       => key_b,
      di_0_i      => di_0_i,
      di_1_i      => di_1_i,
      di_2_i      => di_2_i,
      di_3_i      => di_3_i,
      do_0_o      => do_0_o,
      do_1_o      => do_1_o,
      do_2_o      => do_2_o,
      do_3_o      => do_3_o
      );
 
  process(clock, clear)
  begin
    if (clear = '1') then
      load                        <= '1';
    elsif (clock = '1' and clock'event) then
      fifo16x8 (127 downto 000)   <= fifo16x8i (127 downto 000);
      if (done = '1') then
        load                      <= '1';
      else
--      load                      <= '0';
        load                      <= load_io;
      end if;
    end if;
  end process;
--
  process(clear, clock)
  begin
    if (clear = '1') then
      key_o_srl1                  <= (others => (others => '0'));
    elsif (clock = '1' and clock'event) then
      if (inner_round = '1') then
        key_o_srl1 (43 downto 00) <= key_o_srl2 (43 downto 00);
      end if;
    end if;
  end process;
--
  process(clear, clock)
  begin
    if (clear = '1') then
      key_o_srl1_p                <= (others => (others => '0'));
    elsif (clock = '1' and clock'event) then
      key_o_srl1_p (03 downto 00) <= key_o_srl2_p (03 downto 00);
    end if;
  end process;
--
  process(clear, clock)
  begin
    if (clear = '1') then
      key_o_srl3_p                <= (others => (others => '0'));
    elsif (clock = '1' and clock'event) then
      key_o_srl3_p (03 downto 00) <= key_o_srl4_p (03 downto 00);
    end if;
  end process;
 
  key_o_srl2_p (03 downto 01) <= key_o_srl1_p (02 downto 00);
  key_o_srl2_p (00)           <= key_o;
  key_o_srl4_p (02 downto 00) <= key_o_srl3_p (03 downto 01);
  key_o_srl4_p (03)           <= key_o;
--
  inner_round <= ( counter(1) and counter(0) );
--
  key_o_srl2 (39 downto 00) <= key_o_srl1 (43 downto 04);
 
  key_o_srl2 (43 downto 40) <= ( key_o_srl4_p (03), key_o_srl4_p (02), key_o_srl4_p (01), key_o_srl4_p (00) ) when ( enc = '0' ) else
                               ( key_o_srl2_p (03), key_o_srl2_p (02), key_o_srl2_p (01), key_o_srl2_p (00) );
 
  key_o_srl3 (43 downto 00) <= ( key_o_srl2 (43 downto 04) &
                                 key_i_int (127 downto 096) &
                                 key_i_int (095 downto 064) &
                                 key_i_int (063 downto 032) &
                                 key_i_int (031 downto 000)
                               ) when (done = '1') else
                                 key_o_srl3 (43 downto 00);
 
  fifo16x8o (127 downto 000) <= fifo16x8i (127 downto 000) when (done = '1') else fifo16x8o (127 downto 000);
  fifo16x8i (127 downto 000) <= ( fifo16x8 (095 downto 000) & output_o );
 
  data_o_int (127 downto 000) <= fifo16x8o (127 downto 000);
--
  input (0)               <= do_0_o;
  input (1)               <= do_1_o;
  input (2)               <= do_2_o;
  input (3)               <= do_3_o;
--
  addr_a_1_i              <= (enc & input(0));
  addr_a_2_i              <= (enc & input(1));
  addr_b_1_i              <= (enc & input(2));
  addr_b_2_i              <= (enc & input(3));
--
  mixcol_s0_i             <= do_a_1_o when (enc = '0') else output (31 downto 24);
  mixcol_s1_i             <= do_a_2_o when (enc = '0') else output (23 downto 16);
  mixcol_s2_i             <= do_b_1_o when (enc = '0') else output (15 downto 08);
  mixcol_s3_i             <= do_b_2_o when (enc = '0') else output (07 downto 00);
 
  output   <= mixcol_o xor key_o_srl3(key_counter_up) when (enc = '0') else
              (do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_down);
 
  output_o <= (do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_up) when (enc = '0') else
              (do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_down);
 
  di_0_i                 <= output (31 downto 24)  when (enc = '0') else inv_mixcol_o (31 downto 24);
  di_1_i                 <= output (23 downto 16)  when (enc = '0') else inv_mixcol_o (23 downto 16);
  di_2_i                 <= output (15 downto 08)  when (enc = '0') else inv_mixcol_o (15 downto 08);
  di_3_i                 <= output (07 downto 00)  when (enc = '0') else inv_mixcol_o (07 downto 00);
--
  key_b (127 downto 000) <= key_i_int (127 downto 000) when (enc = '0') else (key_o_srl3 (43) & key_o_srl3 (42) & key_o_srl3 (41) & key_o_srl3 (40));
 
  current_key <= key_o_srl3(key_counter_down);
 
  process (clock, load)
  begin
    if (load = '1') then
      key_counter_up     <= 4;
    elsif (clock = '1' and clock'event) then
      if (key_counter_up < 43) then
        key_counter_up   <= key_counter_up + 1;
      else
        key_counter_up   <= 4;
      end if;
    end if;
  end process;
--
  process (clock, load)
  begin
    if (load = '1') then
      key_counter_down   <= 39;
    elsif (clock = '1' and clock'event) then
      if (key_counter_down > 0) then
        key_counter_down <= key_counter_down - 1;
      else
        key_counter_down <= 39;
      end if;
    end if;
  end process;
--
  process(clear, done)
  begin
    if (clear = '1') then
      counter1bit        <= '0';
    elsif (done = '1' and done'event) then
      counter1bit        <= not (counter1bit);
    end if;
  end process;
--
  process (load, counter1bit)
  begin
    if (load = '1') then
      done_decrypt       <= '0';
    elsif (counter1bit = '0' and counter1bit'event) then
      done_decrypt       <= '1';
    end if;
  end process;
 
end data_flow;

Line No.	Rev	Author	Line
1	5	arif_endro	`-- $Id: mini_aes.vhdl,v 1.2 2005-12-23 04:21:39 arif_endro Exp $`
2	2	arif_endro	`-------------------------------------------------------------------------------`
3			`-- Title : Mini AES 128`
4			`-- Project : Mini AES 128`
5			`-------------------------------------------------------------------------------`
6			`-- File : mini_aes.vhdl`
7			`-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>`
8			`-- Created : 2005/12/03`
9			`-- Last update :`
10			`-- Simulators : ModelSim SE PLUS 6.0`
11			`-- Synthesizers: ISE Xilinx 6.3i`
12			`-- Target :`
13			`-------------------------------------------------------------------------------`
14			`-- Description : Mini AES 128 top component`
15			`-------------------------------------------------------------------------------`
16			`-- Copyright (C) 2005 Arif E. Nugroho`
17			`-- This VHDL design file is an open design; you can redistribute it and/or`
18			`-- modify it and/or implement it after contacting the author`
19			`-------------------------------------------------------------------------------`
20			`-------------------------------------------------------------------------------`
21			`--`
22			`-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION`
23			`-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT`
24			`-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE`
25			`-- ASSOCIATED DISCLAIMER.`
26			`--`
27			`-------------------------------------------------------------------------------`
28			`--`
29			-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
30			`-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF`
31			`-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO`
32			`-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,`
33			`-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,`
34			`-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;`
35			`-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,`
36			`-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR`
37			`-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF`
38			`-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
39			`--`
40			`-------------------------------------------------------------------------------`
41
42			`library ieee;`
43			`use ieee.std_logic_1164.all;`
44			`use ieee.std_logic_unsigned.all;`
45
46			`entity mini_aes is`
47			`port (`
48			`clock : in std_logic;`
49			`clear : in std_logic;`
50	5	arif_endro	`load_i : in std_logic;`
51	2	arif_endro	`enc : in std_logic; -- active low (e.g. 0 = encrypt, 1 = decrypt)`
52	5	arif_endro	`key_i : in std_logic_vector (7 downto 0);`
53			`data_i : in std_logic_vector (7 downto 0);`
54			`data_o : out std_logic_vector (7 downto 0);`
55	2	arif_endro	`done_o : out std_logic`
56			`);`
57			`end mini_aes;`
58
59			`architecture data_flow of mini_aes is`
60
61	5	arif_endro	`component io_interface`
62			`port (`
63			`clock : in std_logic;`
64			`clear : in std_logic;`
65			`load_i : in std_logic;`
66			`load_i_int : out std_logic;`
67			`data_i : in std_logic_vector (7 downto 0);`
68			`key_i : in std_logic_vector (7 downto 0);`
69			`data_o : out std_logic_vector (7 downto 0);`
70			`data_o_int : in std_logic_vector (127 downto 000);`
71			`data_i_int : out std_logic_vector (127 downto 000);`
72			`key_i_int : out std_logic_vector (127 downto 000);`
73			`done_o_int : in std_logic;`
74			`done_o : out std_logic`
75			`);`
76			`end component;`
77
78	2	arif_endro	`component bram_block_a`
79			`port (`
80			`clk_a_i : in std_logic;`
81			`en_a_i : in std_logic;`
82			`we_a_i : in std_logic;`
83			`di_a_i : in std_logic_vector (07 downto 00);`
84			`addr_a_1_i : in std_logic_vector (08 downto 00);`
85			`addr_a_2_i : in std_logic_vector (08 downto 00);`
86			`do_a_1_o : out std_logic_vector (07 downto 00);`
87			`do_a_2_o : out std_logic_vector (07 downto 00)`
88			`);`
89			`end component;`
90			`--`
91			`component bram_block_b`
92			`port (`
93			`clk_b_i : in std_logic;`
94			`we_b_i : in std_logic;`
95			`en_b_i : in std_logic;`
96			`di_b_i : in std_logic_vector (07 downto 00);`
97			`addr_b_1_i : in std_logic_vector (08 downto 00);`
98			`addr_b_2_i : in std_logic_vector (08 downto 00);`
99			`do_b_1_o : out std_logic_vector (07 downto 00);`
100			`do_b_2_o : out std_logic_vector (07 downto 00)`
101			`);`
102			`end component;`
103			`--`
104			`component mix_column`
105			`port (`
106			`s0 : in std_logic_vector (07 downto 00);`
107			`s1 : in std_logic_vector (07 downto 00);`
108			`s2 : in std_logic_vector (07 downto 00);`
109			`s3 : in std_logic_vector (07 downto 00);`
110			`mix_col : out std_logic_vector (31 downto 00);`
111			`inv_mix_col : out std_logic_vector (31 downto 00)`
112			`);`
113			`end component;`
114			`--`
115			`component key_scheduler`
116			`port (`
117			`clock : in std_logic;`
118			`load : in std_logic;`
119			`key_i : in std_logic_vector (127 downto 000);`
120			`key_o : out std_logic_vector (031 downto 000);`
121			`done : out std_logic`
122			`);`
123			`end component;`
124			`--`
125			`component counter2bit`
126			`port (`
127			`clock : in std_logic;`
128			`clear : in std_logic;`
129			`count : out std_logic_vector (1 downto 0)`
130			`);`
131			`end component;`
132			`--`
133			`component folded_register`
134			`port (`
135			`clk_i : in std_logic;`
136			`enc_i : in std_logic;`
137			`load_i : in std_logic;`
138			`data_i : in std_logic_vector (127 downto 000);`
139			`key_i : in std_logic_vector (127 downto 000);`
140			`di_0_i : in std_logic_vector (007 downto 000);`
141			`di_1_i : in std_logic_vector (007 downto 000);`
142			`di_2_i : in std_logic_vector (007 downto 000);`
143			`di_3_i : in std_logic_vector (007 downto 000);`
144			`do_0_o : out std_logic_vector (007 downto 000);`
145			`do_1_o : out std_logic_vector (007 downto 000);`
146			`do_2_o : out std_logic_vector (007 downto 000);`
147			`do_3_o : out std_logic_vector (007 downto 000)`
148			`);`
149			`end component;`
150
151			`type state is array (03 downto 00) of std_logic_vector (07 downto 00);`
152			`type allround is array (43 downto 00) of std_logic_vector (31 downto 00);`
153			`type partialround is array (03 downto 00) of std_logic_vector (31 downto 00);`
154			`signal input : state := ( X"00", X"00", X"00", X"00");`
155			`signal key_o_srl1_p : partialround :=`
156			`(`
157			`X"00000000", X"00000000", X"00000000", X"00000000"`
158			`);`
159			`signal key_o_srl2_p : partialround :=`
160			`(`
161			`X"00000000", X"00000000", X"00000000", X"00000000"`
162			`);`
163			`signal key_o_srl3_p : partialround :=`
164			`(`
165			`X"00000000", X"00000000", X"00000000", X"00000000"`
166			`);`
167			`signal key_o_srl4_p : partialround :=`
168			`(`
169			`X"00000000", X"00000000", X"00000000", X"00000000"`
170			`);`
171			`signal key_o_srl1 : allround :=`
172			`(`
173			`X"00000000", X"00000000", X"00000000", X"00000000",`
174			`X"00000000", X"00000000", X"00000000", X"00000000",`
175			`X"00000000", X"00000000", X"00000000", X"00000000",`
176			`X"00000000", X"00000000", X"00000000", X"00000000",`
177			`X"00000000", X"00000000", X"00000000", X"00000000",`
178			`X"00000000", X"00000000", X"00000000", X"00000000",`
179			`X"00000000", X"00000000", X"00000000", X"00000000",`
180			`X"00000000", X"00000000", X"00000000", X"00000000",`
181			`X"00000000", X"00000000", X"00000000", X"00000000",`
182			`X"00000000", X"00000000", X"00000000", X"00000000",`
183			`X"00000000", X"00000000", X"00000000", X"00000000"`
184			`);`
185			`signal key_o_srl2 : allround :=`
186			`(`
187			`X"00000000", X"00000000", X"00000000", X"00000000",`
188			`X"00000000", X"00000000", X"00000000", X"00000000",`
189			`X"00000000", X"00000000", X"00000000", X"00000000",`
190			`X"00000000", X"00000000", X"00000000", X"00000000",`
191			`X"00000000", X"00000000", X"00000000", X"00000000",`
192			`X"00000000", X"00000000", X"00000000", X"00000000",`
193			`X"00000000", X"00000000", X"00000000", X"00000000",`
194			`X"00000000", X"00000000", X"00000000", X"00000000",`
195			`X"00000000", X"00000000", X"00000000", X"00000000",`
196			`X"00000000", X"00000000", X"00000000", X"00000000",`
197			`X"00000000", X"00000000", X"00000000", X"00000000"`
198			`);`
199			`signal key_o_srl3 : allround :=`
200			`(`
201			`X"00000000", X"00000000", X"00000000", X"00000000",`
202			`X"00000000", X"00000000", X"00000000", X"00000000",`
203			`X"00000000", X"00000000", X"00000000", X"00000000",`
204			`X"00000000", X"00000000", X"00000000", X"00000000",`
205			`X"00000000", X"00000000", X"00000000", X"00000000",`
206			`X"00000000", X"00000000", X"00000000", X"00000000",`
207			`X"00000000", X"00000000", X"00000000", X"00000000",`
208			`X"00000000", X"00000000", X"00000000", X"00000000",`
209			`X"00000000", X"00000000", X"00000000", X"00000000",`
210			`X"00000000", X"00000000", X"00000000", X"00000000",`
211			`X"00000000", X"00000000", X"00000000", X"00000000"`
212			`);`
213			`--`
214			`signal counter : std_logic_vector (01 downto 00) := "00";`
215			`signal inner_round : std_logic := '0';`
216			`signal key_counter_up : integer range 0 to 43;`
217			`signal key_counter_down : integer range 0 to 43;`
218			`signal done : std_logic := '0';`
219			`signal done_decrypt : std_logic := '0';`
220			`signal counter1bit : std_logic := '0';`
221	5	arif_endro	`signal done_o_int : std_logic := '0';`
222			`signal data_i_int : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
223			`signal data_o_int : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
224			`signal key_i_int : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
225	2	arif_endro	`signal load : std_logic := '0';`
226	5	arif_endro	`signal load_io : std_logic := '0';`
227	2	arif_endro	`signal di_0_i : std_logic_vector (007 downto 000);`
228			`signal di_1_i : std_logic_vector (007 downto 000);`
229			`signal di_2_i : std_logic_vector (007 downto 000);`
230			`signal di_3_i : std_logic_vector (007 downto 000);`
231			`signal do_0_o : std_logic_vector (007 downto 000);`
232			`signal do_1_o : std_logic_vector (007 downto 000);`
233			`signal do_2_o : std_logic_vector (007 downto 000);`
234			`signal do_3_o : std_logic_vector (007 downto 000);`
235			`signal current_key : std_logic_vector (031 downto 000) := ( X"0000_0000");`
236			`signal output_o : std_logic_vector (031 downto 000) := ( X"00000000" );`
237			`signal output : std_logic_vector (031 downto 000) := ( X"00000000" );`
238			`signal key_o : std_logic_vector (031 downto 000) := ( X"00000000" );`
239			`signal fifo16x8 : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
240			`signal fifo16x8i : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
241			`signal fifo16x8o : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
242			`signal key_b : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
243			`constant GND : std_logic := '0';`
244			`constant VCC : std_logic := '1';`
245
246			`signal mixcol_s0_i : std_logic_vector (007 downto 000) := B"0000_0000";`
247			`signal mixcol_s1_i : std_logic_vector (007 downto 000) := B"0000_0000";`
248			`signal mixcol_s2_i : std_logic_vector (007 downto 000) := B"0000_0000";`
249			`signal mixcol_s3_i : std_logic_vector (007 downto 000) := B"0000_0000";`
250			`signal mixcol_o : std_logic_vector (031 downto 000) := ( X"00000000" );`
251			`signal inv_mixcol_o : std_logic_vector (031 downto 000) := ( X"00000000" );`
252			`--`
253			`signal en_a_i : std_logic;`
254			`signal en_b_i : std_logic;`
255			`signal clk_a_i : std_logic;`
256			`signal clk_b_i : std_logic;`
257			`signal we_a_i : std_logic;`
258			`signal we_b_i : std_logic;`
259			`signal di_a_i : std_logic_vector (07 downto 00) := B"0000_0000";`
260			`signal di_b_i : std_logic_vector (07 downto 00) := B"0000_0000";`
261			`signal addr_a_1_i : std_logic_vector (08 downto 00) := B"0_0000_0000";`
262			`signal addr_a_2_i : std_logic_vector (08 downto 00) := B"0_0000_0000";`
263			`signal addr_b_1_i : std_logic_vector (08 downto 00) := B"0_0000_0000";`
264			`signal addr_b_2_i : std_logic_vector (08 downto 00) := B"0_0000_0000";`
265			`signal do_a_1_o : std_logic_vector (07 downto 00);`
266			`signal do_a_2_o : std_logic_vector (07 downto 00);`
267			`signal do_b_1_o : std_logic_vector (07 downto 00);`
268			`signal do_b_2_o : std_logic_vector (07 downto 00);`
269
270	5	arif_endro	`--signal data_i_int : std_logic_vector (127 downto 000) :=`
271	2	arif_endro	`--( X"3243F6A8_885A308D_313198A2_E0370734" ); -- PT 0`
272			`--( X"00112233_44556677_8899AABB_CCDDEEFF" ); -- PT 1`
273			`--( X"3925841D_02DC09FB_DC118597_196A0B32" ); -- CT 0`
274			`--( X"69C4E0D8_6A7B0430_D8CDB780_70B4C55A" ); -- CT 1`
275			`--signal key_i : std_logic_vector (127 downto 000) :=`
276			`--( X"2B7E1516_28AED2A6_ABF71588_09CF4F3C" ); -- KEY 0`
277			`--( X"00010203_04050607_08090A0B_0C0D0E0F" ); -- KEY 1`
278
279			`begin`
280
281			`clk_a_i <= clock;`
282			`clk_b_i <= clock;`
283			`en_a_i <= VCC;`
284			`en_b_i <= VCC;`
285			`we_a_i <= GND;`
286			`we_b_i <= GND;`
287
288	5	arif_endro	`done_o_int <= done_decrypt;`
289	2	arif_endro
290	5	arif_endro	`my_io : io_interface`
291			`port map (`
292			`clock => clock,`
293			`clear => clear,`
294			`load_i => load_i,`
295			`load_i_int => load_io,`
296			`data_i => data_i,`
297			`key_i => key_i,`
298			`data_o => data_o,`
299			`data_o_int => data_o_int,`
300			`data_i_int => data_i_int,`
301			`key_i_int => key_i_int,`
302			`done_o_int => done_o_int,`
303			`done_o => done_o`
304			`);`
305
306	2	arif_endro	`sbox1 : bram_block_a`
307			`port map (`
308			`clk_a_i => clk_a_i,`
309			`en_a_i => en_a_i,`
310			`we_a_i => we_a_i,`
311			`di_a_i => di_a_i,`
312			`addr_a_1_i => addr_a_1_i,`
313			`addr_a_2_i => addr_a_2_i,`
314			`do_a_1_o => do_a_1_o,`
315			`do_a_2_o => do_a_2_o`
316			`);`
317			`--`
318			`sbox2 : bram_block_b`
319			`port map (`
320			`clk_b_i => clk_b_i,`
321			`we_b_i => we_b_i,`
322			`en_b_i => en_b_i,`
323			`di_b_i => di_b_i,`
324			`addr_b_1_i => addr_b_1_i,`
325			`addr_b_2_i => addr_b_2_i,`
326			`do_b_1_o => do_b_1_o,`
327			`do_b_2_o => do_b_2_o`
328			`);`
329			`--`
330			`mixcol : mix_column`
331			`port map (`
332			`s0 => mixcol_s0_i,`
333			`s1 => mixcol_s1_i,`
334			`s2 => mixcol_s2_i,`
335			`s3 => mixcol_s3_i,`
336			`mix_col => mixcol_o,`
337			`inv_mix_col => inv_mixcol_o`
338			`);`
339			`--`
340			`key : key_scheduler`
341			`port map (`
342			`clock => clock,`
343			`load => load,`
344	5	arif_endro	`key_i => key_i_int,`
345	2	arif_endro	`key_o => key_o,`
346			`done => done`
347			`);`
348			`--`
349			`count2bit : counter2bit`
350			`port map (`
351			`clock => clock,`
352			`clear => load,`
353			`count => counter`
354			`);`
355			`--`
356			`foldreg : folded_register`
357			`port map (`
358			`clk_i => clock,`
359			`enc_i => enc,`
360			`load_i => load,`
361	5	arif_endro	`data_i => data_i_int,`
362	2	arif_endro	`key_i => key_b,`
363			`di_0_i => di_0_i,`
364			`di_1_i => di_1_i,`
365			`di_2_i => di_2_i,`
366			`di_3_i => di_3_i,`
367			`do_0_o => do_0_o,`
368			`do_1_o => do_1_o,`
369			`do_2_o => do_2_o,`
370			`do_3_o => do_3_o`
371			`);`
372
373			`process(clock, clear)`
374			`begin`
375			`if (clear = '1') then`
376			`load <= '1';`
377			`elsif (clock = '1' and clock'event) then`
378			`fifo16x8 (127 downto 000) <= fifo16x8i (127 downto 000);`
379			`if (done = '1') then`
380			`load <= '1';`
381			`else`
382	5	arif_endro	`-- load <= '0';`
383			`load <= load_io;`
384	2	arif_endro	`end if;`
385			`end if;`
386			`end process;`
387			`--`
388			`process(clear, clock)`
389			`begin`
390			`if (clear = '1') then`
391			`key_o_srl1 <= (others => (others => '0'));`
392			`elsif (clock = '1' and clock'event) then`
393			`if (inner_round = '1') then`
394			`key_o_srl1 (43 downto 00) <= key_o_srl2 (43 downto 00);`
395			`end if;`
396			`end if;`
397			`end process;`
398			`--`
399			`process(clear, clock)`
400			`begin`
401			`if (clear = '1') then`
402			`key_o_srl1_p <= (others => (others => '0'));`
403			`elsif (clock = '1' and clock'event) then`
404			`key_o_srl1_p (03 downto 00) <= key_o_srl2_p (03 downto 00);`
405			`end if;`
406			`end process;`
407			`--`
408			`process(clear, clock)`
409			`begin`
410			`if (clear = '1') then`
411			`key_o_srl3_p <= (others => (others => '0'));`
412			`elsif (clock = '1' and clock'event) then`
413			`key_o_srl3_p (03 downto 00) <= key_o_srl4_p (03 downto 00);`
414			`end if;`
415			`end process;`
416
417			`key_o_srl2_p (03 downto 01) <= key_o_srl1_p (02 downto 00);`
418			`key_o_srl2_p (00) <= key_o;`
419			`key_o_srl4_p (02 downto 00) <= key_o_srl3_p (03 downto 01);`
420			`key_o_srl4_p (03) <= key_o;`
421			`--`
422			`inner_round <= ( counter(1) and counter(0) );`
423			`--`
424			`key_o_srl2 (39 downto 00) <= key_o_srl1 (43 downto 04);`
425
426			`key_o_srl2 (43 downto 40) <= ( key_o_srl4_p (03), key_o_srl4_p (02), key_o_srl4_p (01), key_o_srl4_p (00) ) when ( enc = '0' ) else`
427			`( key_o_srl2_p (03), key_o_srl2_p (02), key_o_srl2_p (01), key_o_srl2_p (00) );`
428
429			`key_o_srl3 (43 downto 00) <= ( key_o_srl2 (43 downto 04) &`
430	5	arif_endro	`key_i_int (127 downto 096) &`
431			`key_i_int (095 downto 064) &`
432			`key_i_int (063 downto 032) &`
433			`key_i_int (031 downto 000)`
434	2	arif_endro	`) when (done = '1') else`
435			`key_o_srl3 (43 downto 00);`
436
437			`fifo16x8o (127 downto 000) <= fifo16x8i (127 downto 000) when (done = '1') else fifo16x8o (127 downto 000);`
438			`fifo16x8i (127 downto 000) <= ( fifo16x8 (095 downto 000) & output_o );`
439
440	5	arif_endro	`data_o_int (127 downto 000) <= fifo16x8o (127 downto 000);`
441	2	arif_endro	`--`
442			`input (0) <= do_0_o;`
443			`input (1) <= do_1_o;`
444			`input (2) <= do_2_o;`
445			`input (3) <= do_3_o;`
446			`--`
447			`addr_a_1_i <= (enc & input(0));`
448			`addr_a_2_i <= (enc & input(1));`
449			`addr_b_1_i <= (enc & input(2));`
450			`addr_b_2_i <= (enc & input(3));`
451			`--`
452			`mixcol_s0_i <= do_a_1_o when (enc = '0') else output (31 downto 24);`
453			`mixcol_s1_i <= do_a_2_o when (enc = '0') else output (23 downto 16);`
454			`mixcol_s2_i <= do_b_1_o when (enc = '0') else output (15 downto 08);`
455			`mixcol_s3_i <= do_b_2_o when (enc = '0') else output (07 downto 00);`
456
457			`output <= mixcol_o xor key_o_srl3(key_counter_up) when (enc = '0') else`
458			`(do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_down);`
459
460			`output_o <= (do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_up) when (enc = '0') else`
461			`(do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_down);`
462
463			`di_0_i <= output (31 downto 24) when (enc = '0') else inv_mixcol_o (31 downto 24);`
464			`di_1_i <= output (23 downto 16) when (enc = '0') else inv_mixcol_o (23 downto 16);`
465			`di_2_i <= output (15 downto 08) when (enc = '0') else inv_mixcol_o (15 downto 08);`
466			`di_3_i <= output (07 downto 00) when (enc = '0') else inv_mixcol_o (07 downto 00);`
467			`--`
468	5	arif_endro	`key_b (127 downto 000) <= key_i_int (127 downto 000) when (enc = '0') else (key_o_srl3 (43) & key_o_srl3 (42) & key_o_srl3 (41) & key_o_srl3 (40));`
469	2	arif_endro
470			`current_key <= key_o_srl3(key_counter_down);`
471
472			`process (clock, load)`
473			`begin`
474			`if (load = '1') then`
475			`key_counter_up <= 4;`
476			`elsif (clock = '1' and clock'event) then`
477			`if (key_counter_up < 43) then`
478			`key_counter_up <= key_counter_up + 1;`
479			`else`
480			`key_counter_up <= 4;`
481			`end if;`
482			`end if;`
483			`end process;`
484			`--`
485			`process (clock, load)`
486			`begin`
487			`if (load = '1') then`
488			`key_counter_down <= 39;`
489			`elsif (clock = '1' and clock'event) then`
490			`if (key_counter_down > 0) then`
491			`key_counter_down <= key_counter_down - 1;`
492			`else`
493			`key_counter_down <= 39;`
494			`end if;`
495			`end if;`
496			`end process;`
497			`--`
498			`process(clear, done)`
499			`begin`
500			`if (clear = '1') then`

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