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-- $Id: mini_aes.vhdl,v 1.2 2005-12-23 04:21:39 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title       : Mini AES 128
-- Project     : Mini AES 128 
-------------------------------------------------------------------------------
-- File        : mini_aes.vhdl
-- Author      : "Arif E. Nugroho" <arif_endro@yahoo.com>
-- Created     : 2005/12/03
-- Last update : 
-- Simulators  : ModelSim SE PLUS 6.0
-- Synthesizers: ISE Xilinx 6.3i
-- Target      : 
-------------------------------------------------------------------------------
-- Description : Mini AES 128 top component
-------------------------------------------------------------------------------
-- Copyright (C) 2005 Arif Endro Nugroho
-------------------------------------------------------------------------------
-- 
--         THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
-- ASSOCIATED DISCLAIMER.
-- 
-------------------------------------------------------------------------------
-- 
--         THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- 
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity mini_aes is
  port (
    clock  : in  std_logic;
    clear  : in  std_logic;
    load_i : in  std_logic;
    enc    : in  std_logic;             -- active low (e.g. 0 = encrypt, 1 = decrypt)
    key_i  : in  std_logic_vector (7 downto 0);
    data_i : in  std_logic_vector (7 downto 0);
    data_o : out std_logic_vector (7 downto 0);
    done_o : out std_logic
    );
end mini_aes;
 
architecture data_flow of mini_aes is
 
  component io_interface
    port (
      clock      : in  std_logic;
      clear      : in  std_logic;
      load_i     : in  std_logic;
      load_i_int : out std_logic;
      data_i     : in  std_logic_vector (7 downto 0);
      key_i      : in  std_logic_vector (7 downto 0);
      data_o     : out std_logic_vector (7 downto 0);
      data_o_int : in  std_logic_vector (127 downto 000);
      data_i_int : out std_logic_vector (127 downto 000);
      key_i_int  : out std_logic_vector (127 downto 000);
      done_o_int : in  std_logic;
      done_o     : out std_logic
      );
  end component;
 
  component bram_block_a
    port (
      clk_a_i     : in  std_logic;
      en_a_i      : in  std_logic;
      we_a_i      : in  std_logic;
      di_a_i      : in  std_logic_vector (07 downto 00);
      addr_a_1_i  : in  std_logic_vector (08 downto 00);
      addr_a_2_i  : in  std_logic_vector (08 downto 00);
      do_a_1_o    : out std_logic_vector (07 downto 00);
      do_a_2_o    : out std_logic_vector (07 downto 00)
      );
  end component;
--
  component bram_block_b
    port (
      clk_b_i     : in  std_logic;
      we_b_i      : in  std_logic;
      en_b_i      : in  std_logic;
      di_b_i      : in  std_logic_vector (07 downto 00);
      addr_b_1_i  : in  std_logic_vector (08 downto 00);
      addr_b_2_i  : in  std_logic_vector (08 downto 00);
      do_b_1_o    : out std_logic_vector (07 downto 00);
      do_b_2_o    : out std_logic_vector (07 downto 00)
      );
  end component;
--
  component mix_column
    port (
      s0          : in  std_logic_vector (07 downto 00);
      s1          : in  std_logic_vector (07 downto 00);
      s2          : in  std_logic_vector (07 downto 00);
      s3          : in  std_logic_vector (07 downto 00);
      mix_col     : out std_logic_vector (31 downto 00);
      inv_mix_col : out std_logic_vector (31 downto 00)
      );
  end component;
--
  component key_scheduler
    port (
      clock       : in  std_logic;
      load        : in  std_logic;
      key_i       : in  std_logic_vector (127 downto 000);
      key_o       : out std_logic_vector (031 downto 000);
      done        : out std_logic
      );
  end component;
--
  component counter2bit
    port (
      clock       : in  std_logic;
      clear       : in  std_logic;
      count       : out std_logic_vector (1 downto 0)
      );
  end component;
--
  component folded_register
    port (
      clk_i       : in  std_logic;
      enc_i       : in  std_logic;
      load_i      : in  std_logic;
      data_i      : in  std_logic_vector (127 downto 000);
      key_i       : in  std_logic_vector (127 downto 000);
      di_0_i      : in  std_logic_vector (007 downto 000);
      di_1_i      : in  std_logic_vector (007 downto 000);
      di_2_i      : in  std_logic_vector (007 downto 000);
      di_3_i      : in  std_logic_vector (007 downto 000);
      do_0_o      : out std_logic_vector (007 downto 000);
      do_1_o      : out std_logic_vector (007 downto 000);
      do_2_o      : out std_logic_vector (007 downto 000);
      do_3_o      : out std_logic_vector (007 downto 000)
      );
  end component;
 
  type state        is array (03 downto 00) of std_logic_vector (07 downto 00);
  type allround     is array (43 downto 00) of std_logic_vector (31 downto 00);
  type partialround is array (03 downto 00) of std_logic_vector (31 downto 00);
  signal   input            : state                             := ( X"00", X"00", X"00", X"00");
  signal   key_o_srl1_p     : partialround                      :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl2_p     : partialround                      :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl3_p     : partialround                      :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl4_p     : partialround                      :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl1       : allround                          :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl2       : allround                          :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl3       : allround                          :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
--
  signal   counter          : std_logic_vector (01 downto 00)     := "00";
  signal   inner_round      : std_logic                           := '0';
  signal   key_counter_up   : integer range 0 to 43;
  signal   key_counter_down : integer range 0 to 43;
  signal   done             : std_logic                           := '0';
  signal   done_decrypt     : std_logic                           := '0';
  signal   counter1bit      : std_logic                           := '0';
  signal   done_o_int       : std_logic                           := '0';
  signal   data_i_int       : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  signal   data_o_int       : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  signal   key_i_int        : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  signal   load             : std_logic                           := '0';
  signal   load_io          : std_logic                           := '0';
  signal   di_0_i           : std_logic_vector (007 downto 000);
  signal   di_1_i           : std_logic_vector (007 downto 000);
  signal   di_2_i           : std_logic_vector (007 downto 000);
  signal   di_3_i           : std_logic_vector (007 downto 000);
  signal   do_0_o           : std_logic_vector (007 downto 000);
  signal   do_1_o           : std_logic_vector (007 downto 000);
  signal   do_2_o           : std_logic_vector (007 downto 000);
  signal   do_3_o           : std_logic_vector (007 downto 000);
  signal   current_key      : std_logic_vector (031 downto 000)   := ( X"0000_0000");
  signal   output_o         : std_logic_vector (031 downto 000)   := ( X"00000000" );
  signal   output           : std_logic_vector (031 downto 000)   := ( X"00000000" );
  signal   key_o            : std_logic_vector (031 downto 000)   := ( X"00000000" );
  signal   fifo16x8         : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  signal   fifo16x8i        : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  signal   fifo16x8o        : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  signal   key_b            : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  constant GND              : std_logic                           := '0';
  constant VCC              : std_logic                           := '1';
 
  signal   mixcol_s0_i      : std_logic_vector (007 downto 000)   := B"0000_0000";
  signal   mixcol_s1_i      : std_logic_vector (007 downto 000)   := B"0000_0000";
  signal   mixcol_s2_i      : std_logic_vector (007 downto 000)   := B"0000_0000";
  signal   mixcol_s3_i      : std_logic_vector (007 downto 000)   := B"0000_0000";
  signal   mixcol_o         : std_logic_vector (031 downto 000)   := ( X"00000000" );
  signal   inv_mixcol_o     : std_logic_vector (031 downto 000)   := ( X"00000000" );
--
  signal   en_a_i           : std_logic;
  signal   en_b_i           : std_logic;
  signal   clk_a_i          : std_logic;
  signal   clk_b_i          : std_logic;
  signal   we_a_i           : std_logic;
  signal   we_b_i           : std_logic;
  signal   di_a_i           : std_logic_vector (07 downto 00)   := B"0000_0000";
  signal   di_b_i           : std_logic_vector (07 downto 00)   := B"0000_0000";
  signal   addr_a_1_i       : std_logic_vector (08 downto 00)   := B"0_0000_0000";
  signal   addr_a_2_i       : std_logic_vector (08 downto 00)   := B"0_0000_0000";
  signal   addr_b_1_i       : std_logic_vector (08 downto 00)   := B"0_0000_0000";
  signal   addr_b_2_i       : std_logic_vector (08 downto 00)   := B"0_0000_0000";
  signal   do_a_1_o         : std_logic_vector (07 downto 00);
  signal   do_a_2_o         : std_logic_vector (07 downto 00);
  signal   do_b_1_o         : std_logic_vector (07 downto 00);
  signal   do_b_2_o         : std_logic_vector (07 downto 00);
 
--signal data_i_int : std_logic_vector (127 downto 000) :=
--( X"3243F6A8_885A308D_313198A2_E0370734" );  -- PT 0
--( X"00112233_44556677_8899AABB_CCDDEEFF" );  -- PT 1
--( X"3925841D_02DC09FB_DC118597_196A0B32" );  -- CT 0
--( X"69C4E0D8_6A7B0430_D8CDB780_70B4C55A" );  -- CT 1
--signal key_i : std_logic_vector (127 downto 000) :=
--( X"2B7E1516_28AED2A6_ABF71588_09CF4F3C" );  -- KEY 0
--( X"00010203_04050607_08090A0B_0C0D0E0F" );  -- KEY 1
 
begin
 
  clk_a_i <= clock;
  clk_b_i <= clock;
  en_a_i  <= VCC;
  en_b_i  <= VCC;
  we_a_i  <= GND;
  we_b_i  <= GND;
 
  done_o_int <= done_decrypt;
 
  my_io : io_interface
    port map (
      clock      => clock,
      clear      => clear,
      load_i     => load_i,
      load_i_int => load_io,
      data_i     => data_i,
      key_i      => key_i,
      data_o     => data_o,
      data_o_int => data_o_int,
      data_i_int => data_i_int,
      key_i_int  => key_i_int,
      done_o_int => done_o_int,
      done_o     => done_o
      );
 
  sbox1     : bram_block_a
    port map (
      clk_a_i     => clk_a_i,
      en_a_i      => en_a_i,
      we_a_i      => we_a_i,
      di_a_i      => di_a_i,
      addr_a_1_i  => addr_a_1_i,
      addr_a_2_i  => addr_a_2_i,
      do_a_1_o    => do_a_1_o,
      do_a_2_o    => do_a_2_o
      );
--
  sbox2     : bram_block_b
    port map (
      clk_b_i     => clk_b_i,
      we_b_i      => we_b_i,
      en_b_i      => en_b_i,
      di_b_i      => di_b_i,
      addr_b_1_i  => addr_b_1_i,
      addr_b_2_i  => addr_b_2_i,
      do_b_1_o    => do_b_1_o,
      do_b_2_o    => do_b_2_o
      );
--
  mixcol    : mix_column
    port map (
      s0          => mixcol_s0_i,
      s1          => mixcol_s1_i,
      s2          => mixcol_s2_i,
      s3          => mixcol_s3_i,
      mix_col     => mixcol_o,
      inv_mix_col => inv_mixcol_o
      );
--
  key       : key_scheduler
    port map (
      clock       => clock,
      load        => load,
      key_i       => key_i_int,
      key_o       => key_o,
      done        => done
      );
--
  count2bit : counter2bit
    port map (
      clock       => clock,
      clear       => load,
      count       => counter
      );
--
  foldreg   : folded_register
    port map (
      clk_i       => clock,
      enc_i       => enc,
      load_i      => load,
      data_i      => data_i_int,
      key_i       => key_b,
      di_0_i      => di_0_i,
      di_1_i      => di_1_i,
      di_2_i      => di_2_i,
      di_3_i      => di_3_i,
      do_0_o      => do_0_o,
      do_1_o      => do_1_o,
      do_2_o      => do_2_o,
      do_3_o      => do_3_o
      );
 
  process(clock, clear)
  begin
    if (clear = '1') then
      load                        <= '1';
    elsif (clock = '1' and clock'event) then
      fifo16x8 (127 downto 000)   <= fifo16x8i (127 downto 000);
      if (done = '1') then
        load                      <= '1';
      else
--      load                      <= '0';
        load                      <= load_io;
      end if;
    end if;
  end process;
--
  process(clear, clock)
  begin
    if (clear = '1') then
      key_o_srl1                  <= (others => (others => '0'));
    elsif (clock = '1' and clock'event) then
      if (inner_round = '1') then
        key_o_srl1 (43 downto 00) <= key_o_srl2 (43 downto 00);
      end if;
    end if;
  end process;
--
  process(clear, clock)
  begin
    if (clear = '1') then
      key_o_srl1_p                <= (others => (others => '0'));
    elsif (clock = '1' and clock'event) then
      key_o_srl1_p (03 downto 00) <= key_o_srl2_p (03 downto 00);
    end if;
  end process;
--
  process(clear, clock)
  begin
    if (clear = '1') then
      key_o_srl3_p                <= (others => (others => '0'));
    elsif (clock = '1' and clock'event) then
      key_o_srl3_p (03 downto 00) <= key_o_srl4_p (03 downto 00);
    end if;
  end process;
 
  key_o_srl2_p (03 downto 01) <= key_o_srl1_p (02 downto 00);
  key_o_srl2_p (00)           <= key_o;
  key_o_srl4_p (02 downto 00) <= key_o_srl3_p (03 downto 01);
  key_o_srl4_p (03)           <= key_o;
--
  inner_round <= ( counter(1) and counter(0) );
--
  key_o_srl2 (39 downto 00) <= key_o_srl1 (43 downto 04);
 
  key_o_srl2 (43 downto 40) <= ( key_o_srl4_p (03), key_o_srl4_p (02), key_o_srl4_p (01), key_o_srl4_p (00) ) when ( enc = '0' ) else
                               ( key_o_srl2_p (03), key_o_srl2_p (02), key_o_srl2_p (01), key_o_srl2_p (00) );
 
  key_o_srl3 (43 downto 00) <= ( key_o_srl2 (43 downto 04) &
                                 key_i_int (127 downto 096) &
                                 key_i_int (095 downto 064) &
                                 key_i_int (063 downto 032) &
                                 key_i_int (031 downto 000)
                               ) when (done = '1') else
                                 key_o_srl3 (43 downto 00);
 
  fifo16x8o (127 downto 000) <= fifo16x8i (127 downto 000) when (done = '1') else fifo16x8o (127 downto 000);
  fifo16x8i (127 downto 000) <= ( fifo16x8 (095 downto 000) & output_o );
 
  data_o_int (127 downto 000) <= fifo16x8o (127 downto 000);
--
  input (0)               <= do_0_o;
  input (1)               <= do_1_o;
  input (2)               <= do_2_o;
  input (3)               <= do_3_o;
--
  addr_a_1_i              <= (enc & input(0));
  addr_a_2_i              <= (enc & input(1));
  addr_b_1_i              <= (enc & input(2));
  addr_b_2_i              <= (enc & input(3));
--
  mixcol_s0_i             <= do_a_1_o when (enc = '0') else output (31 downto 24);
  mixcol_s1_i             <= do_a_2_o when (enc = '0') else output (23 downto 16);
  mixcol_s2_i             <= do_b_1_o when (enc = '0') else output (15 downto 08);
  mixcol_s3_i             <= do_b_2_o when (enc = '0') else output (07 downto 00);
 
  output   <= mixcol_o xor key_o_srl3(key_counter_up) when (enc = '0') else
              (do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_down);
 
  output_o <= (do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_up) when (enc = '0') else
              (do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_down);
 
  di_0_i                 <= output (31 downto 24)  when (enc = '0') else inv_mixcol_o (31 downto 24);
  di_1_i                 <= output (23 downto 16)  when (enc = '0') else inv_mixcol_o (23 downto 16);
  di_2_i                 <= output (15 downto 08)  when (enc = '0') else inv_mixcol_o (15 downto 08);
  di_3_i                 <= output (07 downto 00)  when (enc = '0') else inv_mixcol_o (07 downto 00);
--
  key_b (127 downto 000) <= key_i_int (127 downto 000) when (enc = '0') else (key_o_srl3 (43) & key_o_srl3 (42) & key_o_srl3 (41) & key_o_srl3 (40));
 
  current_key <= key_o_srl3(key_counter_down);
 
  process (clock, load)
  begin
    if (load = '1') then
      key_counter_up     <= 4;
    elsif (clock = '1' and clock'event) then
      if (key_counter_up < 43) then
        key_counter_up   <= key_counter_up + 1;
      else
        key_counter_up   <= 4;
      end if;
    end if;
  end process;
--
  process (clock, load)
  begin
    if (load = '1') then
      key_counter_down   <= 39;
    elsif (clock = '1' and clock'event) then
      if (key_counter_down > 0) then
        key_counter_down <= key_counter_down - 1;
      else
        key_counter_down <= 39;
      end if;
    end if;
  end process;
--
  process(clear, done)
  begin
    if (clear = '1') then
      counter1bit        <= '0';
    elsif (done = '1' and done'event) then
      counter1bit        <= not (counter1bit);
    end if;
  end process;
--
  process (load, counter1bit)
  begin
    if (load = '1') then
      done_decrypt       <= '0';
    elsif (counter1bit = '0' and counter1bit'event) then
      done_decrypt       <= '1';
    end if;
  end process;
 
end data_flow;

Line No.	Rev	Author	Line
1	5	arif_endro	`-- $Id: mini_aes.vhdl,v 1.2 2005-12-23 04:21:39 arif_endro Exp $`
2	2	arif_endro	`-------------------------------------------------------------------------------`
3			`-- Title : Mini AES 128`
4			`-- Project : Mini AES 128`
5			`-------------------------------------------------------------------------------`
6			`-- File : mini_aes.vhdl`
7			`-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>`
8			`-- Created : 2005/12/03`
9			`-- Last update :`
10			`-- Simulators : ModelSim SE PLUS 6.0`
11			`-- Synthesizers: ISE Xilinx 6.3i`
12			`-- Target :`
13			`-------------------------------------------------------------------------------`
14			`-- Description : Mini AES 128 top component`
15			`-------------------------------------------------------------------------------`
16	15	arif_endro	`-- Copyright (C) 2005 Arif Endro Nugroho`
17	2	arif_endro	`-------------------------------------------------------------------------------`
18			`--`
19			`-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION`
20			`-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT`
21			`-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE`
22			`-- ASSOCIATED DISCLAIMER.`
23			`--`
24			`-------------------------------------------------------------------------------`
25			`--`
26			-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
27			`-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF`
28			`-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO`
29			`-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,`
30			`-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,`
31			`-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;`
32			`-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,`
33			`-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR`
34			`-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF`
35			`-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
36			`--`
37			`-------------------------------------------------------------------------------`
38
39			`library ieee;`
40			`use ieee.std_logic_1164.all;`
41			`use ieee.std_logic_unsigned.all;`
42
43			`entity mini_aes is`
44			`port (`
45			`clock : in std_logic;`
46			`clear : in std_logic;`
47	5	arif_endro	`load_i : in std_logic;`
48	2	arif_endro	`enc : in std_logic; -- active low (e.g. 0 = encrypt, 1 = decrypt)`
49	5	arif_endro	`key_i : in std_logic_vector (7 downto 0);`
50			`data_i : in std_logic_vector (7 downto 0);`
51			`data_o : out std_logic_vector (7 downto 0);`
52	2	arif_endro	`done_o : out std_logic`
53			`);`
54			`end mini_aes;`
55
56			`architecture data_flow of mini_aes is`
57
58	5	arif_endro	`component io_interface`
59			`port (`
60			`clock : in std_logic;`
61			`clear : in std_logic;`
62			`load_i : in std_logic;`
63			`load_i_int : out std_logic;`
64			`data_i : in std_logic_vector (7 downto 0);`
65			`key_i : in std_logic_vector (7 downto 0);`
66			`data_o : out std_logic_vector (7 downto 0);`
67			`data_o_int : in std_logic_vector (127 downto 000);`
68			`data_i_int : out std_logic_vector (127 downto 000);`
69			`key_i_int : out std_logic_vector (127 downto 000);`
70			`done_o_int : in std_logic;`
71			`done_o : out std_logic`
72			`);`
73			`end component;`
74
75	2	arif_endro	`component bram_block_a`
76			`port (`
77			`clk_a_i : in std_logic;`
78			`en_a_i : in std_logic;`
79			`we_a_i : in std_logic;`
80			`di_a_i : in std_logic_vector (07 downto 00);`
81			`addr_a_1_i : in std_logic_vector (08 downto 00);`
82			`addr_a_2_i : in std_logic_vector (08 downto 00);`
83			`do_a_1_o : out std_logic_vector (07 downto 00);`
84			`do_a_2_o : out std_logic_vector (07 downto 00)`
85			`);`
86			`end component;`
87			`--`
88			`component bram_block_b`
89			`port (`
90			`clk_b_i : in std_logic;`
91			`we_b_i : in std_logic;`
92			`en_b_i : in std_logic;`
93			`di_b_i : in std_logic_vector (07 downto 00);`
94			`addr_b_1_i : in std_logic_vector (08 downto 00);`
95			`addr_b_2_i : in std_logic_vector (08 downto 00);`
96			`do_b_1_o : out std_logic_vector (07 downto 00);`
97			`do_b_2_o : out std_logic_vector (07 downto 00)`
98			`);`
99			`end component;`
100			`--`
101			`component mix_column`
102			`port (`
103			`s0 : in std_logic_vector (07 downto 00);`
104			`s1 : in std_logic_vector (07 downto 00);`
105			`s2 : in std_logic_vector (07 downto 00);`
106			`s3 : in std_logic_vector (07 downto 00);`
107			`mix_col : out std_logic_vector (31 downto 00);`
108			`inv_mix_col : out std_logic_vector (31 downto 00)`
109			`);`
110			`end component;`
111			`--`
112			`component key_scheduler`
113			`port (`
114			`clock : in std_logic;`
115			`load : in std_logic;`
116			`key_i : in std_logic_vector (127 downto 000);`
117			`key_o : out std_logic_vector (031 downto 000);`
118			`done : out std_logic`
119			`);`
120			`end component;`
121			`--`
122			`component counter2bit`
123			`port (`
124			`clock : in std_logic;`
125			`clear : in std_logic;`
126			`count : out std_logic_vector (1 downto 0)`
127			`);`
128			`end component;`
129			`--`
130			`component folded_register`
131			`port (`
132			`clk_i : in std_logic;`
133			`enc_i : in std_logic;`
134			`load_i : in std_logic;`
135			`data_i : in std_logic_vector (127 downto 000);`
136			`key_i : in std_logic_vector (127 downto 000);`
137			`di_0_i : in std_logic_vector (007 downto 000);`
138			`di_1_i : in std_logic_vector (007 downto 000);`
139			`di_2_i : in std_logic_vector (007 downto 000);`
140			`di_3_i : in std_logic_vector (007 downto 000);`
141			`do_0_o : out std_logic_vector (007 downto 000);`
142			`do_1_o : out std_logic_vector (007 downto 000);`
143			`do_2_o : out std_logic_vector (007 downto 000);`
144			`do_3_o : out std_logic_vector (007 downto 000)`
145			`);`
146			`end component;`
147
148			`type state is array (03 downto 00) of std_logic_vector (07 downto 00);`
149			`type allround is array (43 downto 00) of std_logic_vector (31 downto 00);`
150			`type partialround is array (03 downto 00) of std_logic_vector (31 downto 00);`
151			`signal input : state := ( X"00", X"00", X"00", X"00");`
152			`signal key_o_srl1_p : partialround :=`
153			`(`
154			`X"00000000", X"00000000", X"00000000", X"00000000"`
155			`);`
156			`signal key_o_srl2_p : partialround :=`
157			`(`
158			`X"00000000", X"00000000", X"00000000", X"00000000"`
159			`);`
160			`signal key_o_srl3_p : partialround :=`
161			`(`
162			`X"00000000", X"00000000", X"00000000", X"00000000"`
163			`);`
164			`signal key_o_srl4_p : partialround :=`
165			`(`
166			`X"00000000", X"00000000", X"00000000", X"00000000"`
167			`);`
168			`signal key_o_srl1 : allround :=`
169			`(`
170			`X"00000000", X"00000000", X"00000000", X"00000000",`
171			`X"00000000", X"00000000", X"00000000", X"00000000",`
172			`X"00000000", X"00000000", X"00000000", X"00000000",`
173			`X"00000000", X"00000000", X"00000000", X"00000000",`
174			`X"00000000", X"00000000", X"00000000", X"00000000",`
175			`X"00000000", X"00000000", X"00000000", X"00000000",`
176			`X"00000000", X"00000000", X"00000000", X"00000000",`
177			`X"00000000", X"00000000", X"00000000", X"00000000",`
178			`X"00000000", X"00000000", X"00000000", X"00000000",`
179			`X"00000000", X"00000000", X"00000000", X"00000000",`
180			`X"00000000", X"00000000", X"00000000", X"00000000"`
181			`);`
182			`signal key_o_srl2 : allround :=`
183			`(`
184			`X"00000000", X"00000000", X"00000000", X"00000000",`
185			`X"00000000", X"00000000", X"00000000", X"00000000",`
186			`X"00000000", X"00000000", X"00000000", X"00000000",`
187			`X"00000000", X"00000000", X"00000000", X"00000000",`
188			`X"00000000", X"00000000", X"00000000", X"00000000",`
189			`X"00000000", X"00000000", X"00000000", X"00000000",`
190			`X"00000000", X"00000000", X"00000000", X"00000000",`
191			`X"00000000", X"00000000", X"00000000", X"00000000",`
192			`X"00000000", X"00000000", X"00000000", X"00000000",`
193			`X"00000000", X"00000000", X"00000000", X"00000000",`
194			`X"00000000", X"00000000", X"00000000", X"00000000"`
195			`);`
196			`signal key_o_srl3 : allround :=`
197			`(`
198			`X"00000000", X"00000000", X"00000000", X"00000000",`
199			`X"00000000", X"00000000", X"00000000", X"00000000",`
200			`X"00000000", X"00000000", X"00000000", X"00000000",`
201			`X"00000000", X"00000000", X"00000000", X"00000000",`
202			`X"00000000", X"00000000", X"00000000", X"00000000",`
203			`X"00000000", X"00000000", X"00000000", X"00000000",`
204			`X"00000000", X"00000000", X"00000000", X"00000000",`
205			`X"00000000", X"00000000", X"00000000", X"00000000",`
206			`X"00000000", X"00000000", X"00000000", X"00000000",`
207			`X"00000000", X"00000000", X"00000000", X"00000000",`
208			`X"00000000", X"00000000", X"00000000", X"00000000"`
209			`);`
210			`--`
211			`signal counter : std_logic_vector (01 downto 00) := "00";`
212			`signal inner_round : std_logic := '0';`
213			`signal key_counter_up : integer range 0 to 43;`
214			`signal key_counter_down : integer range 0 to 43;`
215			`signal done : std_logic := '0';`
216			`signal done_decrypt : std_logic := '0';`
217			`signal counter1bit : std_logic := '0';`
218	5	arif_endro	`signal done_o_int : std_logic := '0';`
219			`signal data_i_int : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
220			`signal data_o_int : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
221			`signal key_i_int : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
222	2	arif_endro	`signal load : std_logic := '0';`
223	5	arif_endro	`signal load_io : std_logic := '0';`
224	2	arif_endro	`signal di_0_i : std_logic_vector (007 downto 000);`
225			`signal di_1_i : std_logic_vector (007 downto 000);`
226			`signal di_2_i : std_logic_vector (007 downto 000);`
227			`signal di_3_i : std_logic_vector (007 downto 000);`
228			`signal do_0_o : std_logic_vector (007 downto 000);`
229			`signal do_1_o : std_logic_vector (007 downto 000);`
230			`signal do_2_o : std_logic_vector (007 downto 000);`
231			`signal do_3_o : std_logic_vector (007 downto 000);`
232			`signal current_key : std_logic_vector (031 downto 000) := ( X"0000_0000");`
233			`signal output_o : std_logic_vector (031 downto 000) := ( X"00000000" );`
234			`signal output : std_logic_vector (031 downto 000) := ( X"00000000" );`
235			`signal key_o : std_logic_vector (031 downto 000) := ( X"00000000" );`
236			`signal fifo16x8 : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
237			`signal fifo16x8i : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
238			`signal fifo16x8o : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
239			`signal key_b : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
240			`constant GND : std_logic := '0';`
241			`constant VCC : std_logic := '1';`
242
243			`signal mixcol_s0_i : std_logic_vector (007 downto 000) := B"0000_0000";`
244			`signal mixcol_s1_i : std_logic_vector (007 downto 000) := B"0000_0000";`
245			`signal mixcol_s2_i : std_logic_vector (007 downto 000) := B"0000_0000";`
246			`signal mixcol_s3_i : std_logic_vector (007 downto 000) := B"0000_0000";`
247			`signal mixcol_o : std_logic_vector (031 downto 000) := ( X"00000000" );`
248			`signal inv_mixcol_o : std_logic_vector (031 downto 000) := ( X"00000000" );`
249			`--`
250			`signal en_a_i : std_logic;`
251			`signal en_b_i : std_logic;`
252			`signal clk_a_i : std_logic;`
253			`signal clk_b_i : std_logic;`
254			`signal we_a_i : std_logic;`
255			`signal we_b_i : std_logic;`
256			`signal di_a_i : std_logic_vector (07 downto 00) := B"0000_0000";`
257			`signal di_b_i : std_logic_vector (07 downto 00) := B"0000_0000";`
258			`signal addr_a_1_i : std_logic_vector (08 downto 00) := B"0_0000_0000";`
259			`signal addr_a_2_i : std_logic_vector (08 downto 00) := B"0_0000_0000";`
260			`signal addr_b_1_i : std_logic_vector (08 downto 00) := B"0_0000_0000";`
261			`signal addr_b_2_i : std_logic_vector (08 downto 00) := B"0_0000_0000";`
262			`signal do_a_1_o : std_logic_vector (07 downto 00);`
263			`signal do_a_2_o : std_logic_vector (07 downto 00);`
264			`signal do_b_1_o : std_logic_vector (07 downto 00);`
265			`signal do_b_2_o : std_logic_vector (07 downto 00);`
266
267	5	arif_endro	`--signal data_i_int : std_logic_vector (127 downto 000) :=`
268	2	arif_endro	`--( X"3243F6A8_885A308D_313198A2_E0370734" ); -- PT 0`
269			`--( X"00112233_44556677_8899AABB_CCDDEEFF" ); -- PT 1`
270			`--( X"3925841D_02DC09FB_DC118597_196A0B32" ); -- CT 0`
271			`--( X"69C4E0D8_6A7B0430_D8CDB780_70B4C55A" ); -- CT 1`
272			`--signal key_i : std_logic_vector (127 downto 000) :=`
273			`--( X"2B7E1516_28AED2A6_ABF71588_09CF4F3C" ); -- KEY 0`
274			`--( X"00010203_04050607_08090A0B_0C0D0E0F" ); -- KEY 1`
275
276			`begin`
277
278			`clk_a_i <= clock;`
279			`clk_b_i <= clock;`
280			`en_a_i <= VCC;`
281			`en_b_i <= VCC;`
282			`we_a_i <= GND;`
283			`we_b_i <= GND;`
284
285	5	arif_endro	`done_o_int <= done_decrypt;`
286	2	arif_endro
287	5	arif_endro	`my_io : io_interface`
288			`port map (`
289			`clock => clock,`
290			`clear => clear,`
291			`load_i => load_i,`
292			`load_i_int => load_io,`
293			`data_i => data_i,`
294			`key_i => key_i,`
295			`data_o => data_o,`
296			`data_o_int => data_o_int,`
297			`data_i_int => data_i_int,`
298			`key_i_int => key_i_int,`
299			`done_o_int => done_o_int,`
300			`done_o => done_o`
301			`);`
302
303	2	arif_endro	`sbox1 : bram_block_a`
304			`port map (`
305			`clk_a_i => clk_a_i,`
306			`en_a_i => en_a_i,`
307			`we_a_i => we_a_i,`
308			`di_a_i => di_a_i,`
309			`addr_a_1_i => addr_a_1_i,`
310			`addr_a_2_i => addr_a_2_i,`
311			`do_a_1_o => do_a_1_o,`
312			`do_a_2_o => do_a_2_o`
313			`);`
314			`--`
315			`sbox2 : bram_block_b`
316			`port map (`
317			`clk_b_i => clk_b_i,`
318			`we_b_i => we_b_i,`
319			`en_b_i => en_b_i,`
320			`di_b_i => di_b_i,`
321			`addr_b_1_i => addr_b_1_i,`
322			`addr_b_2_i => addr_b_2_i,`
323			`do_b_1_o => do_b_1_o,`
324			`do_b_2_o => do_b_2_o`
325			`);`
326			`--`
327			`mixcol : mix_column`
328			`port map (`
329			`s0 => mixcol_s0_i,`
330			`s1 => mixcol_s1_i,`
331			`s2 => mixcol_s2_i,`
332			`s3 => mixcol_s3_i,`
333			`mix_col => mixcol_o,`
334			`inv_mix_col => inv_mixcol_o`
335			`);`
336			`--`
337			`key : key_scheduler`
338			`port map (`
339			`clock => clock,`
340			`load => load,`
341	5	arif_endro	`key_i => key_i_int,`
342	2	arif_endro	`key_o => key_o,`
343			`done => done`
344			`);`
345			`--`
346			`count2bit : counter2bit`
347			`port map (`
348			`clock => clock,`
349			`clear => load,`
350			`count => counter`
351			`);`
352			`--`
353			`foldreg : folded_register`
354			`port map (`
355			`clk_i => clock,`
356			`enc_i => enc,`
357			`load_i => load,`
358	5	arif_endro	`data_i => data_i_int,`
359	2	arif_endro	`key_i => key_b,`
360			`di_0_i => di_0_i,`
361			`di_1_i => di_1_i,`
362			`di_2_i => di_2_i,`
363			`di_3_i => di_3_i,`
364			`do_0_o => do_0_o,`
365			`do_1_o => do_1_o,`
366			`do_2_o => do_2_o,`
367			`do_3_o => do_3_o`
368			`);`
369
370			`process(clock, clear)`
371			`begin`
372			`if (clear = '1') then`
373			`load <= '1';`
374			`elsif (clock = '1' and clock'event) then`
375			`fifo16x8 (127 downto 000) <= fifo16x8i (127 downto 000);`
376			`if (done = '1') then`
377			`load <= '1';`
378			`else`
379	5	arif_endro	`-- load <= '0';`
380			`load <= load_io;`
381	2	arif_endro	`end if;`
382			`end if;`
383			`end process;`
384			`--`
385			`process(clear, clock)`
386			`begin`
387			`if (clear = '1') then`
388			`key_o_srl1 <= (others => (others => '0'));`
389			`elsif (clock = '1' and clock'event) then`
390			`if (inner_round = '1') then`
391			`key_o_srl1 (43 downto 00) <= key_o_srl2 (43 downto 00);`
392			`end if;`
393			`end if;`
394			`end process;`
395			`--`
396			`process(clear, clock)`
397			`begin`
398			`if (clear = '1') then`
399			`key_o_srl1_p <= (others => (others => '0'));`
400			`elsif (clock = '1' and clock'event) then`
401			`key_o_srl1_p (03 downto 00) <= key_o_srl2_p (03 downto 00);`
402			`end if;`
403			`end process;`
404			`--`
405			`process(clear, clock)`
406			`begin`
407			`if (clear = '1') then`
408			`key_o_srl3_p <= (others => (others => '0'));`
409			`elsif (clock = '1' and clock'event) then`
410			`key_o_srl3_p (03 downto 00) <= key_o_srl4_p (03 downto 00);`
411			`end if;`
412			`end process;`
413
414			`key_o_srl2_p (03 downto 01) <= key_o_srl1_p (02 downto 00);`
415			`key_o_srl2_p (00) <= key_o;`
416			`key_o_srl4_p (02 downto 00) <= key_o_srl3_p (03 downto 01);`
417			`key_o_srl4_p (03) <= key_o;`
418			`--`
419			`inner_round <= ( counter(1) and counter(0) );`
420			`--`
421			`key_o_srl2 (39 downto 00) <= key_o_srl1 (43 downto 04);`
422
423			`key_o_srl2 (43 downto 40) <= ( key_o_srl4_p (03), key_o_srl4_p (02), key_o_srl4_p (01), key_o_srl4_p (00) ) when ( enc = '0' ) else`
424			`( key_o_srl2_p (03), key_o_srl2_p (02), key_o_srl2_p (01), key_o_srl2_p (00) );`
425
426			`key_o_srl3 (43 downto 00) <= ( key_o_srl2 (43 downto 04) &`
427	5	arif_endro	`key_i_int (127 downto 096) &`
428			`key_i_int (095 downto 064) &`
429			`key_i_int (063 downto 032) &`
430			`key_i_int (031 downto 000)`
431	2	arif_endro	`) when (done = '1') else`
432			`key_o_srl3 (43 downto 00);`
433
434			`fifo16x8o (127 downto 000) <= fifo16x8i (127 downto 000) when (done = '1') else fifo16x8o (127 downto 000);`
435			`fifo16x8i (127 downto 000) <= ( fifo16x8 (095 downto 000) & output_o );`
436
437	5	arif_endro	`data_o_int (127 downto 000) <= fifo16x8o (127 downto 000);`
438	2	arif_endro	`--`
439			`input (0) <= do_0_o;`
440			`input (1) <= do_1_o;`
441			`input (2) <= do_2_o;`
442			`input (3) <= do_3_o;`
443			`--`
444			`addr_a_1_i <= (enc & input(0));`
445			`addr_a_2_i <= (enc & input(1));`
446			`addr_b_1_i <= (enc & input(2));`
447			`addr_b_2_i <= (enc & input(3));`
448			`--`
449			`mixcol_s0_i <= do_a_1_o when (enc = '0') else output (31 downto 24);`
450			`mixcol_s1_i <= do_a_2_o when (enc = '0') else output (23 downto 16);`
451			`mixcol_s2_i <= do_b_1_o when (enc = '0') else output (15 downto 08);`
452			`mixcol_s3_i <= do_b_2_o when (enc = '0') else output (07 downto 00);`
453
454			`output <= mixcol_o xor key_o_srl3(key_counter_up) when (enc = '0') else`
455			`(do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_down);`
456
457			`output_o <= (do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_up) when (enc = '0') else`
458			`(do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_down);`
459
460			`di_0_i <= output (31 downto 24) when (enc = '0') else inv_mixcol_o (31 downto 24);`
461			`di_1_i <= output (23 downto 16) when (enc = '0') else inv_mixcol_o (23 downto 16);`
462			`di_2_i <= output (15 downto 08) when (enc = '0') else inv_mixcol_o (15 downto 08);`
463			`di_3_i <= output (07 downto 00) when (enc = '0') else inv_mixcol_o (07 downto 00);`
464			`--`
465	5	arif_endro	`key_b (127 downto 000) <= key_i_int (127 downto 000) when (enc = '0') else (key_o_srl3 (43) & key_o_srl3 (42) & key_o_srl3 (41) & key_o_srl3 (40));`
466	2	arif_endro
467			`current_key <= key_o_srl3(key_counter_down);`
468
469			`process (clock, load)`
470			`begin`
471			`if (load = '1') then`
472			`key_counter_up <= 4;`
473			`elsif (clock = '1' and clock'event) then`
474			`if (key_counter_up < 43) then`
475			`key_counter_up <= key_counter_up + 1;`
476			`else`
477			`key_counter_up <= 4;`
478			`end if;`
479			`end if;`
480			`end process;`
481			`--`
482			`process (clock, load)`
483			`begin`
484			`if (load = '1') then`
485			`key_counter_down <= 39;`
486			`elsif (clock = '1' and clock'event) then`
487			`if (key_counter_down > 0) then`
488			`key_counter_down <= key_counter_down - 1;`
489			`else`
490			`key_counter_down <= 39;`
491			`end if;`
492			`end if;`
493			`end process;`
494			`--`
495			`process(clear, done)`
496			`begin`
497			`if (clear = '1') then`
498			`counter1bit <= '0';`
499			`elsif (done = '1' and done'event) then`
500			`counter1bit <= not (counter1bit);`

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