URL https://opencores.org/ocsvn/mini_aes/mini_aes/trunk

Subversion Repositories mini_aes

[/] [mini_aes/] [trunk/] [source/] [mini_aes.vhdl] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log


-- $Id: mini_aes.vhdl,v 1.1.1.1 2005-12-06 02:48:33 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title       : Mini AES 128
-- Project     : Mini AES 128 
-------------------------------------------------------------------------------
-- File        : mini_aes.vhdl
-- Author      : "Arif E. Nugroho" <arif_endro@yahoo.com>
-- Created     : 2005/12/03
-- Last update : 
-- Simulators  : ModelSim SE PLUS 6.0
-- Synthesizers: ISE Xilinx 6.3i
-- Target      : 
-------------------------------------------------------------------------------
-- Description : Mini AES 128 top component
-------------------------------------------------------------------------------
-- Copyright (C) 2005 Arif E. Nugroho
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- 
--         THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
-- ASSOCIATED DISCLAIMER.
-- 
-------------------------------------------------------------------------------
-- 
--         THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- 
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity mini_aes is
  port (
    clock  : in  std_logic;
    clear  : in  std_logic;
    enc    : in  std_logic;             -- active low (e.g. 0 = encrypt, 1 = decrypt)
    key_i  : in  std_logic_vector (127 downto 00);
    data_i : in  std_logic_vector (127 downto 00);
    data_o : out std_logic_vector (127 downto 00);
    done_o : out std_logic
    );
end mini_aes;
 
architecture data_flow of mini_aes is
 
  component bram_block_a
    port (
      clk_a_i     : in  std_logic;
      en_a_i      : in  std_logic;
      we_a_i      : in  std_logic;
      di_a_i      : in  std_logic_vector (07 downto 00);
      addr_a_1_i  : in  std_logic_vector (08 downto 00);
      addr_a_2_i  : in  std_logic_vector (08 downto 00);
      do_a_1_o    : out std_logic_vector (07 downto 00);
      do_a_2_o    : out std_logic_vector (07 downto 00)
      );
  end component;
--
  component bram_block_b
    port (
      clk_b_i     : in  std_logic;
      we_b_i      : in  std_logic;
      en_b_i      : in  std_logic;
      di_b_i      : in  std_logic_vector (07 downto 00);
      addr_b_1_i  : in  std_logic_vector (08 downto 00);
      addr_b_2_i  : in  std_logic_vector (08 downto 00);
      do_b_1_o    : out std_logic_vector (07 downto 00);
      do_b_2_o    : out std_logic_vector (07 downto 00)
      );
  end component;
--
  component mix_column
    port (
      s0          : in  std_logic_vector (07 downto 00);
      s1          : in  std_logic_vector (07 downto 00);
      s2          : in  std_logic_vector (07 downto 00);
      s3          : in  std_logic_vector (07 downto 00);
      mix_col     : out std_logic_vector (31 downto 00);
      inv_mix_col : out std_logic_vector (31 downto 00)
      );
  end component;
--
  component key_scheduler
    port (
      clock       : in  std_logic;
      load        : in  std_logic;
      key_i       : in  std_logic_vector (127 downto 000);
      key_o       : out std_logic_vector (031 downto 000);
      done        : out std_logic
      );
  end component;
--
  component counter2bit
    port (
      clock       : in  std_logic;
      clear       : in  std_logic;
      count       : out std_logic_vector (1 downto 0)
      );
  end component;
--
  component folded_register
    port (
      clk_i       : in  std_logic;
      enc_i       : in  std_logic;
      load_i      : in  std_logic;
      data_i      : in  std_logic_vector (127 downto 000);
      key_i       : in  std_logic_vector (127 downto 000);
      di_0_i      : in  std_logic_vector (007 downto 000);
      di_1_i      : in  std_logic_vector (007 downto 000);
      di_2_i      : in  std_logic_vector (007 downto 000);
      di_3_i      : in  std_logic_vector (007 downto 000);
      do_0_o      : out std_logic_vector (007 downto 000);
      do_1_o      : out std_logic_vector (007 downto 000);
      do_2_o      : out std_logic_vector (007 downto 000);
      do_3_o      : out std_logic_vector (007 downto 000)
      );
  end component;
 
  type state        is array (03 downto 00) of std_logic_vector (07 downto 00);
  type allround     is array (43 downto 00) of std_logic_vector (31 downto 00);
  type partialround is array (03 downto 00) of std_logic_vector (31 downto 00);
  signal   input            : state                             := ( X"00", X"00", X"00", X"00");
  signal   key_o_srl1_p     : partialround                      :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl2_p     : partialround                      :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl3_p     : partialround                      :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl4_p     : partialround                      :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl1       : allround                          :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl2       : allround                          :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl3       : allround                          :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
--
  signal   counter          : std_logic_vector (01 downto 00)     := "00";
  signal   inner_round      : std_logic                           := '0';
  signal   key_counter_up   : integer range 0 to 43;
  signal   key_counter_down : integer range 0 to 43;
  signal   done             : std_logic                           := '0';
  signal   done_decrypt     : std_logic                           := '0';
  signal   counter1bit      : std_logic                           := '0';
  signal   load             : std_logic                           := '0';
  signal   di_0_i           : std_logic_vector (007 downto 000);
  signal   di_1_i           : std_logic_vector (007 downto 000);
  signal   di_2_i           : std_logic_vector (007 downto 000);
  signal   di_3_i           : std_logic_vector (007 downto 000);
  signal   do_0_o           : std_logic_vector (007 downto 000);
  signal   do_1_o           : std_logic_vector (007 downto 000);
  signal   do_2_o           : std_logic_vector (007 downto 000);
  signal   do_3_o           : std_logic_vector (007 downto 000);
  signal   current_key      : std_logic_vector (031 downto 000)   := ( X"0000_0000");
  signal   output_o         : std_logic_vector (031 downto 000)   := ( X"00000000" );
  signal   output           : std_logic_vector (031 downto 000)   := ( X"00000000" );
  signal   key_o            : std_logic_vector (031 downto 000)   := ( X"00000000" );
  signal   fifo16x8         : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  signal   fifo16x8i        : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  signal   fifo16x8o        : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  signal   key_b            : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  constant GND              : std_logic                           := '0';
  constant VCC              : std_logic                           := '1';
 
  signal   mixcol_s0_i      : std_logic_vector (007 downto 000)   := B"0000_0000";
  signal   mixcol_s1_i      : std_logic_vector (007 downto 000)   := B"0000_0000";
  signal   mixcol_s2_i      : std_logic_vector (007 downto 000)   := B"0000_0000";
  signal   mixcol_s3_i      : std_logic_vector (007 downto 000)   := B"0000_0000";
  signal   mixcol_o         : std_logic_vector (031 downto 000)   := ( X"00000000" );
  signal   inv_mixcol_o     : std_logic_vector (031 downto 000)   := ( X"00000000" );
--
  signal   en_a_i           : std_logic;
  signal   en_b_i           : std_logic;
  signal   clk_a_i          : std_logic;
  signal   clk_b_i          : std_logic;
  signal   we_a_i           : std_logic;
  signal   we_b_i           : std_logic;
  signal   di_a_i           : std_logic_vector (07 downto 00)   := B"0000_0000";
  signal   di_b_i           : std_logic_vector (07 downto 00)   := B"0000_0000";
  signal   addr_a_1_i       : std_logic_vector (08 downto 00)   := B"0_0000_0000";
  signal   addr_a_2_i       : std_logic_vector (08 downto 00)   := B"0_0000_0000";
  signal   addr_b_1_i       : std_logic_vector (08 downto 00)   := B"0_0000_0000";
  signal   addr_b_2_i       : std_logic_vector (08 downto 00)   := B"0_0000_0000";
  signal   do_a_1_o         : std_logic_vector (07 downto 00);
  signal   do_a_2_o         : std_logic_vector (07 downto 00);
  signal   do_b_1_o         : std_logic_vector (07 downto 00);
  signal   do_b_2_o         : std_logic_vector (07 downto 00);
 
--signal data_i : std_logic_vector (127 downto 000) :=
--( X"3243F6A8_885A308D_313198A2_E0370734" );  -- PT 0
--( X"00112233_44556677_8899AABB_CCDDEEFF" );  -- PT 1
--( X"3925841D_02DC09FB_DC118597_196A0B32" );  -- CT 0
--( X"69C4E0D8_6A7B0430_D8CDB780_70B4C55A" );  -- CT 1
--signal key_i : std_logic_vector (127 downto 000) :=
--( X"2B7E1516_28AED2A6_ABF71588_09CF4F3C" );  -- KEY 0
--( X"00010203_04050607_08090A0B_0C0D0E0F" );  -- KEY 1
 
begin
 
  clk_a_i <= clock;
  clk_b_i <= clock;
  en_a_i  <= VCC;
  en_b_i  <= VCC;
  we_a_i  <= GND;
  we_b_i  <= GND;
 
  done_o <= done_decrypt;
 
  sbox1     : bram_block_a
    port map (
      clk_a_i     => clk_a_i,
      en_a_i      => en_a_i,
      we_a_i      => we_a_i,
      di_a_i      => di_a_i,
      addr_a_1_i  => addr_a_1_i,
      addr_a_2_i  => addr_a_2_i,
      do_a_1_o    => do_a_1_o,
      do_a_2_o    => do_a_2_o
      );
--
  sbox2     : bram_block_b
    port map (
      clk_b_i     => clk_b_i,
      we_b_i      => we_b_i,
      en_b_i      => en_b_i,
      di_b_i      => di_b_i,
      addr_b_1_i  => addr_b_1_i,
      addr_b_2_i  => addr_b_2_i,
      do_b_1_o    => do_b_1_o,
      do_b_2_o    => do_b_2_o
      );
--
  mixcol    : mix_column
    port map (
      s0          => mixcol_s0_i,
      s1          => mixcol_s1_i,
      s2          => mixcol_s2_i,
      s3          => mixcol_s3_i,
      mix_col     => mixcol_o,
      inv_mix_col => inv_mixcol_o
      );
--
  key       : key_scheduler
    port map (
      clock       => clock,
      load        => load,
      key_i       => key_i,
      key_o       => key_o,
      done        => done
      );
--
  count2bit : counter2bit
    port map (
      clock       => clock,
      clear       => load,
      count       => counter
      );
--
  foldreg   : folded_register
    port map (
      clk_i       => clock,
      enc_i       => enc,
      load_i      => load,
      data_i      => data_i,
      key_i       => key_b,
      di_0_i      => di_0_i,
      di_1_i      => di_1_i,
      di_2_i      => di_2_i,
      di_3_i      => di_3_i,
      do_0_o      => do_0_o,
      do_1_o      => do_1_o,
      do_2_o      => do_2_o,
      do_3_o      => do_3_o
      );
 
  process(clock, clear)
  begin
    if (clear = '1') then
      load                        <= '1';
    elsif (clock = '1' and clock'event) then
      fifo16x8 (127 downto 000)   <= fifo16x8i (127 downto 000);
      if (done = '1') then
        load                      <= '1';
      else
        load                      <= '0';
      end if;
    end if;
  end process;
--
  process(clear, clock)
  begin
    if (clear = '1') then
      key_o_srl1                  <= (others => (others => '0'));
    elsif (clock = '1' and clock'event) then
      if (inner_round = '1') then
        key_o_srl1 (43 downto 00) <= key_o_srl2 (43 downto 00);
      end if;
    end if;
  end process;
--
  process(clear, clock)
  begin
    if (clear = '1') then
      key_o_srl1_p                <= (others => (others => '0'));
    elsif (clock = '1' and clock'event) then
      key_o_srl1_p (03 downto 00) <= key_o_srl2_p (03 downto 00);
    end if;
  end process;
--
  process(clear, clock)
  begin
    if (clear = '1') then
      key_o_srl3_p                <= (others => (others => '0'));
    elsif (clock = '1' and clock'event) then
      key_o_srl3_p (03 downto 00) <= key_o_srl4_p (03 downto 00);
    end if;
  end process;
 
  key_o_srl2_p (03 downto 01) <= key_o_srl1_p (02 downto 00);
  key_o_srl2_p (00)           <= key_o;
  key_o_srl4_p (02 downto 00) <= key_o_srl3_p (03 downto 01);
  key_o_srl4_p (03)           <= key_o;
--
  inner_round <= ( counter(1) and counter(0) );
--
  key_o_srl2 (39 downto 00) <= key_o_srl1 (43 downto 04);
 
  key_o_srl2 (43 downto 40) <= ( key_o_srl4_p (03), key_o_srl4_p (02), key_o_srl4_p (01), key_o_srl4_p (00) ) when ( enc = '0' ) else
                               ( key_o_srl2_p (03), key_o_srl2_p (02), key_o_srl2_p (01), key_o_srl2_p (00) );
 
  key_o_srl3 (43 downto 00) <= ( key_o_srl2 (43 downto 04) &
                                 key_i (127 downto 096) &
                                 key_i (095 downto 064) &
                                 key_i (063 downto 032) &
                                 key_i (031 downto 000)
                               ) when (done = '1') else
                                 key_o_srl3 (43 downto 00);
 
  fifo16x8o (127 downto 000) <= fifo16x8i (127 downto 000) when (done = '1') else fifo16x8o (127 downto 000);
  fifo16x8i (127 downto 000) <= ( fifo16x8 (095 downto 000) & output_o );
 
  data_o (127 downto 000) <= fifo16x8o (127 downto 000);
--
  input (0)               <= do_0_o;
  input (1)               <= do_1_o;
  input (2)               <= do_2_o;
  input (3)               <= do_3_o;
--
  addr_a_1_i              <= (enc & input(0));
  addr_a_2_i              <= (enc & input(1));
  addr_b_1_i              <= (enc & input(2));
  addr_b_2_i              <= (enc & input(3));
--
  mixcol_s0_i             <= do_a_1_o when (enc = '0') else output (31 downto 24);
  mixcol_s1_i             <= do_a_2_o when (enc = '0') else output (23 downto 16);
  mixcol_s2_i             <= do_b_1_o when (enc = '0') else output (15 downto 08);
  mixcol_s3_i             <= do_b_2_o when (enc = '0') else output (07 downto 00);
 
  output   <= mixcol_o xor key_o_srl3(key_counter_up) when (enc = '0') else
              (do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_down);
 
  output_o <= (do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_up) when (enc = '0') else
              (do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_down);
 
  di_0_i                 <= output (31 downto 24)  when (enc = '0') else inv_mixcol_o (31 downto 24);
  di_1_i                 <= output (23 downto 16)  when (enc = '0') else inv_mixcol_o (23 downto 16);
  di_2_i                 <= output (15 downto 08)  when (enc = '0') else inv_mixcol_o (15 downto 08);
  di_3_i                 <= output (07 downto 00)  when (enc = '0') else inv_mixcol_o (07 downto 00);
--
  key_b (127 downto 000) <= key_i (127 downto 000) when (enc = '0') else (key_o_srl3 (43) & key_o_srl3 (42) & key_o_srl3 (41) & key_o_srl3 (40));
 
  current_key <= key_o_srl3(key_counter_down);
 
  process (clock, load)
  begin
    if (load = '1') then
      key_counter_up     <= 4;
    elsif (clock = '1' and clock'event) then
      if (key_counter_up < 43) then
        key_counter_up   <= key_counter_up + 1;
      else
        key_counter_up   <= 4;
      end if;
    end if;
  end process;
--
  process (clock, load)
  begin
    if (load = '1') then
      key_counter_down   <= 39;
    elsif (clock = '1' and clock'event) then
      if (key_counter_down > 0) then
        key_counter_down <= key_counter_down - 1;
      else
        key_counter_down <= 39;
      end if;
    end if;
  end process;
--
  process(clear, done)
  begin
    if (clear = '1') then
      counter1bit        <= '0';
    elsif (done = '1' and done'event) then
      counter1bit        <= not (counter1bit);
    end if;
  end process;
--
  process (load, counter1bit)
  begin
    if (load = '1') then
      done_decrypt       <= '0';
    elsif (counter1bit = '0' and counter1bit'event) then
      done_decrypt       <= '1';
    end if;
  end process;
 
end data_flow;

Browse

Tools

Subversion Repositories mini_aes

[/] [mini_aes/] [trunk/] [source/] [mini_aes.vhdl] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	arif_endro	`-- $Id: mini_aes.vhdl,v 1.1.1.1 2005-12-06 02:48:33 arif_endro Exp $`
2			`-------------------------------------------------------------------------------`
3			`-- Title : Mini AES 128`
4			`-- Project : Mini AES 128`
5			`-------------------------------------------------------------------------------`
6			`-- File : mini_aes.vhdl`
7			`-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>`
8			`-- Created : 2005/12/03`
9			`-- Last update :`
10			`-- Simulators : ModelSim SE PLUS 6.0`
11			`-- Synthesizers: ISE Xilinx 6.3i`
12			`-- Target :`
13			`-------------------------------------------------------------------------------`
14			`-- Description : Mini AES 128 top component`
15			`-------------------------------------------------------------------------------`
16			`-- Copyright (C) 2005 Arif E. Nugroho`
17			`-- This VHDL design file is an open design; you can redistribute it and/or`
18			`-- modify it and/or implement it after contacting the author`
19			`-------------------------------------------------------------------------------`
20			`-------------------------------------------------------------------------------`
21			`--`
22			`-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION`
23			`-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT`
24			`-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE`
25			`-- ASSOCIATED DISCLAIMER.`
26			`--`
27			`-------------------------------------------------------------------------------`
28			`--`
29			-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
30			`-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF`
31			`-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO`
32			`-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,`
33			`-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,`
34			`-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;`
35			`-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,`
36			`-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR`
37			`-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF`
38			`-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
39			`--`
40			`-------------------------------------------------------------------------------`
41
42			`library ieee;`
43			`use ieee.std_logic_1164.all;`
44			`use ieee.std_logic_unsigned.all;`
45
46			`entity mini_aes is`
47			`port (`
48			`clock : in std_logic;`
49			`clear : in std_logic;`
50			`enc : in std_logic; -- active low (e.g. 0 = encrypt, 1 = decrypt)`
51			`key_i : in std_logic_vector (127 downto 00);`
52			`data_i : in std_logic_vector (127 downto 00);`
53			`data_o : out std_logic_vector (127 downto 00);`
54			`done_o : out std_logic`
55			`);`
56			`end mini_aes;`
57
58			`architecture data_flow of mini_aes is`
59
60			`component bram_block_a`
61			`port (`
62			`clk_a_i : in std_logic;`
63			`en_a_i : in std_logic;`
64			`we_a_i : in std_logic;`
65			`di_a_i : in std_logic_vector (07 downto 00);`
66			`addr_a_1_i : in std_logic_vector (08 downto 00);`
67			`addr_a_2_i : in std_logic_vector (08 downto 00);`
68			`do_a_1_o : out std_logic_vector (07 downto 00);`
69			`do_a_2_o : out std_logic_vector (07 downto 00)`
70			`);`
71			`end component;`
72			`--`
73			`component bram_block_b`
74			`port (`
75			`clk_b_i : in std_logic;`
76			`we_b_i : in std_logic;`
77			`en_b_i : in std_logic;`
78			`di_b_i : in std_logic_vector (07 downto 00);`
79			`addr_b_1_i : in std_logic_vector (08 downto 00);`
80			`addr_b_2_i : in std_logic_vector (08 downto 00);`
81			`do_b_1_o : out std_logic_vector (07 downto 00);`
82			`do_b_2_o : out std_logic_vector (07 downto 00)`
83			`);`
84			`end component;`
85			`--`
86			`component mix_column`
87			`port (`
88			`s0 : in std_logic_vector (07 downto 00);`
89			`s1 : in std_logic_vector (07 downto 00);`
90			`s2 : in std_logic_vector (07 downto 00);`
91			`s3 : in std_logic_vector (07 downto 00);`
92			`mix_col : out std_logic_vector (31 downto 00);`
93			`inv_mix_col : out std_logic_vector (31 downto 00)`
94			`);`
95			`end component;`
96			`--`
97			`component key_scheduler`
98			`port (`
99			`clock : in std_logic;`
100			`load : in std_logic;`
101			`key_i : in std_logic_vector (127 downto 000);`
102			`key_o : out std_logic_vector (031 downto 000);`
103			`done : out std_logic`
104			`);`
105			`end component;`
106			`--`
107			`component counter2bit`
108			`port (`
109			`clock : in std_logic;`
110			`clear : in std_logic;`
111			`count : out std_logic_vector (1 downto 0)`
112			`);`
113			`end component;`
114			`--`
115			`component folded_register`
116			`port (`
117			`clk_i : in std_logic;`
118			`enc_i : in std_logic;`
119			`load_i : in std_logic;`
120			`data_i : in std_logic_vector (127 downto 000);`
121			`key_i : in std_logic_vector (127 downto 000);`
122			`di_0_i : in std_logic_vector (007 downto 000);`
123			`di_1_i : in std_logic_vector (007 downto 000);`
124			`di_2_i : in std_logic_vector (007 downto 000);`
125			`di_3_i : in std_logic_vector (007 downto 000);`
126			`do_0_o : out std_logic_vector (007 downto 000);`
127			`do_1_o : out std_logic_vector (007 downto 000);`
128			`do_2_o : out std_logic_vector (007 downto 000);`
129			`do_3_o : out std_logic_vector (007 downto 000)`
130			`);`
131			`end component;`
132
133			`type state is array (03 downto 00) of std_logic_vector (07 downto 00);`
134			`type allround is array (43 downto 00) of std_logic_vector (31 downto 00);`
135			`type partialround is array (03 downto 00) of std_logic_vector (31 downto 00);`
136			`signal input : state := ( X"00", X"00", X"00", X"00");`
137			`signal key_o_srl1_p : partialround :=`
138			`(`
139			`X"00000000", X"00000000", X"00000000", X"00000000"`
140			`);`
141			`signal key_o_srl2_p : partialround :=`
142			`(`
143			`X"00000000", X"00000000", X"00000000", X"00000000"`
144			`);`
145			`signal key_o_srl3_p : partialround :=`
146			`(`
147			`X"00000000", X"00000000", X"00000000", X"00000000"`
148			`);`
149			`signal key_o_srl4_p : partialround :=`
150			`(`
151			`X"00000000", X"00000000", X"00000000", X"00000000"`
152			`);`
153			`signal key_o_srl1 : allround :=`
154			`(`
155			`X"00000000", X"00000000", X"00000000", X"00000000",`
156			`X"00000000", X"00000000", X"00000000", X"00000000",`
157			`X"00000000", X"00000000", X"00000000", X"00000000",`
158			`X"00000000", X"00000000", X"00000000", X"00000000",`
159			`X"00000000", X"00000000", X"00000000", X"00000000",`
160			`X"00000000", X"00000000", X"00000000", X"00000000",`
161			`X"00000000", X"00000000", X"00000000", X"00000000",`
162			`X"00000000", X"00000000", X"00000000", X"00000000",`
163			`X"00000000", X"00000000", X"00000000", X"00000000",`
164			`X"00000000", X"00000000", X"00000000", X"00000000",`
165			`X"00000000", X"00000000", X"00000000", X"00000000"`
166			`);`
167			`signal key_o_srl2 : allround :=`
168			`(`
169			`X"00000000", X"00000000", X"00000000", X"00000000",`
170			`X"00000000", X"00000000", X"00000000", X"00000000",`
171			`X"00000000", X"00000000", X"00000000", X"00000000",`
172			`X"00000000", X"00000000", X"00000000", X"00000000",`
173			`X"00000000", X"00000000", X"00000000", X"00000000",`
174			`X"00000000", X"00000000", X"00000000", X"00000000",`
175			`X"00000000", X"00000000", X"00000000", X"00000000",`
176			`X"00000000", X"00000000", X"00000000", X"00000000",`
177			`X"00000000", X"00000000", X"00000000", X"00000000",`
178			`X"00000000", X"00000000", X"00000000", X"00000000",`
179			`X"00000000", X"00000000", X"00000000", X"00000000"`
180			`);`
181			`signal key_o_srl3 : allround :=`
182			`(`
183			`X"00000000", X"00000000", X"00000000", X"00000000",`
184			`X"00000000", X"00000000", X"00000000", X"00000000",`
185			`X"00000000", X"00000000", X"00000000", X"00000000",`
186			`X"00000000", X"00000000", X"00000000", X"00000000",`
187			`X"00000000", X"00000000", X"00000000", X"00000000",`
188			`X"00000000", X"00000000", X"00000000", X"00000000",`
189			`X"00000000", X"00000000", X"00000000", X"00000000",`
190			`X"00000000", X"00000000", X"00000000", X"00000000",`
191			`X"00000000", X"00000000", X"00000000", X"00000000",`
192			`X"00000000", X"00000000", X"00000000", X"00000000",`
193			`X"00000000", X"00000000", X"00000000", X"00000000"`
194			`);`
195			`--`
196			`signal counter : std_logic_vector (01 downto 00) := "00";`
197			`signal inner_round : std_logic := '0';`
198			`signal key_counter_up : integer range 0 to 43;`
199			`signal key_counter_down : integer range 0 to 43;`
200			`signal done : std_logic := '0';`
201			`signal done_decrypt : std_logic := '0';`
202			`signal counter1bit : std_logic := '0';`
203			`signal load : std_logic := '0';`
204			`signal di_0_i : std_logic_vector (007 downto 000);`
205			`signal di_1_i : std_logic_vector (007 downto 000);`
206			`signal di_2_i : std_logic_vector (007 downto 000);`
207			`signal di_3_i : std_logic_vector (007 downto 000);`
208			`signal do_0_o : std_logic_vector (007 downto 000);`
209			`signal do_1_o : std_logic_vector (007 downto 000);`
210			`signal do_2_o : std_logic_vector (007 downto 000);`
211			`signal do_3_o : std_logic_vector (007 downto 000);`
212			`signal current_key : std_logic_vector (031 downto 000) := ( X"0000_0000");`
213			`signal output_o : std_logic_vector (031 downto 000) := ( X"00000000" );`
214			`signal output : std_logic_vector (031 downto 000) := ( X"00000000" );`
215			`signal key_o : std_logic_vector (031 downto 000) := ( X"00000000" );`
216			`signal fifo16x8 : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
217			`signal fifo16x8i : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
218			`signal fifo16x8o : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
219			`signal key_b : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
220			`constant GND : std_logic := '0';`
221			`constant VCC : std_logic := '1';`
222
223			`signal mixcol_s0_i : std_logic_vector (007 downto 000) := B"0000_0000";`
224			`signal mixcol_s1_i : std_logic_vector (007 downto 000) := B"0000_0000";`
225			`signal mixcol_s2_i : std_logic_vector (007 downto 000) := B"0000_0000";`
226			`signal mixcol_s3_i : std_logic_vector (007 downto 000) := B"0000_0000";`
227			`signal mixcol_o : std_logic_vector (031 downto 000) := ( X"00000000" );`
228			`signal inv_mixcol_o : std_logic_vector (031 downto 000) := ( X"00000000" );`
229			`--`
230			`signal en_a_i : std_logic;`
231			`signal en_b_i : std_logic;`
232			`signal clk_a_i : std_logic;`
233			`signal clk_b_i : std_logic;`
234			`signal we_a_i : std_logic;`
235			`signal we_b_i : std_logic;`
236			`signal di_a_i : std_logic_vector (07 downto 00) := B"0000_0000";`
237			`signal di_b_i : std_logic_vector (07 downto 00) := B"0000_0000";`
238			`signal addr_a_1_i : std_logic_vector (08 downto 00) := B"0_0000_0000";`
239			`signal addr_a_2_i : std_logic_vector (08 downto 00) := B"0_0000_0000";`
240			`signal addr_b_1_i : std_logic_vector (08 downto 00) := B"0_0000_0000";`
241			`signal addr_b_2_i : std_logic_vector (08 downto 00) := B"0_0000_0000";`
242			`signal do_a_1_o : std_logic_vector (07 downto 00);`
243			`signal do_a_2_o : std_logic_vector (07 downto 00);`
244			`signal do_b_1_o : std_logic_vector (07 downto 00);`
245			`signal do_b_2_o : std_logic_vector (07 downto 00);`
246
247			`--signal data_i : std_logic_vector (127 downto 000) :=`
248			`--( X"3243F6A8_885A308D_313198A2_E0370734" ); -- PT 0`
249			`--( X"00112233_44556677_8899AABB_CCDDEEFF" ); -- PT 1`
250			`--( X"3925841D_02DC09FB_DC118597_196A0B32" ); -- CT 0`
251			`--( X"69C4E0D8_6A7B0430_D8CDB780_70B4C55A" ); -- CT 1`
252			`--signal key_i : std_logic_vector (127 downto 000) :=`
253			`--( X"2B7E1516_28AED2A6_ABF71588_09CF4F3C" ); -- KEY 0`
254			`--( X"00010203_04050607_08090A0B_0C0D0E0F" ); -- KEY 1`
255
256			`begin`
257
258			`clk_a_i <= clock;`
259			`clk_b_i <= clock;`
260			`en_a_i <= VCC;`
261			`en_b_i <= VCC;`
262			`we_a_i <= GND;`
263			`we_b_i <= GND;`
264
265			`done_o <= done_decrypt;`
266
267			`sbox1 : bram_block_a`
268			`port map (`
269			`clk_a_i => clk_a_i,`
270			`en_a_i => en_a_i,`
271			`we_a_i => we_a_i,`
272			`di_a_i => di_a_i,`
273			`addr_a_1_i => addr_a_1_i,`
274			`addr_a_2_i => addr_a_2_i,`
275			`do_a_1_o => do_a_1_o,`
276			`do_a_2_o => do_a_2_o`
277			`);`
278			`--`
279			`sbox2 : bram_block_b`
280			`port map (`
281			`clk_b_i => clk_b_i,`
282			`we_b_i => we_b_i,`
283			`en_b_i => en_b_i,`
284			`di_b_i => di_b_i,`
285			`addr_b_1_i => addr_b_1_i,`
286			`addr_b_2_i => addr_b_2_i,`
287			`do_b_1_o => do_b_1_o,`
288			`do_b_2_o => do_b_2_o`
289			`);`
290			`--`
291			`mixcol : mix_column`
292			`port map (`
293			`s0 => mixcol_s0_i,`
294			`s1 => mixcol_s1_i,`
295			`s2 => mixcol_s2_i,`
296			`s3 => mixcol_s3_i,`
297			`mix_col => mixcol_o,`
298			`inv_mix_col => inv_mixcol_o`
299			`);`
300			`--`
301			`key : key_scheduler`
302			`port map (`
303			`clock => clock,`
304			`load => load,`
305			`key_i => key_i,`
306			`key_o => key_o,`
307			`done => done`
308			`);`
309			`--`
310			`count2bit : counter2bit`
311			`port map (`
312			`clock => clock,`
313			`clear => load,`
314			`count => counter`
315			`);`
316			`--`
317			`foldreg : folded_register`
318			`port map (`
319			`clk_i => clock,`
320			`enc_i => enc,`
321			`load_i => load,`
322			`data_i => data_i,`
323			`key_i => key_b,`
324			`di_0_i => di_0_i,`
325			`di_1_i => di_1_i,`
326			`di_2_i => di_2_i,`
327			`di_3_i => di_3_i,`
328			`do_0_o => do_0_o,`
329			`do_1_o => do_1_o,`
330			`do_2_o => do_2_o,`
331			`do_3_o => do_3_o`
332			`);`
333
334			`process(clock, clear)`
335			`begin`
336			`if (clear = '1') then`
337			`load <= '1';`
338			`elsif (clock = '1' and clock'event) then`
339			`fifo16x8 (127 downto 000) <= fifo16x8i (127 downto 000);`
340			`if (done = '1') then`
341			`load <= '1';`
342			`else`
343			`load <= '0';`
344			`end if;`
345			`end if;`
346			`end process;`
347			`--`
348			`process(clear, clock)`
349			`begin`
350			`if (clear = '1') then`
351			`key_o_srl1 <= (others => (others => '0'));`
352			`elsif (clock = '1' and clock'event) then`
353			`if (inner_round = '1') then`
354			`key_o_srl1 (43 downto 00) <= key_o_srl2 (43 downto 00);`
355			`end if;`
356			`end if;`
357			`end process;`
358			`--`
359			`process(clear, clock)`
360			`begin`
361			`if (clear = '1') then`
362			`key_o_srl1_p <= (others => (others => '0'));`
363			`elsif (clock = '1' and clock'event) then`
364			`key_o_srl1_p (03 downto 00) <= key_o_srl2_p (03 downto 00);`
365			`end if;`
366			`end process;`
367			`--`
368			`process(clear, clock)`
369			`begin`
370			`if (clear = '1') then`
371			`key_o_srl3_p <= (others => (others => '0'));`
372			`elsif (clock = '1' and clock'event) then`
373			`key_o_srl3_p (03 downto 00) <= key_o_srl4_p (03 downto 00);`
374			`end if;`
375			`end process;`
376
377			`key_o_srl2_p (03 downto 01) <= key_o_srl1_p (02 downto 00);`
378			`key_o_srl2_p (00) <= key_o;`
379			`key_o_srl4_p (02 downto 00) <= key_o_srl3_p (03 downto 01);`
380			`key_o_srl4_p (03) <= key_o;`
381			`--`
382			`inner_round <= ( counter(1) and counter(0) );`
383			`--`
384			`key_o_srl2 (39 downto 00) <= key_o_srl1 (43 downto 04);`
385
386			`key_o_srl2 (43 downto 40) <= ( key_o_srl4_p (03), key_o_srl4_p (02), key_o_srl4_p (01), key_o_srl4_p (00) ) when ( enc = '0' ) else`
387			`( key_o_srl2_p (03), key_o_srl2_p (02), key_o_srl2_p (01), key_o_srl2_p (00) );`
388
389			`key_o_srl3 (43 downto 00) <= ( key_o_srl2 (43 downto 04) &`
390			`key_i (127 downto 096) &`
391			`key_i (095 downto 064) &`
392			`key_i (063 downto 032) &`
393			`key_i (031 downto 000)`
394			`) when (done = '1') else`
395			`key_o_srl3 (43 downto 00);`
396
397			`fifo16x8o (127 downto 000) <= fifo16x8i (127 downto 000) when (done = '1') else fifo16x8o (127 downto 000);`
398			`fifo16x8i (127 downto 000) <= ( fifo16x8 (095 downto 000) & output_o );`
399
400			`data_o (127 downto 000) <= fifo16x8o (127 downto 000);`
401			`--`
402			`input (0) <= do_0_o;`
403			`input (1) <= do_1_o;`
404			`input (2) <= do_2_o;`
405			`input (3) <= do_3_o;`
406			`--`
407			`addr_a_1_i <= (enc & input(0));`
408			`addr_a_2_i <= (enc & input(1));`
409			`addr_b_1_i <= (enc & input(2));`
410			`addr_b_2_i <= (enc & input(3));`
411			`--`
412			`mixcol_s0_i <= do_a_1_o when (enc = '0') else output (31 downto 24);`
413			`mixcol_s1_i <= do_a_2_o when (enc = '0') else output (23 downto 16);`
414			`mixcol_s2_i <= do_b_1_o when (enc = '0') else output (15 downto 08);`
415			`mixcol_s3_i <= do_b_2_o when (enc = '0') else output (07 downto 00);`
416
417			`output <= mixcol_o xor key_o_srl3(key_counter_up) when (enc = '0') else`
418			`(do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_down);`
419
420			`output_o <= (do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_up) when (enc = '0') else`
421			`(do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_down);`
422
423			`di_0_i <= output (31 downto 24) when (enc = '0') else inv_mixcol_o (31 downto 24);`
424			`di_1_i <= output (23 downto 16) when (enc = '0') else inv_mixcol_o (23 downto 16);`
425			`di_2_i <= output (15 downto 08) when (enc = '0') else inv_mixcol_o (15 downto 08);`
426			`di_3_i <= output (07 downto 00) when (enc = '0') else inv_mixcol_o (07 downto 00);`
427			`--`
428			`key_b (127 downto 000) <= key_i (127 downto 000) when (enc = '0') else (key_o_srl3 (43) & key_o_srl3 (42) & key_o_srl3 (41) & key_o_srl3 (40));`
429
430			`current_key <= key_o_srl3(key_counter_down);`
431
432			`process (clock, load)`
433			`begin`
434			`if (load = '1') then`
435			`key_counter_up <= 4;`
436			`elsif (clock = '1' and clock'event) then`
437			`if (key_counter_up < 43) then`
438			`key_counter_up <= key_counter_up + 1;`
439			`else`
440			`key_counter_up <= 4;`
441			`end if;`
442			`end if;`
443			`end process;`
444			`--`
445			`process (clock, load)`
446			`begin`
447			`if (load = '1') then`
448			`key_counter_down <= 39;`
449			`elsif (clock = '1' and clock'event) then`
450			`if (key_counter_down > 0) then`
451			`key_counter_down <= key_counter_down - 1;`
452			`else`
453			`key_counter_down <= 39;`
454			`end if;`
455			`end if;`
456			`end process;`
457			`--`
458			`process(clear, done)`
459			`begin`
460			`if (clear = '1') then`
461			`counter1bit <= '0';`
462			`elsif (done = '1' and done'event) then`
463			`counter1bit <= not (counter1bit);`
464			`end if;`
465			`end process;`
466			`--`
467			`process (load, counter1bit)`
468			`begin`
469			`if (load = '1') then`
470			`done_decrypt <= '0';`
471			`elsif (counter1bit = '0' and counter1bit'event) then`
472			`done_decrypt <= '1';`
473			`end if;`
474			`end process;`
475
476			`end data_flow;`